1263363Semaste//===-- RegisterContext_x86.h -----------------------------------*- C++ -*-===// 2254721Semaste// 3254721Semaste// The LLVM Compiler Infrastructure 4254721Semaste// 5254721Semaste// This file is distributed under the University of Illinois Open Source 6254721Semaste// License. See LICENSE.TXT for details. 7254721Semaste// 8254721Semaste//===----------------------------------------------------------------------===// 9254721Semaste 10254721Semaste#ifndef liblldb_RegisterContext_x86_H_ 11254721Semaste#define liblldb_RegisterContext_x86_H_ 12254721Semaste 13263363Semaste//--------------------------------------------------------------------------- 14263363Semaste// i386 gcc, dwarf, gdb enums 15263363Semaste//--------------------------------------------------------------------------- 16263363Semaste 17263363Semaste// Register numbers seen in eh_frame (eRegisterKindGCC) 18263363Semaste// 19263363Semaste// From Jason Molenda: "gcc registers" is the register numbering used in the eh_frame 20263363Semaste// CFI. The only registers that are described in eh_frame CFI are those that are 21263363Semaste// preserved across function calls aka callee-saved aka non-volatile. And none 22263363Semaste// of the floating point registers on x86 are preserved across function calls. 23263363Semaste// 24263363Semaste// The only reason there is a "gcc register" and a "dwarf register" is because of a 25263363Semaste// mistake years and years ago with i386 where they got esp and ebp 26263363Semaste// backwards when they emitted the eh_frame instructions. Once there were 27263363Semaste// binaries In The Wild using the reversed numbering, we had to stick with it 28263363Semaste// forever. 29254721Semasteenum 30254721Semaste{ 31263363Semaste // 2nd parameter in DwarfRegNum() is regnum for exception handling on x86-32. 32263363Semaste // See http://llvm.org/docs/WritingAnLLVMBackend.html#defining-a-register 33263363Semaste gcc_eax_i386 = 0, 34263363Semaste gcc_ecx_i386, 35263363Semaste gcc_edx_i386, 36263363Semaste gcc_ebx_i386, 37263363Semaste gcc_ebp_i386, // Warning: these are switched from dwarf values 38263363Semaste gcc_esp_i386, // 39263363Semaste gcc_esi_i386, 40263363Semaste gcc_edi_i386, 41263363Semaste gcc_eip_i386, 42263363Semaste gcc_eflags_i386, 43263363Semaste gcc_st0_i386 = 12, 44263363Semaste gcc_st1_i386, 45263363Semaste gcc_st2_i386, 46263363Semaste gcc_st3_i386, 47263363Semaste gcc_st4_i386, 48263363Semaste gcc_st5_i386, 49263363Semaste gcc_st6_i386, 50263363Semaste gcc_st7_i386, 51263363Semaste gcc_xmm0_i386 = 21, 52263363Semaste gcc_xmm1_i386, 53263363Semaste gcc_xmm2_i386, 54263363Semaste gcc_xmm3_i386, 55263363Semaste gcc_xmm4_i386, 56263363Semaste gcc_xmm5_i386, 57263363Semaste gcc_xmm6_i386, 58263363Semaste gcc_xmm7_i386, 59263363Semaste gcc_mm0_i386 = 29, 60263363Semaste gcc_mm1_i386, 61263363Semaste gcc_mm2_i386, 62263363Semaste gcc_mm3_i386, 63263363Semaste gcc_mm4_i386, 64263363Semaste gcc_mm5_i386, 65263363Semaste gcc_mm6_i386, 66263363Semaste gcc_mm7_i386, 67254721Semaste}; 68254721Semaste 69263363Semaste// DWARF register numbers (eRegisterKindDWARF) 70263363Semaste// Intel's x86 or IA-32 71254721Semasteenum 72254721Semaste{ 73263363Semaste // General Purpose Registers. 74263363Semaste dwarf_eax_i386 = 0, 75263363Semaste dwarf_ecx_i386, 76263363Semaste dwarf_edx_i386, 77263363Semaste dwarf_ebx_i386, 78263363Semaste dwarf_esp_i386, 79263363Semaste dwarf_ebp_i386, 80263363Semaste dwarf_esi_i386, 81263363Semaste dwarf_edi_i386, 82263363Semaste dwarf_eip_i386, 83263363Semaste dwarf_eflags_i386, 84263363Semaste // Floating Point Registers 85263363Semaste dwarf_st0_i386 = 11, 86263363Semaste dwarf_st1_i386, 87263363Semaste dwarf_st2_i386, 88263363Semaste dwarf_st3_i386, 89263363Semaste dwarf_st4_i386, 90263363Semaste dwarf_st5_i386, 91263363Semaste dwarf_st6_i386, 92263363Semaste dwarf_st7_i386, 93263363Semaste // SSE Registers 94263363Semaste dwarf_xmm0_i386 = 21, 95263363Semaste dwarf_xmm1_i386, 96263363Semaste dwarf_xmm2_i386, 97263363Semaste dwarf_xmm3_i386, 98263363Semaste dwarf_xmm4_i386, 99263363Semaste dwarf_xmm5_i386, 100263363Semaste dwarf_xmm6_i386, 101263363Semaste dwarf_xmm7_i386, 102263363Semaste // MMX Registers 103263363Semaste dwarf_mm0_i386 = 29, 104263363Semaste dwarf_mm1_i386, 105263363Semaste dwarf_mm2_i386, 106263363Semaste dwarf_mm3_i386, 107263363Semaste dwarf_mm4_i386, 108263363Semaste dwarf_mm5_i386, 109263363Semaste dwarf_mm6_i386, 110263363Semaste dwarf_mm7_i386, 111263363Semaste dwarf_fctrl_i386 = 37, // x87 control word 112263363Semaste dwarf_fstat_i386 = 38, // x87 status word 113263363Semaste dwarf_mxcsr_i386 = 39, 114263363Semaste dwarf_es_i386 = 40, 115263363Semaste dwarf_cs_i386 = 41, 116263363Semaste dwarf_ss_i386 = 42, 117263363Semaste dwarf_ds_i386 = 43, 118263363Semaste dwarf_fs_i386 = 44, 119263363Semaste dwarf_gs_i386 = 45 120263363Semaste 121263363Semaste // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and 122263363Semaste // then differentiate based on size of the register. 123254721Semaste}; 124254721Semaste 125263363Semaste// Register numbers GDB uses (eRegisterKindGDB) 126263363Semaste// 127263363Semaste// From Jason Molenda: The "gdb numbers" are what you would see in the stabs debug format. 128254721Semasteenum 129254721Semaste{ 130263363Semaste gdb_eax_i386, 131263363Semaste gdb_ecx_i386, 132263363Semaste gdb_edx_i386, 133263363Semaste gdb_ebx_i386, 134263363Semaste gdb_esp_i386, 135263363Semaste gdb_ebp_i386, 136263363Semaste gdb_esi_i386, 137263363Semaste gdb_edi_i386, 138263363Semaste gdb_eip_i386, 139263363Semaste gdb_eflags_i386, 140263363Semaste gdb_cs_i386, 141263363Semaste gdb_ss_i386, 142263363Semaste gdb_ds_i386, 143263363Semaste gdb_es_i386, 144263363Semaste gdb_fs_i386, 145263363Semaste gdb_gs_i386, 146263363Semaste gdb_st0_i386 = 16, 147263363Semaste gdb_st1_i386, 148263363Semaste gdb_st2_i386, 149263363Semaste gdb_st3_i386, 150263363Semaste gdb_st4_i386, 151263363Semaste gdb_st5_i386, 152263363Semaste gdb_st6_i386, 153263363Semaste gdb_st7_i386, 154263363Semaste gdb_fctrl_i386, // FPU Control Word 155263363Semaste gdb_fstat_i386, // FPU Status Word 156263363Semaste gdb_ftag_i386, // FPU Tag Word 157263363Semaste gdb_fiseg_i386, // FPU IP Selector 158263363Semaste gdb_fioff_i386, // FPU IP Offset 159263363Semaste gdb_foseg_i386, // FPU Operand Pointer Selector 160263363Semaste gdb_fooff_i386, // FPU Operand Pointer Offset 161263363Semaste gdb_fop_i386, // Last Instruction Opcode 162263363Semaste gdb_xmm0_i386 = 32, 163263363Semaste gdb_xmm1_i386, 164263363Semaste gdb_xmm2_i386, 165263363Semaste gdb_xmm3_i386, 166263363Semaste gdb_xmm4_i386, 167263363Semaste gdb_xmm5_i386, 168263363Semaste gdb_xmm6_i386, 169263363Semaste gdb_xmm7_i386, 170263363Semaste gdb_mxcsr_i386 = 40, 171263363Semaste gdb_ymm0h_i386, 172263363Semaste gdb_ymm1h_i386, 173263363Semaste gdb_ymm2h_i386, 174263363Semaste gdb_ymm3h_i386, 175263363Semaste gdb_ymm4h_i386, 176263363Semaste gdb_ymm5h_i386, 177263363Semaste gdb_ymm6h_i386, 178263363Semaste gdb_ymm7h_i386, 179263363Semaste gdb_mm0_i386, 180263363Semaste gdb_mm1_i386, 181263363Semaste gdb_mm2_i386, 182263363Semaste gdb_mm3_i386, 183263363Semaste gdb_mm4_i386, 184263363Semaste gdb_mm5_i386, 185263363Semaste gdb_mm6_i386, 186263363Semaste gdb_mm7_i386, 187254721Semaste}; 188254721Semaste 189263363Semaste//--------------------------------------------------------------------------- 190263363Semaste// AMD x86_64, AMD64, Intel EM64T, or Intel 64 gcc, dwarf, gdb enums 191263363Semaste//--------------------------------------------------------------------------- 192263363Semaste 193263363Semaste// GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF) 194263363Semaste// This is the spec I used (as opposed to x86-64-abi-0.99.pdf): 195263363Semaste// http://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf 196263363Semasteenum 197263363Semaste{ 198263363Semaste // GP Registers 199263363Semaste gcc_dwarf_rax_x86_64 = 0, 200263363Semaste gcc_dwarf_rdx_x86_64, 201263363Semaste gcc_dwarf_rcx_x86_64, 202263363Semaste gcc_dwarf_rbx_x86_64, 203263363Semaste gcc_dwarf_rsi_x86_64, 204263363Semaste gcc_dwarf_rdi_x86_64, 205263363Semaste gcc_dwarf_rbp_x86_64, 206263363Semaste gcc_dwarf_rsp_x86_64, 207263363Semaste // Extended GP Registers 208263363Semaste gcc_dwarf_r8_x86_64 = 8, 209263363Semaste gcc_dwarf_r9_x86_64, 210263363Semaste gcc_dwarf_r10_x86_64, 211263363Semaste gcc_dwarf_r11_x86_64, 212263363Semaste gcc_dwarf_r12_x86_64, 213263363Semaste gcc_dwarf_r13_x86_64, 214263363Semaste gcc_dwarf_r14_x86_64, 215263363Semaste gcc_dwarf_r15_x86_64, 216263363Semaste // Return Address (RA) mapped to RIP 217263363Semaste gcc_dwarf_rip_x86_64 = 16, 218263363Semaste // SSE Vector Registers 219263363Semaste gcc_dwarf_xmm0_x86_64 = 17, 220263363Semaste gcc_dwarf_xmm1_x86_64, 221263363Semaste gcc_dwarf_xmm2_x86_64, 222263363Semaste gcc_dwarf_xmm3_x86_64, 223263363Semaste gcc_dwarf_xmm4_x86_64, 224263363Semaste gcc_dwarf_xmm5_x86_64, 225263363Semaste gcc_dwarf_xmm6_x86_64, 226263363Semaste gcc_dwarf_xmm7_x86_64, 227263363Semaste gcc_dwarf_xmm8_x86_64, 228263363Semaste gcc_dwarf_xmm9_x86_64, 229263363Semaste gcc_dwarf_xmm10_x86_64, 230263363Semaste gcc_dwarf_xmm11_x86_64, 231263363Semaste gcc_dwarf_xmm12_x86_64, 232263363Semaste gcc_dwarf_xmm13_x86_64, 233263363Semaste gcc_dwarf_xmm14_x86_64, 234263363Semaste gcc_dwarf_xmm15_x86_64, 235263363Semaste // Floating Point Registers 236263363Semaste gcc_dwarf_st0_x86_64 = 33, 237263363Semaste gcc_dwarf_st1_x86_64, 238263363Semaste gcc_dwarf_st2_x86_64, 239263363Semaste gcc_dwarf_st3_x86_64, 240263363Semaste gcc_dwarf_st4_x86_64, 241263363Semaste gcc_dwarf_st5_x86_64, 242263363Semaste gcc_dwarf_st6_x86_64, 243263363Semaste gcc_dwarf_st7_x86_64, 244263363Semaste // MMX Registers 245263363Semaste gcc_dwarf_mm0_x86_64 = 41, 246263363Semaste gcc_dwarf_mm1_x86_64, 247263363Semaste gcc_dwarf_mm2_x86_64, 248263363Semaste gcc_dwarf_mm3_x86_64, 249263363Semaste gcc_dwarf_mm4_x86_64, 250263363Semaste gcc_dwarf_mm5_x86_64, 251263363Semaste gcc_dwarf_mm6_x86_64, 252263363Semaste gcc_dwarf_mm7_x86_64, 253263363Semaste // Control and Status Flags Register 254263363Semaste gcc_dwarf_rflags_x86_64 = 49, 255263363Semaste // selector registers 256263363Semaste gcc_dwarf_es_x86_64 = 50, 257263363Semaste gcc_dwarf_cs_x86_64, 258263363Semaste gcc_dwarf_ss_x86_64, 259263363Semaste gcc_dwarf_ds_x86_64, 260263363Semaste gcc_dwarf_fs_x86_64, 261263363Semaste gcc_dwarf_gs_x86_64, 262263363Semaste // Floating point control registers 263263363Semaste gcc_dwarf_mxcsr_x86_64 = 64, // Media Control and Status 264263363Semaste gcc_dwarf_fctrl_x86_64, // x87 control word 265263363Semaste gcc_dwarf_fstat_x86_64, // x87 status word 266263363Semaste // Upper Vector Registers 267263363Semaste gcc_dwarf_ymm0h_x86_64 = 67, 268263363Semaste gcc_dwarf_ymm1h_x86_64, 269263363Semaste gcc_dwarf_ymm2h_x86_64, 270263363Semaste gcc_dwarf_ymm3h_x86_64, 271263363Semaste gcc_dwarf_ymm4h_x86_64, 272263363Semaste gcc_dwarf_ymm5h_x86_64, 273263363Semaste gcc_dwarf_ymm6h_x86_64, 274263363Semaste gcc_dwarf_ymm7h_x86_64, 275263363Semaste gcc_dwarf_ymm8h_x86_64, 276263363Semaste gcc_dwarf_ymm9h_x86_64, 277263363Semaste gcc_dwarf_ymm10h_x86_64, 278263363Semaste gcc_dwarf_ymm11h_x86_64, 279263363Semaste gcc_dwarf_ymm12h_x86_64, 280263363Semaste gcc_dwarf_ymm13h_x86_64, 281263363Semaste gcc_dwarf_ymm14h_x86_64, 282263363Semaste gcc_dwarf_ymm15h_x86_64, 283263363Semaste // AVX2 Vector Mask Registers 284263363Semaste // gcc_dwarf_k0_x86_64 = 118, 285263363Semaste // gcc_dwarf_k1_x86_64, 286263363Semaste // gcc_dwarf_k2_x86_64, 287263363Semaste // gcc_dwarf_k3_x86_64, 288263363Semaste // gcc_dwarf_k4_x86_64, 289263363Semaste // gcc_dwarf_k5_x86_64, 290263363Semaste // gcc_dwarf_k6_x86_64, 291263363Semaste // gcc_dwarf_k7_x86_64, 292263363Semaste}; 293263363Semaste 294263363Semaste// GDB Register numbers (eRegisterKindGDB) 295263363Semasteenum 296263363Semaste{ 297263363Semaste // GP Registers 298263363Semaste gdb_rax_x86_64 = 0, 299263363Semaste gdb_rbx_x86_64, 300263363Semaste gdb_rcx_x86_64, 301263363Semaste gdb_rdx_x86_64, 302263363Semaste gdb_rsi_x86_64, 303263363Semaste gdb_rdi_x86_64, 304263363Semaste gdb_rbp_x86_64, 305263363Semaste gdb_rsp_x86_64, 306263363Semaste // Extended GP Registers 307263363Semaste gdb_r8_x86_64, 308263363Semaste gdb_r9_x86_64, 309263363Semaste gdb_r10_x86_64, 310263363Semaste gdb_r11_x86_64, 311263363Semaste gdb_r12_x86_64, 312263363Semaste gdb_r13_x86_64, 313263363Semaste gdb_r14_x86_64, 314263363Semaste gdb_r15_x86_64, 315263363Semaste // Return Address (RA) mapped to RIP 316263363Semaste gdb_rip_x86_64, 317263363Semaste // Control and Status Flags Register 318263363Semaste gdb_rflags_x86_64, 319263363Semaste gdb_cs_x86_64, 320263363Semaste gdb_ss_x86_64, 321263363Semaste gdb_ds_x86_64, 322263363Semaste gdb_es_x86_64, 323263363Semaste gdb_fs_x86_64, 324263363Semaste gdb_gs_x86_64, 325263363Semaste // Floating Point Registers 326263363Semaste gdb_st0_x86_64, 327263363Semaste gdb_st1_x86_64, 328263363Semaste gdb_st2_x86_64, 329263363Semaste gdb_st3_x86_64, 330263363Semaste gdb_st4_x86_64, 331263363Semaste gdb_st5_x86_64, 332263363Semaste gdb_st6_x86_64, 333263363Semaste gdb_st7_x86_64, 334263363Semaste gdb_fctrl_x86_64, 335263363Semaste gdb_fstat_x86_64, 336263363Semaste gdb_ftag_x86_64, 337263363Semaste gdb_fiseg_x86_64, 338263363Semaste gdb_fioff_x86_64, 339263363Semaste gdb_foseg_x86_64, 340263363Semaste gdb_fooff_x86_64, 341263363Semaste gdb_fop_x86_64, 342263363Semaste // SSE Vector Registers 343263363Semaste gdb_xmm0_x86_64 = 40, 344263363Semaste gdb_xmm1_x86_64, 345263363Semaste gdb_xmm2_x86_64, 346263363Semaste gdb_xmm3_x86_64, 347263363Semaste gdb_xmm4_x86_64, 348263363Semaste gdb_xmm5_x86_64, 349263363Semaste gdb_xmm6_x86_64, 350263363Semaste gdb_xmm7_x86_64, 351263363Semaste gdb_xmm8_x86_64, 352263363Semaste gdb_xmm9_x86_64, 353263363Semaste gdb_xmm10_x86_64, 354263363Semaste gdb_xmm11_x86_64, 355263363Semaste gdb_xmm12_x86_64, 356263363Semaste gdb_xmm13_x86_64, 357263363Semaste gdb_xmm14_x86_64, 358263363Semaste gdb_xmm15_x86_64, 359263363Semaste // Floating point control registers 360263363Semaste gdb_mxcsr_x86_64 = 56, 361263363Semaste gdb_ymm0h_x86_64, 362263363Semaste gdb_ymm1h_x86_64, 363263363Semaste gdb_ymm2h_x86_64, 364263363Semaste gdb_ymm3h_x86_64, 365263363Semaste gdb_ymm4h_x86_64, 366263363Semaste gdb_ymm5h_x86_64, 367263363Semaste gdb_ymm6h_x86_64, 368263363Semaste gdb_ymm7h_x86_64, 369263363Semaste gdb_ymm8h_x86_64, 370263363Semaste gdb_ymm9h_x86_64, 371263363Semaste gdb_ymm10h_x86_64, 372263363Semaste gdb_ymm11h_x86_64, 373263363Semaste gdb_ymm12h_x86_64, 374263363Semaste gdb_ymm13h_x86_64, 375263363Semaste gdb_ymm14h_x86_64, 376263363Semaste gdb_ymm15h_x86_64 377263363Semaste}; 378263363Semaste 379263363Semaste//--------------------------------------------------------------------------- 380263363Semaste// Generic floating-point registers 381263363Semaste//--------------------------------------------------------------------------- 382263363Semaste 383263363Semastestruct MMSReg 384263363Semaste{ 385263363Semaste uint8_t bytes[10]; 386263363Semaste uint8_t pad[6]; 387263363Semaste}; 388263363Semaste 389263363Semastestruct XMMReg 390263363Semaste{ 391263363Semaste uint8_t bytes[16]; // 128-bits for each XMM register 392263363Semaste}; 393263363Semaste 394263363Semaste// i387_fxsave_struct 395263363Semastestruct FXSAVE 396263363Semaste{ 397263363Semaste uint16_t fctrl; // FPU Control Word (fcw) 398263363Semaste uint16_t fstat; // FPU Status Word (fsw) 399263363Semaste uint16_t ftag; // FPU Tag Word (ftw) 400263363Semaste uint16_t fop; // Last Instruction Opcode (fop) 401263363Semaste union 402263363Semaste { 403263363Semaste struct 404263363Semaste { 405263363Semaste uint64_t fip; // Instruction Pointer 406263363Semaste uint64_t fdp; // Data Pointer 407263363Semaste } x86_64; 408263363Semaste struct 409263363Semaste { 410263363Semaste uint32_t fioff; // FPU IP Offset (fip) 411263363Semaste uint32_t fiseg; // FPU IP Selector (fcs) 412263363Semaste uint32_t fooff; // FPU Operand Pointer Offset (foo) 413263363Semaste uint32_t foseg; // FPU Operand Pointer Selector (fos) 414263363Semaste } i386; 415263363Semaste } ptr; 416263363Semaste uint32_t mxcsr; // MXCSR Register State 417263363Semaste uint32_t mxcsrmask; // MXCSR Mask 418263363Semaste MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes 419263363Semaste XMMReg xmm[16]; // 16*16 bytes for each XMM-reg = 256 bytes 420263363Semaste uint32_t padding[24]; 421263363Semaste}; 422263363Semaste 423263363Semaste//--------------------------------------------------------------------------- 424263363Semaste// Extended floating-point registers 425263363Semaste//--------------------------------------------------------------------------- 426263363Semaste 427263363Semastestruct YMMHReg 428263363Semaste{ 429263363Semaste uint8_t bytes[16]; // 16 * 8 bits for the high bytes of each YMM register 430263363Semaste}; 431263363Semaste 432263363Semastestruct YMMReg 433263363Semaste{ 434263363Semaste uint8_t bytes[32]; // 16 * 16 bits for each YMM register 435263363Semaste}; 436263363Semaste 437263363Semastestruct YMM 438263363Semaste{ 439263363Semaste YMMReg ymm[16]; // assembled from ymmh and xmm registers 440263363Semaste}; 441263363Semaste 442263363Semastestruct XSAVE_HDR 443263363Semaste{ 444263363Semaste uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states supported by the processor 445263363Semaste uint64_t reserved1[2]; 446263363Semaste uint64_t reserved2[5]; 447263363Semaste} __attribute__((packed)); 448263363Semaste 449263363Semaste// x86 extensions to FXSAVE (i.e. for AVX processors) 450263363Semastestruct XSAVE 451263363Semaste{ 452263363Semaste FXSAVE i387; // floating point registers typical in i387_fxsave_struct 453263363Semaste XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the following extensions are usable 454263363Semaste YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes are in FXSAVE.xmm for compatibility with SSE) 455263363Semaste // Slot any extensions to the register file here 456263363Semaste} __attribute__((packed, aligned (64))); 457263363Semaste 458263363Semaste// Floating-point registers 459263363Semastestruct FPR 460263363Semaste{ 461263363Semaste // Thread state for the floating-point unit of the processor read by ptrace. 462263363Semaste union XSTATE 463263363Semaste { 464263363Semaste FXSAVE fxsave; // Generic floating-point registers. 465263363Semaste XSAVE xsave; // x86 extended processor state. 466263363Semaste } xstate; 467263363Semaste}; 468263363Semaste 469263363Semaste//--------------------------------------------------------------------------- 470263363Semaste// ptrace PTRACE_GETREGSET, PTRACE_SETREGSET structure 471263363Semaste//--------------------------------------------------------------------------- 472263363Semaste 473263363Semastestruct IOVEC 474263363Semaste{ 475263363Semaste void *iov_base; // pointer to XSAVE 476263363Semaste size_t iov_len; // sizeof(XSAVE) 477263363Semaste}; 478263363Semaste 479254721Semaste#endif 480