ArchSpec.cpp revision 263508
1//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "lldb/Core/ArchSpec.h" 11 12#include <stdio.h> 13#include <errno.h> 14 15#include <string> 16 17#include "llvm/Support/COFF.h" 18#include "llvm/Support/ELF.h" 19#include "llvm/Support/Host.h" 20#include "llvm/Support/MachO.h" 21#include "lldb/Core/RegularExpression.h" 22#include "lldb/Host/Endian.h" 23#include "lldb/Host/Host.h" 24#include "lldb/Target/Platform.h" 25 26using namespace lldb; 27using namespace lldb_private; 28 29#define ARCH_SPEC_SEPARATOR_CHAR '-' 30 31 32static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match); 33 34namespace lldb_private { 35 36 struct CoreDefinition 37 { 38 ByteOrder default_byte_order; 39 uint32_t addr_byte_size; 40 uint32_t min_opcode_byte_size; 41 uint32_t max_opcode_byte_size; 42 llvm::Triple::ArchType machine; 43 ArchSpec::Core core; 44 const char *name; 45 }; 46 47} 48 49// This core information can be looked using the ArchSpec::Core as the index 50static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] = 51{ 52 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" }, 53 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" }, 54 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" }, 55 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" }, 56 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" }, 57 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" }, 58 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" }, 59 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" }, 60 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" }, 61 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" }, 62 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" }, 63 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" }, 64 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" }, 65 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" }, 66 { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" }, 67 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" }, 68 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" }, 69 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" }, 70 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" }, 71 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" }, 72 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" }, 73 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" }, 74 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" }, 75 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" }, 76 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" }, 77 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" }, 78 { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" }, 79 80 { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, 81 82 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" }, 83 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" }, 84 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" }, 85 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" }, 86 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" }, 87 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" }, 88 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" }, 89 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" }, 90 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" }, 91 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" }, 92 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" }, 93 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" }, 94 { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" }, 95 96 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" }, 97 { eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" }, 98 99 { eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" }, 100 { eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" }, 101 102 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" }, 103 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" }, 104 { eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" }, 105 106 { eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" }, 107 { eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" }, 108 { eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" } 109}; 110 111struct ArchDefinitionEntry 112{ 113 ArchSpec::Core core; 114 uint32_t cpu; 115 uint32_t sub; 116 uint32_t cpu_mask; 117 uint32_t sub_mask; 118}; 119 120struct ArchDefinition 121{ 122 ArchitectureType type; 123 size_t num_entries; 124 const ArchDefinitionEntry *entries; 125 const char *name; 126}; 127 128 129size_t 130ArchSpec::AutoComplete (const char *name, StringList &matches) 131{ 132 uint32_t i; 133 if (name && name[0]) 134 { 135 for (i = 0; i < ArchSpec::kNumCores; ++i) 136 { 137 if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name)) 138 matches.AppendString (g_core_definitions[i].name); 139 } 140 } 141 else 142 { 143 for (i = 0; i < ArchSpec::kNumCores; ++i) 144 matches.AppendString (g_core_definitions[i].name); 145 } 146 return matches.GetSize(); 147} 148 149 150 151#define CPU_ANY (UINT32_MAX) 152 153//===----------------------------------------------------------------------===// 154// A table that gets searched linearly for matches. This table is used to 155// convert cpu type and subtypes to architecture names, and to convert 156// architecture names to cpu types and subtypes. The ordering is important and 157// allows the precedence to be set when the table is built. 158#define SUBTYPE_MASK 0x00FFFFFFu 159static const ArchDefinitionEntry g_macho_arch_entries[] = 160{ 161 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX }, 162 { ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK }, 163 { ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 164 { ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 165 { ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK }, 166 { ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK }, 167 { ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 168 { ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 169 { ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 170 { ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK }, 171 { ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK }, 172 { ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK }, 173 { ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK }, 174 { ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK }, 175 { ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK }, 176 { ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK }, 177 { ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK }, 178 { ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK }, 179 { ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 180 { ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK }, 181 { ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK }, 182 { ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK }, 183 { ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK }, 184 { ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK }, 185 { ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK }, 186 { ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK }, 187 { ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK }, 188 { ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK }, 189 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX }, 190 { ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK }, 191 { ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK }, 192 { ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK }, 193 { ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK }, 194 { ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK }, 195 { ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK }, 196 { ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK }, 197 { ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK }, 198 { ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK }, 199 { ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK }, 200 { ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK }, 201 { ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK }, 202 { ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK }, 203 { ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK }, 204 { ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK }, 205 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK }, 206 { ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK }, 207 { ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK }, 208 { ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX }, 209 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK }, 210 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK }, 211 { ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX }, 212 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files 213 { ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u }, 214 { ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u } 215}; 216static const ArchDefinition g_macho_arch_def = { 217 eArchTypeMachO, 218 sizeof(g_macho_arch_entries)/sizeof(g_macho_arch_entries[0]), 219 g_macho_arch_entries, 220 "mach-o" 221}; 222 223//===----------------------------------------------------------------------===// 224// A table that gets searched linearly for matches. This table is used to 225// convert cpu type and subtypes to architecture names, and to convert 226// architecture names to cpu types and subtypes. The ordering is important and 227// allows the precedence to be set when the table is built. 228static const ArchDefinitionEntry g_elf_arch_entries[] = 229{ 230 { ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc 231 { ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386 232 { ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated) 233 { ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC 234 { ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64 235 { ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM 236 { ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9 237 { ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64 238 { ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // MIPS 239}; 240 241static const ArchDefinition g_elf_arch_def = { 242 eArchTypeELF, 243 sizeof(g_elf_arch_entries)/sizeof(g_elf_arch_entries[0]), 244 g_elf_arch_entries, 245 "elf", 246}; 247 248static const ArchDefinitionEntry g_coff_arch_entries[] = 249{ 250 { ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386 251 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC 252 { ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU) 253 { ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM 254 { ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMV7 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7 255 { ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7 256 { ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64 257}; 258 259static const ArchDefinition g_coff_arch_def = { 260 eArchTypeCOFF, 261 sizeof(g_coff_arch_entries)/sizeof(g_coff_arch_entries[0]), 262 g_coff_arch_entries, 263 "pe-coff", 264}; 265 266//===----------------------------------------------------------------------===// 267// Table of all ArchDefinitions 268static const ArchDefinition *g_arch_definitions[] = { 269 &g_macho_arch_def, 270 &g_elf_arch_def, 271 &g_coff_arch_def 272}; 273 274static const size_t k_num_arch_definitions = 275 sizeof(g_arch_definitions) / sizeof(g_arch_definitions[0]); 276 277//===----------------------------------------------------------------------===// 278// Static helper functions. 279 280 281// Get the architecture definition for a given object type. 282static const ArchDefinition * 283FindArchDefinition (ArchitectureType arch_type) 284{ 285 for (unsigned int i = 0; i < k_num_arch_definitions; ++i) 286 { 287 const ArchDefinition *def = g_arch_definitions[i]; 288 if (def->type == arch_type) 289 return def; 290 } 291 return NULL; 292} 293 294// Get an architecture definition by name. 295static const CoreDefinition * 296FindCoreDefinition (llvm::StringRef name) 297{ 298 for (unsigned int i = 0; i < ArchSpec::kNumCores; ++i) 299 { 300 if (name.equals_lower(g_core_definitions[i].name)) 301 return &g_core_definitions[i]; 302 } 303 return NULL; 304} 305 306static inline const CoreDefinition * 307FindCoreDefinition (ArchSpec::Core core) 308{ 309 if (core >= 0 && core < ArchSpec::kNumCores) 310 return &g_core_definitions[core]; 311 return NULL; 312} 313 314// Get a definition entry by cpu type and subtype. 315static const ArchDefinitionEntry * 316FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub) 317{ 318 if (def == NULL) 319 return NULL; 320 321 const ArchDefinitionEntry *entries = def->entries; 322 for (size_t i = 0; i < def->num_entries; ++i) 323 { 324 if (entries[i].cpu == (cpu & entries[i].cpu_mask)) 325 if (entries[i].sub == (sub & entries[i].sub_mask)) 326 return &entries[i]; 327 } 328 return NULL; 329} 330 331static const ArchDefinitionEntry * 332FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core) 333{ 334 if (def == NULL) 335 return NULL; 336 337 const ArchDefinitionEntry *entries = def->entries; 338 for (size_t i = 0; i < def->num_entries; ++i) 339 { 340 if (entries[i].core == core) 341 return &entries[i]; 342 } 343 return NULL; 344} 345 346//===----------------------------------------------------------------------===// 347// Constructors and destructors. 348 349ArchSpec::ArchSpec() : 350 m_triple (), 351 m_core (kCore_invalid), 352 m_byte_order (eByteOrderInvalid) 353{ 354} 355 356ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) : 357 m_triple (), 358 m_core (kCore_invalid), 359 m_byte_order (eByteOrderInvalid) 360{ 361 if (triple_cstr) 362 SetTriple(triple_cstr, platform); 363} 364 365 366ArchSpec::ArchSpec (const char *triple_cstr) : 367 m_triple (), 368 m_core (kCore_invalid), 369 m_byte_order (eByteOrderInvalid) 370{ 371 if (triple_cstr) 372 SetTriple(triple_cstr); 373} 374 375ArchSpec::ArchSpec(const llvm::Triple &triple) : 376 m_triple (), 377 m_core (kCore_invalid), 378 m_byte_order (eByteOrderInvalid) 379{ 380 SetTriple(triple); 381} 382 383ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) : 384 m_triple (), 385 m_core (kCore_invalid), 386 m_byte_order (eByteOrderInvalid) 387{ 388 SetArchitecture (arch_type, cpu, subtype); 389} 390 391ArchSpec::~ArchSpec() 392{ 393} 394 395//===----------------------------------------------------------------------===// 396// Assignment and initialization. 397 398const ArchSpec& 399ArchSpec::operator= (const ArchSpec& rhs) 400{ 401 if (this != &rhs) 402 { 403 m_triple = rhs.m_triple; 404 m_core = rhs.m_core; 405 m_byte_order = rhs.m_byte_order; 406 } 407 return *this; 408} 409 410void 411ArchSpec::Clear() 412{ 413 m_triple = llvm::Triple(); 414 m_core = kCore_invalid; 415 m_byte_order = eByteOrderInvalid; 416} 417 418//===----------------------------------------------------------------------===// 419// Predicates. 420 421 422const char * 423ArchSpec::GetArchitectureName () const 424{ 425 const CoreDefinition *core_def = FindCoreDefinition (m_core); 426 if (core_def) 427 return core_def->name; 428 return "unknown"; 429} 430 431uint32_t 432ArchSpec::GetMachOCPUType () const 433{ 434 const CoreDefinition *core_def = FindCoreDefinition (m_core); 435 if (core_def) 436 { 437 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); 438 if (arch_def) 439 { 440 return arch_def->cpu; 441 } 442 } 443 return LLDB_INVALID_CPUTYPE; 444} 445 446uint32_t 447ArchSpec::GetMachOCPUSubType () const 448{ 449 const CoreDefinition *core_def = FindCoreDefinition (m_core); 450 if (core_def) 451 { 452 const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core); 453 if (arch_def) 454 { 455 return arch_def->sub; 456 } 457 } 458 return LLDB_INVALID_CPUTYPE; 459} 460 461llvm::Triple::ArchType 462ArchSpec::GetMachine () const 463{ 464 const CoreDefinition *core_def = FindCoreDefinition (m_core); 465 if (core_def) 466 return core_def->machine; 467 468 return llvm::Triple::UnknownArch; 469} 470 471uint32_t 472ArchSpec::GetAddressByteSize() const 473{ 474 const CoreDefinition *core_def = FindCoreDefinition (m_core); 475 if (core_def) 476 return core_def->addr_byte_size; 477 return 0; 478} 479 480ByteOrder 481ArchSpec::GetDefaultEndian () const 482{ 483 const CoreDefinition *core_def = FindCoreDefinition (m_core); 484 if (core_def) 485 return core_def->default_byte_order; 486 return eByteOrderInvalid; 487} 488 489lldb::ByteOrder 490ArchSpec::GetByteOrder () const 491{ 492 if (m_byte_order == eByteOrderInvalid) 493 return GetDefaultEndian(); 494 return m_byte_order; 495} 496 497//===----------------------------------------------------------------------===// 498// Mutators. 499 500bool 501ArchSpec::SetTriple (const llvm::Triple &triple) 502{ 503 m_triple = triple; 504 505 llvm::StringRef arch_name (m_triple.getArchName()); 506 const CoreDefinition *core_def = FindCoreDefinition (arch_name); 507 if (core_def) 508 { 509 m_core = core_def->core; 510 // Set the byte order to the default byte order for an architecture. 511 // This can be modified if needed for cases when cores handle both 512 // big and little endian 513 m_byte_order = core_def->default_byte_order; 514 } 515 else 516 { 517 Clear(); 518 } 519 520 521 return IsValid(); 522} 523 524static bool 525ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch) 526{ 527 // Accept "12-10" or "12.10" as cpu type/subtype 528 if (isdigit(triple_cstr[0])) 529 { 530 char *end = NULL; 531 errno = 0; 532 uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0); 533 if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.'))) 534 { 535 errno = 0; 536 uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0); 537 if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0'))) 538 { 539 if (arch.SetArchitecture (eArchTypeMachO, cpu, sub)) 540 { 541 if (*end == '-') 542 { 543 llvm::StringRef vendor_os (end + 1); 544 size_t dash_pos = vendor_os.find('-'); 545 if (dash_pos != llvm::StringRef::npos) 546 { 547 llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos)); 548 arch.GetTriple().setVendorName(vendor_str); 549 const size_t vendor_start_pos = dash_pos+1; 550 dash_pos = vendor_os.find('-', vendor_start_pos); 551 if (dash_pos == llvm::StringRef::npos) 552 { 553 if (vendor_start_pos < vendor_os.size()) 554 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos)); 555 } 556 else 557 { 558 arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos)); 559 } 560 } 561 } 562 return true; 563 } 564 } 565 } 566 } 567 return false; 568} 569bool 570ArchSpec::SetTriple (const char *triple_cstr) 571{ 572 if (triple_cstr && triple_cstr[0]) 573 { 574 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this)) 575 return true; 576 577 llvm::StringRef triple_stref (triple_cstr); 578 if (triple_stref.startswith (LLDB_ARCH_DEFAULT)) 579 { 580 // Special case for the current host default architectures... 581 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT)) 582 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32); 583 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT)) 584 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64); 585 else if (triple_stref.equals (LLDB_ARCH_DEFAULT)) 586 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture); 587 } 588 else 589 { 590 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref)); 591 triple_stref = normalized_triple_sstr; 592 SetTriple (llvm::Triple (triple_stref)); 593 } 594 } 595 else 596 Clear(); 597 return IsValid(); 598} 599 600bool 601ArchSpec::SetTriple (const char *triple_cstr, Platform *platform) 602{ 603 if (triple_cstr && triple_cstr[0]) 604 { 605 if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this)) 606 return true; 607 608 llvm::StringRef triple_stref (triple_cstr); 609 if (triple_stref.startswith (LLDB_ARCH_DEFAULT)) 610 { 611 // Special case for the current host default architectures... 612 if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT)) 613 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32); 614 else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT)) 615 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64); 616 else if (triple_stref.equals (LLDB_ARCH_DEFAULT)) 617 *this = Host::GetArchitecture (Host::eSystemDefaultArchitecture); 618 } 619 else 620 { 621 ArchSpec raw_arch (triple_cstr); 622 623 std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref)); 624 triple_stref = normalized_triple_sstr; 625 llvm::Triple normalized_triple (triple_stref); 626 627 const bool os_specified = normalized_triple.getOSName().size() > 0; 628 const bool vendor_specified = normalized_triple.getVendorName().size() > 0; 629 const bool env_specified = normalized_triple.getEnvironmentName().size() > 0; 630 631 // If we got an arch only, then default the vendor, os, environment 632 // to match the platform if one is supplied 633 if (!(os_specified || vendor_specified || env_specified)) 634 { 635 if (platform) 636 { 637 // If we were given a platform, use the platform's system 638 // architecture. If this is not available (might not be 639 // connected) use the first supported architecture. 640 ArchSpec compatible_arch; 641 if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch)) 642 { 643 if (compatible_arch.IsValid()) 644 { 645 const llvm::Triple &compatible_triple = compatible_arch.GetTriple(); 646 if (!vendor_specified) 647 normalized_triple.setVendor(compatible_triple.getVendor()); 648 if (!os_specified) 649 normalized_triple.setOS(compatible_triple.getOS()); 650 if (!env_specified && compatible_triple.getEnvironmentName().size()) 651 normalized_triple.setEnvironment(compatible_triple.getEnvironment()); 652 } 653 } 654 else 655 { 656 *this = raw_arch; 657 return IsValid(); 658 } 659 } 660 else 661 { 662 // No platform specified, fall back to the host system for 663 // the default vendor, os, and environment. 664 llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple()); 665 if (!vendor_specified) 666 normalized_triple.setVendor(host_triple.getVendor()); 667 if (!vendor_specified) 668 normalized_triple.setOS(host_triple.getOS()); 669 if (!env_specified && host_triple.getEnvironmentName().size()) 670 normalized_triple.setEnvironment(host_triple.getEnvironment()); 671 } 672 } 673 SetTriple (normalized_triple); 674 } 675 } 676 else 677 Clear(); 678 return IsValid(); 679} 680 681bool 682ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub) 683{ 684 m_core = kCore_invalid; 685 bool update_triple = true; 686 const ArchDefinition *arch_def = FindArchDefinition(arch_type); 687 if (arch_def) 688 { 689 const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub); 690 if (arch_def_entry) 691 { 692 const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core); 693 if (core_def) 694 { 695 m_core = core_def->core; 696 update_triple = false; 697 // Always use the architecture name because it might be more descriptive 698 // than the architecture enum ("armv7" -> llvm::Triple::arm). 699 m_triple.setArchName(llvm::StringRef(core_def->name)); 700 if (arch_type == eArchTypeMachO) 701 { 702 m_triple.setVendor (llvm::Triple::Apple); 703 704 switch (core_def->machine) 705 { 706 case llvm::Triple::arm: 707 case llvm::Triple::thumb: 708 m_triple.setOS (llvm::Triple::IOS); 709 break; 710 711 case llvm::Triple::x86: 712 case llvm::Triple::x86_64: 713 default: 714 m_triple.setOS (llvm::Triple::MacOSX); 715 break; 716 } 717 } 718 else 719 { 720 m_triple.setVendor (llvm::Triple::UnknownVendor); 721 m_triple.setOS (llvm::Triple::UnknownOS); 722 } 723 // Fall back onto setting the machine type if the arch by name failed... 724 if (m_triple.getArch () == llvm::Triple::UnknownArch) 725 m_triple.setArch (core_def->machine); 726 } 727 } 728 } 729 CoreUpdated(update_triple); 730 return IsValid(); 731} 732 733uint32_t 734ArchSpec::GetMinimumOpcodeByteSize() const 735{ 736 const CoreDefinition *core_def = FindCoreDefinition (m_core); 737 if (core_def) 738 return core_def->min_opcode_byte_size; 739 return 0; 740} 741 742uint32_t 743ArchSpec::GetMaximumOpcodeByteSize() const 744{ 745 const CoreDefinition *core_def = FindCoreDefinition (m_core); 746 if (core_def) 747 return core_def->max_opcode_byte_size; 748 return 0; 749} 750 751bool 752ArchSpec::IsExactMatch (const ArchSpec& rhs) const 753{ 754 return IsEqualTo (rhs, true); 755} 756 757bool 758ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const 759{ 760 return IsEqualTo (rhs, false); 761} 762 763bool 764ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const 765{ 766 if (GetByteOrder() != rhs.GetByteOrder()) 767 return false; 768 769 const ArchSpec::Core lhs_core = GetCore (); 770 const ArchSpec::Core rhs_core = rhs.GetCore (); 771 772 const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match); 773 774 if (core_match) 775 { 776 const llvm::Triple &lhs_triple = GetTriple(); 777 const llvm::Triple &rhs_triple = rhs.GetTriple(); 778 779 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor(); 780 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor(); 781 if (lhs_triple_vendor != rhs_triple_vendor) 782 { 783 if (exact_match) 784 { 785 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified(); 786 const bool lhs_vendor_specified = TripleVendorWasSpecified(); 787 // Both architectures had the vendor specified, so if they aren't 788 // equal then we return false 789 if (rhs_vendor_specified && lhs_vendor_specified) 790 return false; 791 } 792 793 // Only fail if both vendor types are not unknown 794 if (lhs_triple_vendor != llvm::Triple::UnknownVendor && 795 rhs_triple_vendor != llvm::Triple::UnknownVendor) 796 return false; 797 } 798 799 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS(); 800 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS(); 801 if (lhs_triple_os != rhs_triple_os) 802 { 803 if (exact_match) 804 { 805 const bool rhs_os_specified = rhs.TripleOSWasSpecified(); 806 const bool lhs_os_specified = TripleOSWasSpecified(); 807 // Both architectures had the OS specified, so if they aren't 808 // equal then we return false 809 if (rhs_os_specified && lhs_os_specified) 810 return false; 811 } 812 // Only fail if both os types are not unknown 813 if (lhs_triple_os != llvm::Triple::UnknownOS && 814 rhs_triple_os != llvm::Triple::UnknownOS) 815 return false; 816 } 817 818 const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment(); 819 const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment(); 820 821 if (lhs_triple_env != rhs_triple_env) 822 { 823 // Only fail if both environment types are not unknown 824 if (lhs_triple_env != llvm::Triple::UnknownEnvironment && 825 rhs_triple_env != llvm::Triple::UnknownEnvironment) 826 return false; 827 } 828 return true; 829 } 830 return false; 831} 832 833//===----------------------------------------------------------------------===// 834// Helper methods. 835 836void 837ArchSpec::CoreUpdated (bool update_triple) 838{ 839 const CoreDefinition *core_def = FindCoreDefinition (m_core); 840 if (core_def) 841 { 842 if (update_triple) 843 m_triple = llvm::Triple(core_def->name, "unknown", "unknown"); 844 m_byte_order = core_def->default_byte_order; 845 } 846 else 847 { 848 if (update_triple) 849 m_triple = llvm::Triple(); 850 m_byte_order = eByteOrderInvalid; 851 } 852} 853 854//===----------------------------------------------------------------------===// 855// Operators. 856 857static bool 858cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match) 859{ 860 if (core1 == core2) 861 return true; 862 863 switch (core1) 864 { 865 case ArchSpec::kCore_any: 866 return true; 867 868 case ArchSpec::kCore_arm_any: 869 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last) 870 return true; 871 if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last) 872 return true; 873 if (core2 == ArchSpec::kCore_arm_any) 874 return true; 875 break; 876 877 case ArchSpec::kCore_x86_32_any: 878 if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any)) 879 return true; 880 break; 881 882 case ArchSpec::kCore_ppc_any: 883 if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any)) 884 return true; 885 break; 886 887 case ArchSpec::kCore_ppc64_any: 888 if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any)) 889 return true; 890 break; 891 892 case ArchSpec::eCore_arm_armv6m: 893 if (!enforce_exact_match) 894 { 895 try_inverse = false; 896 if (core2 == ArchSpec::eCore_arm_armv7) 897 return true; 898 } 899 break; 900 901 case ArchSpec::eCore_arm_armv7m: 902 case ArchSpec::eCore_arm_armv7em: 903 case ArchSpec::eCore_arm_armv7f: 904 case ArchSpec::eCore_arm_armv7k: 905 case ArchSpec::eCore_arm_armv7s: 906 if (!enforce_exact_match) 907 { 908 try_inverse = false; 909 if (core2 == ArchSpec::eCore_arm_armv7) 910 return true; 911 } 912 break; 913 914 default: 915 break; 916 } 917 if (try_inverse) 918 return cores_match (core2, core1, false, enforce_exact_match); 919 return false; 920} 921 922bool 923lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs) 924{ 925 const ArchSpec::Core lhs_core = lhs.GetCore (); 926 const ArchSpec::Core rhs_core = rhs.GetCore (); 927 return lhs_core < rhs_core; 928} 929