XCoreInstrInfo.td revision 263508
1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40 41def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42 [SDNPHasChain]>; 43 44def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45 [SDNPHasChain]>; 46 47def SDT_XCoreAddress : SDTypeProfile<1, 1, 48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49 50def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51 []>; 52 53def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54 []>; 55 56def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57 []>; 58 59def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61 [SDNPHasChain, SDNPMayStore]>; 62 63// These are target-independent nodes, but have target-specific formats. 64def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66 SDTCisVT<1, i32> ]>; 67 68def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69 [SDNPHasChain, SDNPOutGlue]>; 70def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72 73def SDT_XCoreMEMBARRIER : SDTypeProfile<0, 0, []>; 74 75def XCoreMemBarrier : SDNode<"XCoreISD::MEMBARRIER", SDT_XCoreMEMBARRIER, 76 [SDNPHasChain]>; 77 78//===----------------------------------------------------------------------===// 79// Instruction Pattern Stuff 80//===----------------------------------------------------------------------===// 81 82def div4_xform : SDNodeXForm<imm, [{ 83 // Transformation function: imm/4 84 assert(N->getZExtValue() % 4 == 0); 85 return getI32Imm(N->getZExtValue()/4); 86}]>; 87 88def msksize_xform : SDNodeXForm<imm, [{ 89 // Transformation function: get the size of a mask 90 assert(isMask_32(N->getZExtValue())); 91 // look for the first non-zero bit 92 return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue())); 93}]>; 94 95def neg_xform : SDNodeXForm<imm, [{ 96 // Transformation function: -imm 97 uint32_t value = N->getZExtValue(); 98 return getI32Imm(-value); 99}]>; 100 101def bpwsub_xform : SDNodeXForm<imm, [{ 102 // Transformation function: 32-imm 103 uint32_t value = N->getZExtValue(); 104 return getI32Imm(32-value); 105}]>; 106 107def div4neg_xform : SDNodeXForm<imm, [{ 108 // Transformation function: -imm/4 109 uint32_t value = N->getZExtValue(); 110 assert(-value % 4 == 0); 111 return getI32Imm(-value/4); 112}]>; 113 114def immUs4Neg : PatLeaf<(imm), [{ 115 uint32_t value = (uint32_t)N->getZExtValue(); 116 return (-value)%4 == 0 && (-value)/4 <= 11; 117}]>; 118 119def immUs4 : PatLeaf<(imm), [{ 120 uint32_t value = (uint32_t)N->getZExtValue(); 121 return value%4 == 0 && value/4 <= 11; 122}]>; 123 124def immUsNeg : PatLeaf<(imm), [{ 125 return -((uint32_t)N->getZExtValue()) <= 11; 126}]>; 127 128def immUs : PatLeaf<(imm), [{ 129 return (uint32_t)N->getZExtValue() <= 11; 130}]>; 131 132def immU6 : PatLeaf<(imm), [{ 133 return (uint32_t)N->getZExtValue() < (1 << 6); 134}]>; 135 136def immU10 : PatLeaf<(imm), [{ 137 return (uint32_t)N->getZExtValue() < (1 << 10); 138}]>; 139 140def immU16 : PatLeaf<(imm), [{ 141 return (uint32_t)N->getZExtValue() < (1 << 16); 142}]>; 143 144def immU20 : PatLeaf<(imm), [{ 145 return (uint32_t)N->getZExtValue() < (1 << 20); 146}]>; 147 148def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 149 150def immBitp : PatLeaf<(imm), [{ 151 uint32_t value = (uint32_t)N->getZExtValue(); 152 return (value >= 1 && value <= 8) 153 || value == 16 154 || value == 24 155 || value == 32; 156}]>; 157 158def immBpwSubBitp : PatLeaf<(imm), [{ 159 uint32_t value = (uint32_t)N->getZExtValue(); 160 return (value >= 24 && value <= 31) 161 || value == 16 162 || value == 8 163 || value == 0; 164}]>; 165 166def lda16f : PatFrag<(ops node:$addr, node:$offset), 167 (add node:$addr, (shl node:$offset, 1))>; 168def lda16b : PatFrag<(ops node:$addr, node:$offset), 169 (sub node:$addr, (shl node:$offset, 1))>; 170def ldawf : PatFrag<(ops node:$addr, node:$offset), 171 (add node:$addr, (shl node:$offset, 2))>; 172def ldawb : PatFrag<(ops node:$addr, node:$offset), 173 (sub node:$addr, (shl node:$offset, 2))>; 174 175// Instruction operand types 176def pcrel_imm : Operand<i32>; 177def pcrel_imm_neg : Operand<i32> { 178 let DecoderMethod = "DecodeNegImmOperand"; 179} 180def brtarget : Operand<OtherVT>; 181def brtarget_neg : Operand<OtherVT> { 182 let DecoderMethod = "DecodeNegImmOperand"; 183} 184 185// Addressing modes 186def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 187 188// Address operands 189def MEMii : Operand<i32> { 190 let MIOperandInfo = (ops i32imm, i32imm); 191} 192 193// Jump tables. 194def InlineJT : Operand<i32> { 195 let PrintMethod = "printInlineJT"; 196} 197 198def InlineJT32 : Operand<i32> { 199 let PrintMethod = "printInlineJT32"; 200} 201 202//===----------------------------------------------------------------------===// 203// Instruction Class Templates 204//===----------------------------------------------------------------------===// 205 206// Three operand short 207 208multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 209 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 210 !strconcat(OpcStr, " $dst, $b, $c"), 211 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 212 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 213 !strconcat(OpcStr, " $dst, $b, $c"), 214 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 215} 216 217multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 218 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 219 !strconcat(OpcStr, " $dst, $b, $c"), []>; 220 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 221 !strconcat(OpcStr, " $dst, $b, $c"), []>; 222} 223 224multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 225 SDNode OpNode> { 226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 227 !strconcat(OpcStr, " $dst, $b, $c"), 228 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 229 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 230 !strconcat(OpcStr, " $dst, $b, $c"), 231 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 232} 233 234class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 236 !strconcat(OpcStr, " $dst, $b, $c"), 237 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 238 239class F3R_np<bits<5> opc, string OpcStr> : 240 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 241 !strconcat(OpcStr, " $dst, $b, $c"), []>; 242// Three operand long 243 244/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 245multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 246 SDNode OpNode> { 247 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 248 !strconcat(OpcStr, " $dst, $b, $c"), 249 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 250 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 251 !strconcat(OpcStr, " $dst, $b, $c"), 252 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 253} 254 255/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 256multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 257 SDNode OpNode> { 258 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 259 !strconcat(OpcStr, " $dst, $b, $c"), 260 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 261 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 262 !strconcat(OpcStr, " $dst, $b, $c"), 263 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 264} 265 266class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 267 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 268 !strconcat(OpcStr, " $dst, $b, $c"), 269 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 270 271// Register - U6 272// Operand register - U6 273multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 274 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 275 !strconcat(OpcStr, " $a, $b"), []>; 276 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 277 !strconcat(OpcStr, " $a, $b"), []>; 278} 279 280multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 281 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 282 !strconcat(OpcStr, " $a, $b"), []>; 283 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b), 284 !strconcat(OpcStr, " $a, $b"), []>; 285} 286 287 288// U6 289multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 290 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 291 [(OpNode immU6:$a)]>; 292 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 293 [(OpNode immU16:$a)]>; 294} 295 296multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 297 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 298 [(Int immU6:$a)]>; 299 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 300 [(Int immU16:$a)]>; 301} 302 303multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 304 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 305 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 306} 307 308// Two operand short 309 310class F2R_np<bits<6> opc, string OpcStr> : 311 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 312 !strconcat(OpcStr, " $dst, $b"), []>; 313 314// Two operand long 315 316//===----------------------------------------------------------------------===// 317// Pseudo Instructions 318//===----------------------------------------------------------------------===// 319 320let Defs = [SP], Uses = [SP] in { 321def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 322 "# ADJCALLSTACKDOWN $amt", 323 [(callseq_start timm:$amt)]>; 324def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 325 "# ADJCALLSTACKUP $amt1", 326 [(callseq_end timm:$amt1, timm:$amt2)]>; 327} 328 329def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 330 "# LDWFI $dst, $addr", 331 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 332 333def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 334 "# LDAWFI $dst, $addr", 335 [(set GRRegs:$dst, ADDRspii:$addr)]>; 336 337def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 338 "# STWFI $src, $addr", 339 [(store GRRegs:$src, ADDRspii:$addr)]>; 340 341// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 342// instruction selection into a branch sequence. 343let usesCustomInserter = 1 in { 344 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 345 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 346 "# SELECT_CC PSEUDO!", 347 [(set GRRegs:$dst, 348 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 349} 350 351let hasSideEffects = 1 in 352def Int_MemBarrier : PseudoInstXCore<(outs), (ins), "#MEMBARRIER", 353 [(XCoreMemBarrier)]>; 354 355//===----------------------------------------------------------------------===// 356// Instructions 357//===----------------------------------------------------------------------===// 358 359// Three operand short 360defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 361defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 362let neverHasSideEffects = 1 in { 363defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 364def LSS_3r : F3R_np<0b11000, "lss">; 365def LSU_3r : F3R_np<0b11001, "lsu">; 366} 367def AND_3r : F3R<0b00111, "and", and>; 368def OR_3r : F3R<0b01000, "or", or>; 369 370let mayLoad=1 in { 371def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 372 (ins GRRegs:$addr, GRRegs:$offset), 373 "ldw $dst, $addr[$offset]", []>; 374 375def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 376 (ins GRRegs:$addr, i32imm:$offset), 377 "ldw $dst, $addr[$offset]", []>; 378 379def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 380 (ins GRRegs:$addr, GRRegs:$offset), 381 "ld16s $dst, $addr[$offset]", []>; 382 383def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 384 (ins GRRegs:$addr, GRRegs:$offset), 385 "ld8u $dst, $addr[$offset]", []>; 386} 387 388let mayStore=1 in { 389def STW_l3r : _FL3R<0b000001100, (outs), 390 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 391 "stw $val, $addr[$offset]", []>; 392 393def STW_2rus : _F2RUS<0b0000, (outs), 394 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 395 "stw $val, $addr[$offset]", []>; 396} 397 398defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 399defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 400 401// The first operand is treated as an immediate since it refers to a register 402// number in another thread. 403def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 404 "set t[$c]:r$a, $b", []>; 405 406// Three operand long 407def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 408 (ins GRRegs:$addr, GRRegs:$offset), 409 "ldaw $dst, $addr[$offset]", 410 [(set GRRegs:$dst, 411 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 412 413let neverHasSideEffects = 1 in 414def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 415 (ins GRRegs:$addr, i32imm:$offset), 416 "ldaw $dst, $addr[$offset]", []>; 417 418def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 419 (ins GRRegs:$addr, GRRegs:$offset), 420 "ldaw $dst, $addr[-$offset]", 421 [(set GRRegs:$dst, 422 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 423 424let neverHasSideEffects = 1 in 425def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 426 (ins GRRegs:$addr, i32imm:$offset), 427 "ldaw $dst, $addr[-$offset]", []>; 428 429def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 430 (ins GRRegs:$addr, GRRegs:$offset), 431 "lda16 $dst, $addr[$offset]", 432 [(set GRRegs:$dst, 433 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 434 435def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 436 (ins GRRegs:$addr, GRRegs:$offset), 437 "lda16 $dst, $addr[-$offset]", 438 [(set GRRegs:$dst, 439 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 440 441def MUL_l3r : FL3R<0b001111100, "mul", mul>; 442// Instructions which may trap are marked as side effecting. 443let hasSideEffects = 1 in { 444def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 445def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 446def REMS_l3r : FL3R<0b110001100, "rems", srem>; 447def REMU_l3r : FL3R<0b110011100, "remu", urem>; 448} 449def XOR_l3r : FL3R<0b000011100, "xor", xor>; 450defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 451 452let Constraints = "$src1 = $dst" in 453def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 454 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 455 "crc32 $dst, $src2, $src3", 456 [(set GRRegs:$dst, 457 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 458 GRRegs:$src3))]>; 459 460let mayStore=1 in { 461def ST16_l3r : _FL3R<0b100001100, (outs), 462 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 463 "st16 $val, $addr[$offset]", []>; 464 465def ST8_l3r : _FL3R<0b100011100, (outs), 466 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 467 "st8 $val, $addr[$offset]", []>; 468} 469 470def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 471 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 472 []>; 473 474def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 475 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 476 "outpw res[$b], $a, $c", []>; 477 478// Four operand long 479let Constraints = "$e = $a,$f = $b" in { 480def MACCU_l4r : _FL4RSrcDstSrcDst< 481 0b000001, (outs GRRegs:$a, GRRegs:$b), 482 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 483 484def MACCS_l4r : _FL4RSrcDstSrcDst< 485 0b000010, (outs GRRegs:$a, GRRegs:$b), 486 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 487} 488 489let Constraints = "$e = $b" in 490def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 491 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 492 "crc8 $b, $a, $c, $d", []>; 493 494// Five operand long 495 496def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 497 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 498 "ladd $dst2, $dst1, $src1, $src2, $src3", 499 []>; 500 501def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 502 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 503 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 504 505def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 506 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 507 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 508 509// Six operand long 510 511def LMUL_l6r : _FL6R< 512 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 513 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 514 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 515 516// Register - U6 517 518//let Uses = [DP] in ... 519let neverHasSideEffects = 1, isReMaterializable = 1 in 520def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 521 "ldaw $a, dp[$b]", []>; 522 523let isReMaterializable = 1 in 524def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins i32imm:$b), 525 "ldaw $a, dp[$b]", 526 [(set RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 527 528let mayLoad=1 in 529def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 530 "ldw $a, dp[$b]", []>; 531 532def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins i32imm:$b), 533 "ldw $a, dp[$b]", 534 [(set RRegs:$a, (load (dprelwrapper tglobaladdr:$b)))]>; 535 536let mayStore=1 in 537def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 538 "stw $a, dp[$b]", []>; 539 540def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, i32imm:$b), 541 "stw $a, dp[$b]", 542 [(store RRegs:$a, (dprelwrapper tglobaladdr:$b))]>; 543 544//let Uses = [CP] in .. 545let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in { 546def LDWCP_ru6 : _FRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 547 "ldw $a, cp[$b]", []>; 548def LDWCP_lru6: _FLRU6<0b011011, (outs RRegs:$a), (ins i32imm:$b), 549 "ldw $a, cp[$b]", 550 [(set RRegs:$a, (load (cprelwrapper tglobaladdr:$b)))]>; 551} 552 553let Uses = [SP] in { 554let mayStore=1 in { 555def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 556 "stw $a, sp[$b]", 557 [(XCoreStwsp RRegs:$a, immU6:$b)]>; 558 559def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 560 "stw $a, sp[$b]", 561 [(XCoreStwsp RRegs:$a, immU16:$b)]>; 562} 563 564let mayLoad=1 in { 565def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 566 "ldw $a, sp[$b]", []>; 567 568def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 569 "ldw $a, sp[$b]", []>; 570} 571 572let neverHasSideEffects = 1 in { 573def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 574 "ldaw $a, sp[$b]", []>; 575 576def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 577 "ldaw $a, sp[$b]", []>; 578} 579} 580 581let isReMaterializable = 1 in { 582def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 583 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 584 585def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 586 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 587} 588 589def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 590 "setc res[$a], $b", 591 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 592 593def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 594 "setc res[$a], $b", 595 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 596 597// Operand register - U6 598let isBranch = 1, isTerminator = 1 in { 599defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 600defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 601defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 602defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 603} 604 605// U6 606let Defs = [SP], Uses = [SP] in { 607let neverHasSideEffects = 1 in 608defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 609 610let mayStore = 1 in 611defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 612 613let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 614defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 615} 616} 617 618let neverHasSideEffects = 1 in 619defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 620 621let Uses = [R11], isCall=1 in 622defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 623 624let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 625def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 626 627def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>; 628 629def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 630 631def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 632} 633 634//let Uses = [CP] in ... 635let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 636def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 637 []>; 638 639let Defs = [R11], isReMaterializable = 1 in 640def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins i32imm:$a), "ldaw r11, cp[$a]", 641 [(set R11, (cprelwrapper tglobaladdr:$a))]>; 642 643let Defs = [R11] in 644defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 645 646defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 647 648defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 649 650// setsr may cause a branch if it is used to enable events. clrsr may 651// branch if it is executed while events are enabled. 652let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 653 isCodeGenOnly = 1 in { 654defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 655defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 656} 657 658defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 659 660let Uses = [SP], Defs = [SP], mayStore = 1 in 661defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 662 663let Uses = [SP], Defs = [SP], mayLoad = 1 in 664defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 665 666// U10 667 668let Defs = [R11], isReMaterializable = 1 in { 669let neverHasSideEffects = 1 in 670def LDAPF_u10 : _FU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", []>; 671 672def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 673 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 674 675let neverHasSideEffects = 1 in 676def LDAPB_u10 : _FU10<0b110111, (outs), (ins pcrel_imm_neg:$a), "ldap r11, $a", 677 []>; 678 679let neverHasSideEffects = 1 in 680def LDAPB_lu10 : _FLU10<0b110111, (outs), (ins pcrel_imm_neg:$a), 681 "ldap r11, $a", 682 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 683 684let isCodeGenOnly = 1 in 685def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins pcrel_imm:$a), "ldap r11, $a", 686 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 687} 688 689let isCall=1, 690// All calls clobber the link register and the non-callee-saved registers: 691Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 692def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 693 694def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 695 696def BLRF_u10 : _FU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 697 [(XCoreBranchLink immU10:$a)]>; 698 699def BLRF_lu10 : _FLU10<0b110100, (outs), (ins pcrel_imm:$a), "bl $a", 700 [(XCoreBranchLink immU20:$a)]>; 701 702def BLRB_u10 : _FU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 703 704def BLRB_lu10 : _FLU10<0b110101, (outs), (ins pcrel_imm_neg:$a), "bl $a", []>; 705} 706 707let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 708 neverHasSideEffects = 1 in { 709def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 710 711def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 712 []>; 713} 714 715// Two operand short 716def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 717 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 718 719def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 720 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 721 722let Constraints = "$src1 = $dst" in { 723def SEXT_rus : 724 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 725 "sext $dst, $src2", 726 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 727 immBitp:$src2))]>; 728 729def SEXT_2r : 730 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 731 "sext $dst, $src2", 732 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 733 734def ZEXT_rus : 735 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 736 "zext $dst, $src2", 737 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 738 immBitp:$src2))]>; 739 740def ZEXT_2r : 741 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 742 "zext $dst, $src2", 743 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 744 745def ANDNOT_2r : 746 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 747 "andnot $dst, $src2", 748 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 749} 750 751let isReMaterializable = 1, neverHasSideEffects = 1 in 752def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 753 "mkmsk $dst, $size", []>; 754 755def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 756 "mkmsk $dst, $size", 757 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 758 759def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 760 "getr $dst, $type", 761 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 762 763def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 764 "getts $dst, res[$r]", 765 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 766 767def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 768 "setpt res[$r], $val", 769 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 770 771def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 772 "outct res[$r], $val", 773 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 774 775def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 776 "outct res[$r], $val", 777 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 778 779def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 780 "outt res[$r], $val", 781 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 782 783def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 784 "out res[$r], $val", 785 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 786 787let Constraints = "$src = $dst" in 788def OUTSHR_2r : 789 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 790 "outshr res[$r], $src", 791 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 792 793def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 794 "inct $dst, res[$r]", 795 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 796 797def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 798 "int $dst, res[$r]", 799 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 800 801def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 802 "in $dst, res[$r]", 803 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 804 805let Constraints = "$src = $dst" in 806def INSHR_2r : 807 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 808 "inshr $dst, res[$r]", 809 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 810 811def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 812 "chkct res[$r], $val", 813 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 814 815def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 816 "chkct res[$r], $val", 817 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 818 819def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 820 "testct $dst, res[$src]", 821 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 822 823def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 824 "testwct $dst, res[$src]", 825 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 826 827def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 828 "setd res[$r], $val", 829 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 830 831def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 832 "setpsc res[$src1], $src2", 833 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 834 835def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 836 "getst $dst, res[$r]", 837 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 838 839def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 840 "init t[$t]:sp, $src", 841 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 842 843def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 844 "init t[$t]:pc, $src", 845 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 846 847def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 848 "init t[$t]:cp, $src", 849 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 850 851def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 852 "init t[$t]:dp, $src", 853 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 854 855def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 856 "peek $dst, res[$src]", 857 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 858 859def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 860 "endin $dst, res[$src]", 861 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 862 863def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 864 "eef $a, res[$b]", []>; 865 866def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 867 "eet $a, res[$b]", []>; 868 869def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 870 "tsetmr r$a, $b", []>; 871 872// Two operand long 873def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 874 "bitrev $dst, $src", 875 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 876 877def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 878 "byterev $dst, $src", 879 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 880 881def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 882 "clz $dst, $src", 883 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 884 885def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 886 "getd $dst, res[$src]", []>; 887 888def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 889 "getn $dst, res[$src]", []>; 890 891def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 892 "setc res[$r], $val", 893 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 894 895def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 896 "settw res[$r], $val", 897 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 898 899def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 900 "get $dst, ps[$src]", 901 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 902 903def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 904 "set ps[$src1], $src2", 905 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 906 907def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 908 "init t[$t]:lr, $src", 909 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 910 911def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 912 "setclk res[$src1], $src2", 913 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 914 915def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 916 "setn res[$src1], $src2", []>; 917 918def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 919 "setrdy res[$src1], $src2", 920 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 921 922def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 923 "testlcl $dst, res[$src]", []>; 924 925// One operand short 926def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 927 "msync res[$a]", 928 [(int_xcore_msync GRRegs:$a)]>; 929def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 930 "mjoin res[$a]", 931 [(int_xcore_mjoin GRRegs:$a)]>; 932 933let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 934def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 935 "bau $a", 936 [(brind GRRegs:$a)]>; 937 938let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 939def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 940 "bru $i\n$t", 941 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 942 943let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 944def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 945 "bru $i\n$t", 946 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 947 948let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 949def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 950 951let Defs=[SP], neverHasSideEffects=1 in 952def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 953 954let neverHasSideEffects=1 in 955def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 956 957let neverHasSideEffects=1 in 958def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 959 960let hasCtrlDep = 1 in 961def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 962 "ecallt $a", 963 []>; 964 965let hasCtrlDep = 1 in 966def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 967 "ecallf $a", 968 []>; 969 970let isCall=1, 971// All calls clobber the link register and the non-callee-saved registers: 972Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 973def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 974 "bla $a", 975 [(XCoreBranchLink GRRegs:$a)]>; 976} 977 978def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 979 "syncr res[$a]", 980 [(int_xcore_syncr GRRegs:$a)]>; 981 982def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 983 "freer res[$a]", 984 [(int_xcore_freer GRRegs:$a)]>; 985 986let Uses=[R11] in { 987def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 988 "setv res[$a], r11", 989 [(int_xcore_setv GRRegs:$a, R11)]>; 990 991def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 992 "setev res[$a], r11", 993 [(int_xcore_setev GRRegs:$a, R11)]>; 994} 995 996def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 997 998def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>; 999 1000def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 1001 "eeu res[$a]", 1002 [(int_xcore_eeu GRRegs:$a)]>; 1003 1004def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 1005 1006def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 1007 1008def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 1009 1010def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 1011 1012def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>; 1013 1014// Zero operand short 1015 1016def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 1017 1018def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 1019 1020let Defs = [SP], Uses = [SP] in 1021def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1022 1023let Defs = [SP] in 1024def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1025 1026def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1027 1028def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1029 1030let Defs = [R11] in { 1031def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1032 "get r11, id", 1033 [(set R11, (int_xcore_getid))]>; 1034 1035def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1036 "get r11, ed", 1037 [(set R11, (int_xcore_geted))]>; 1038 1039def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1040 "get r11, et", 1041 [(set R11, (int_xcore_getet))]>; 1042 1043def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1044 "get r11, kep", []>; 1045 1046def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1047 "get r11, ksp", []>; 1048} 1049 1050let Defs = [SP] in 1051def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1052 1053let Uses = [SP], mayLoad = 1 in { 1054def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1055 1056def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1057 1058def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1059 1060def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1061} 1062 1063let Uses=[R11] in 1064def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1065 1066def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1067 "ssync", 1068 [(int_xcore_ssync)]>; 1069 1070let Uses = [SP], mayStore = 1 in { 1071def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1072 1073def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1074 1075def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1076 1077def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1078} 1079 1080let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1081 hasSideEffects = 1 in 1082def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1083 "waiteu", 1084 [(brind (int_xcore_waitevent))]>; 1085 1086//===----------------------------------------------------------------------===// 1087// Non-Instruction Patterns 1088//===----------------------------------------------------------------------===// 1089 1090def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>; 1091def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1092 1093/// sext_inreg 1094def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1095def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1096def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1097 1098/// loads 1099def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1100 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1101def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1102 1103def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1104 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1105def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1106 1107def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1108 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1109def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1110 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1111def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1112 1113/// anyext 1114def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1115 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1116def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1117def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1118 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1119def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1120 1121/// stores 1122def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1123 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1124def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1125 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1126 1127def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1128 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1129def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1130 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1131 1132def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1133 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1134def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1135 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1136def : Pat<(store GRRegs:$val, GRRegs:$addr), 1137 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1138 1139/// cttz 1140def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1141 1142/// trap 1143def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1144 1145/// 1146/// branch patterns 1147/// 1148 1149// unconditional branch 1150def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1151 1152// direct match equal/notequal zero brcond 1153def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1154 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1155def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1156 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1157 1158def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1159 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1160def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1161 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1162def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1163 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1164def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1165 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1166def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1167 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1168def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1169 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1170 1171// generic brcond pattern 1172def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1173 1174 1175/// 1176/// Select patterns 1177/// 1178 1179// direct match equal/notequal zero select 1180def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1181 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1182 1183def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1184 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1185 1186def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1187 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1188def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1189 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1190def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1191 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1192def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1193 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1194def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1195 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1196def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1197 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1198 1199/// 1200/// setcc patterns, only matched when none of the above brcond 1201/// patterns match 1202/// 1203 1204// setcc 2 register operands 1205def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1206 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1207def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1208 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1209 1210def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1211 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1212def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1213 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1214 1215def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1216 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1217def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1218 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1219 1220def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1221 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1222def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1223 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1224 1225def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1226 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1227 1228def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1229 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1230 1231// setcc reg/imm operands 1232def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1233 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1234def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1235 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1236 1237// misc 1238def : Pat<(add GRRegs:$addr, immUs4:$offset), 1239 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1240 1241def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1242 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1243 1244def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1245 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1246 1247// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1248def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1249 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1250 1251def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1252 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1253 1254/// 1255/// Some peepholes 1256/// 1257 1258def : Pat<(mul GRRegs:$src, 3), 1259 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1260 1261def : Pat<(mul GRRegs:$src, 5), 1262 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1263 1264def : Pat<(mul GRRegs:$src, -3), 1265 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1266 1267// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1268def : Pat<(sra GRRegs:$src, 31), 1269 (ASHR_l2rus GRRegs:$src, 32)>; 1270 1271def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1272 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1273 1274// setge X, 0 is canonicalized to setgt X, -1 1275def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1276 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1277 1278def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1279 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1280 1281def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1282 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1283 1284def : Pat<(setgt GRRegs:$lhs, -1), 1285 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1286 1287def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1288 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1289