X86InstrFPStack.td revision 263508
1//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 x87 FPU instruction set, defining the 11// instructions, and properties of the instructions which are needed for code 12// generation, machine code emission, and analysis. 13// 14//===----------------------------------------------------------------------===// 15 16//===----------------------------------------------------------------------===// 17// FPStack specific DAG Nodes. 18//===----------------------------------------------------------------------===// 19 20def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, 21 SDTCisVT<1, f80>]>; 22def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, 23 SDTCisPtrTy<1>, 24 SDTCisVT<2, OtherVT>]>; 25def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, 26 SDTCisPtrTy<1>, 27 SDTCisVT<2, OtherVT>]>; 28def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, 29 SDTCisVT<2, OtherVT>]>; 30def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 31def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 32 33def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 34 35def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 36 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 37def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 38 [SDNPHasChain, SDNPInGlue, SDNPMayStore, 39 SDNPMemOperand]>; 40def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 41 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 42def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, 43 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, 44 SDNPMemOperand]>; 45def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; 46def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, 47 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 48def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, 49 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 50def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, 51 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 52def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 53 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 54 SDNPMemOperand]>; 55 56//===----------------------------------------------------------------------===// 57// FPStack pattern fragments 58//===----------------------------------------------------------------------===// 59 60def fpimm0 : PatLeaf<(fpimm), [{ 61 return N->isExactlyValue(+0.0); 62}]>; 63 64def fpimmneg0 : PatLeaf<(fpimm), [{ 65 return N->isExactlyValue(-0.0); 66}]>; 67 68def fpimm1 : PatLeaf<(fpimm), [{ 69 return N->isExactlyValue(+1.0); 70}]>; 71 72def fpimmneg1 : PatLeaf<(fpimm), [{ 73 return N->isExactlyValue(-1.0); 74}]>; 75 76// Some 'special' instructions 77let usesCustomInserter = 1 in { // Expanded after instruction selection. 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), 79 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; 80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), 81 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; 82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), 83 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; 84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), 85 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; 86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), 87 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; 88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), 89 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; 90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), 91 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; 92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), 93 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; 94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), 95 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; 96} 97 98// All FP Stack operations are represented with four instructions here. The 99// first three instructions, generated by the instruction selector, use "RFP32" 100// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, 101// 64-bit or 80-bit floating point values. These sizes apply to the values, 102// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be 103// copied to each other without losing information. These instructions are all 104// pseudo instructions and use the "_Fp" suffix. 105// In some cases there are additional variants with a mixture of different 106// register sizes. 107// The second instruction is defined with FPI, which is the actual instruction 108// emitted by the assembler. These use "RST" registers, although frequently 109// the actual register(s) used are implicit. These are always 80 bits. 110// The FP stackifier pass converts one to the other after register allocation 111// occurs. 112// 113// Note that the FpI instruction should have instruction selection info (e.g. 114// a pattern) and the FPI instruction should have emission info (e.g. opcode 115// encoding and asm printing info). 116 117// Pseudo Instruction for FP stack return values. 118def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; 119 120// FpIf32, FpIf64 - Floating Point Pseudo Instruction template. 121// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. 122// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. 123// f80 instructions cannot use SSE and use neither of these. 124class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 125 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; 126class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 127 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; 128 129// Factoring for arithmetic. 130multiclass FPBinary_rr<SDNode OpNode> { 131// Register op register -> register 132// These are separated out because they have no reversed form. 133def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, 134 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; 135def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, 136 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; 137def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, 138 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; 139} 140// The FopST0 series are not included here because of the irregularities 141// in where the 'r' goes in assembly output. 142// These instructions cannot address 80-bit memory. 143multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { 144// ST(0) = ST(0) + [mem] 145def _Fp32m : FpIf32<(outs RFP32:$dst), 146 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, 147 [(set RFP32:$dst, 148 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; 149def _Fp64m : FpIf64<(outs RFP64:$dst), 150 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, 151 [(set RFP64:$dst, 152 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; 153def _Fp64m32: FpIf64<(outs RFP64:$dst), 154 (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, 155 [(set RFP64:$dst, 156 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>; 157def _Fp80m32: FpI_<(outs RFP80:$dst), 158 (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, 159 [(set RFP80:$dst, 160 (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>; 161def _Fp80m64: FpI_<(outs RFP80:$dst), 162 (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, 163 [(set RFP80:$dst, 164 (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>; 165def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), 166 !strconcat("f", asmstring, "{s}\t$src")> { 167 let mayLoad = 1; 168} 169def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), 170 !strconcat("f", asmstring, "{l}\t$src")> { 171 let mayLoad = 1; 172} 173// ST(0) = ST(0) + [memint] 174def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), 175 OneArgFPRW, 176 [(set RFP32:$dst, (OpNode RFP32:$src1, 177 (X86fild addr:$src2, i16)))]>; 178def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), 179 OneArgFPRW, 180 [(set RFP32:$dst, (OpNode RFP32:$src1, 181 (X86fild addr:$src2, i32)))]>; 182def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), 183 OneArgFPRW, 184 [(set RFP64:$dst, (OpNode RFP64:$src1, 185 (X86fild addr:$src2, i16)))]>; 186def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), 187 OneArgFPRW, 188 [(set RFP64:$dst, (OpNode RFP64:$src1, 189 (X86fild addr:$src2, i32)))]>; 190def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), 191 OneArgFPRW, 192 [(set RFP80:$dst, (OpNode RFP80:$src1, 193 (X86fild addr:$src2, i16)))]>; 194def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), 195 OneArgFPRW, 196 [(set RFP80:$dst, (OpNode RFP80:$src1, 197 (X86fild addr:$src2, i32)))]>; 198def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), 199 !strconcat("fi", asmstring, "{s}\t$src")> { 200 let mayLoad = 1; 201} 202def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), 203 !strconcat("fi", asmstring, "{l}\t$src")> { 204 let mayLoad = 1; 205} 206} 207 208let Defs = [FPSW] in { 209defm ADD : FPBinary_rr<fadd>; 210defm SUB : FPBinary_rr<fsub>; 211defm MUL : FPBinary_rr<fmul>; 212defm DIV : FPBinary_rr<fdiv>; 213defm ADD : FPBinary<fadd, MRM0m, "add">; 214defm SUB : FPBinary<fsub, MRM4m, "sub">; 215defm SUBR: FPBinary<fsub ,MRM5m, "subr">; 216defm MUL : FPBinary<fmul, MRM1m, "mul">; 217defm DIV : FPBinary<fdiv, MRM6m, "div">; 218defm DIVR: FPBinary<fdiv, MRM7m, "divr">; 219} 220 221class FPST0rInst<bits<8> o, string asm> 222 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8; 223class FPrST0Inst<bits<8> o, string asm> 224 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC; 225class FPrST0PInst<bits<8> o, string asm> 226 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE; 227 228// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion 229// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, 230// we have to put some 'r's in and take them out of weird places. 231def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">; 232def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">; 233def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">; 234def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">; 235def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, st(0)}">; 236def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">; 237def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">; 238def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; 239def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">; 240def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">; 241def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, st(0)}">; 242def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">; 243def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">; 244def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; 245def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">; 246def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">; 247def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; 248def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">; 249 250def COM_FST0r : FPST0rInst <0xD0, "fcom\t$op">; 251def COMP_FST0r : FPST0rInst <0xD8, "fcomp\t$op">; 252 253// Unary operations. 254multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> { 255def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, 256 [(set RFP32:$dst, (OpNode RFP32:$src))]>; 257def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, 258 [(set RFP64:$dst, (OpNode RFP64:$src))]>; 259def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, 260 [(set RFP80:$dst, (OpNode RFP80:$src))]>; 261def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9; 262} 263 264let Defs = [FPSW] in { 265defm CHS : FPUnary<fneg, 0xE0, "fchs">; 266defm ABS : FPUnary<fabs, 0xE1, "fabs">; 267defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">; 268defm SIN : FPUnary<fsin, 0xFE, "fsin">; 269defm COS : FPUnary<fcos, 0xFF, "fcos">; 270 271let neverHasSideEffects = 1 in { 272def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; 273def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; 274def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; 275} 276def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9; 277} // Defs = [FPSW] 278 279// Versions of FP instructions that take a single memory operand. Added for the 280// disassembler; remove as they are included with patterns elsewhere. 281def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; 282def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; 283 284def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; 285def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">; 286 287def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; 288def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; 289 290def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; 291def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; 292 293def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; 294def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">; 295def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">; 296 297def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; 298def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; 299 300def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">; 301def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">; 302 303// Floating point cmovs. 304class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 305 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; 306class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : 307 FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; 308 309multiclass FPCMov<PatLeaf cc> { 310 def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), 311 CondMovFP, 312 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, 313 cc, EFLAGS))]>; 314 def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), 315 CondMovFP, 316 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, 317 cc, EFLAGS))]>; 318 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), 319 CondMovFP, 320 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, 321 cc, EFLAGS))]>, 322 Requires<[HasCMov]>; 323} 324 325let Defs = [FPSW] in { 326let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { 327defm CMOVB : FPCMov<X86_COND_B>; 328defm CMOVBE : FPCMov<X86_COND_BE>; 329defm CMOVE : FPCMov<X86_COND_E>; 330defm CMOVP : FPCMov<X86_COND_P>; 331defm CMOVNB : FPCMov<X86_COND_AE>; 332defm CMOVNBE: FPCMov<X86_COND_A>; 333defm CMOVNE : FPCMov<X86_COND_NE>; 334defm CMOVNP : FPCMov<X86_COND_NP>; 335} // Uses = [EFLAGS], Constraints = "$src1 = $dst" 336 337let Predicates = [HasCMov] in { 338// These are not factored because there's no clean way to pass DA/DB. 339def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), 340 "fcmovb\t{$op, %st(0)|st(0), $op}">, DA; 341def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), 342 "fcmovbe\t{$op, %st(0)|st(0), $op}">, DA; 343def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), 344 "fcmove\t{$op, %st(0)|st(0), $op}">, DA; 345def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), 346 "fcmovu\t{$op, %st(0)|st(0), $op}">, DA; 347def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins), 348 "fcmovnb\t{$op, %st(0)|st(0), $op}">, DB; 349def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins), 350 "fcmovnbe\t{$op, %st(0)|st(0), $op}">, DB; 351def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins), 352 "fcmovne\t{$op, %st(0)|st(0), $op}">, DB; 353def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins), 354 "fcmovnu\t{$op, %st(0)|st(0), $op}">, DB; 355} // Predicates = [HasCMov] 356 357// Floating point loads & stores. 358let canFoldAsLoad = 1 in { 359def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, 360 [(set RFP32:$dst, (loadf32 addr:$src))]>; 361let isReMaterializable = 1 in 362 def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, 363 [(set RFP64:$dst, (loadf64 addr:$src))]>; 364def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, 365 [(set RFP80:$dst, (loadf80 addr:$src))]>; 366} 367def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, 368 [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; 369def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, 370 [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; 371def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, 372 [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; 373def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, 374 [(set RFP32:$dst, (X86fild addr:$src, i16))]>; 375def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, 376 [(set RFP32:$dst, (X86fild addr:$src, i32))]>; 377def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, 378 [(set RFP32:$dst, (X86fild addr:$src, i64))]>; 379def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, 380 [(set RFP64:$dst, (X86fild addr:$src, i16))]>; 381def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, 382 [(set RFP64:$dst, (X86fild addr:$src, i32))]>; 383def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, 384 [(set RFP64:$dst, (X86fild addr:$src, i64))]>; 385def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, 386 [(set RFP80:$dst, (X86fild addr:$src, i16))]>; 387def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, 388 [(set RFP80:$dst, (X86fild addr:$src, i32))]>; 389def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, 390 [(set RFP80:$dst, (X86fild addr:$src, i64))]>; 391 392def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, 393 [(store RFP32:$src, addr:$op)]>; 394def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, 395 [(truncstoref32 RFP64:$src, addr:$op)]>; 396def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, 397 [(store RFP64:$src, addr:$op)]>; 398def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, 399 [(truncstoref32 RFP80:$src, addr:$op)]>; 400def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, 401 [(truncstoref64 RFP80:$src, addr:$op)]>; 402// FST does not support 80-bit memory target; FSTP must be used. 403 404let mayStore = 1, neverHasSideEffects = 1 in { 405def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; 406def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; 407def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; 408def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; 409def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; 410} 411def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, 412 [(store RFP80:$src, addr:$op)]>; 413let mayStore = 1, neverHasSideEffects = 1 in { 414def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; 415def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; 416def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; 417def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; 418def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; 419def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; 420def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; 421def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; 422def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; 423} 424 425let mayLoad = 1, SchedRW = [WriteLoad] in { 426def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", 427 IIC_FLD>; 428def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", 429 IIC_FLD>; 430def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", 431 IIC_FLD80>; 432def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", 433 IIC_FILD>; 434def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", 435 IIC_FILD>; 436def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", 437 IIC_FILD>; 438} 439let mayStore = 1, SchedRW = [WriteStore] in { 440def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", 441 IIC_FST>; 442def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", 443 IIC_FST>; 444def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", 445 IIC_FST>; 446def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", 447 IIC_FST>; 448def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", 449 IIC_FST80>; 450def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", 451 IIC_FIST>; 452def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", 453 IIC_FIST>; 454def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", 455 IIC_FIST>; 456def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", 457 IIC_FIST>; 458def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", 459 IIC_FIST>; 460} 461 462// FISTTP requires SSE3 even though it's a FPStack op. 463let Predicates = [HasSSE3] in { 464def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, 465 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; 466def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, 467 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; 468def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, 469 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; 470def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, 471 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; 472def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, 473 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; 474def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, 475 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; 476def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, 477 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; 478def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, 479 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; 480def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, 481 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; 482} // Predicates = [HasSSE3] 483 484let mayStore = 1, SchedRW = [WriteStore] in { 485def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", 486 IIC_FST>; 487def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", 488 IIC_FST>; 489def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), 490 "fisttp{ll}\t$dst", IIC_FST>; 491} 492 493// FP Stack manipulation instructions. 494let SchedRW = [WriteMove] in { 495def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op", 496 IIC_FLD>, D9; 497def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op", 498 IIC_FST>, DD; 499def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op", 500 IIC_FST>, DD; 501def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op", 502 IIC_FXCH>, D9; 503} 504 505// Floating point constant loads. 506let isReMaterializable = 1 in { 507def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 508 [(set RFP32:$dst, fpimm0)]>; 509def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, 510 [(set RFP32:$dst, fpimm1)]>; 511def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 512 [(set RFP64:$dst, fpimm0)]>; 513def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, 514 [(set RFP64:$dst, fpimm1)]>; 515def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 516 [(set RFP80:$dst, fpimm0)]>; 517def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, 518 [(set RFP80:$dst, fpimm1)]>; 519} 520 521let SchedRW = [WriteZero] in { 522def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz", IIC_FLDZ>, D9; 523def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1", IIC_FIST>, D9; 524} 525 526// Floating point compares. 527let SchedRW = [WriteFAdd] in { 528def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 529 [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; 530def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 531 [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; 532def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 533 [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; 534} // SchedRW 535} // Defs = [FPSW] 536 537let SchedRW = [WriteFAdd] in { 538// CC = ST(0) cmp ST(i) 539let Defs = [EFLAGS, FPSW] in { 540def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, 541 [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; 542def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, 543 [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; 544def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, 545 [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; 546} 547 548let Defs = [FPSW], Uses = [ST0] in { 549def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i) 550 (outs), (ins RST:$reg), 551 "fucom\t$reg", IIC_FUCOM>, DD; 552def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop 553 (outs), (ins RST:$reg), 554 "fucomp\t$reg", IIC_FUCOM>, DD; 555def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop 556 (outs), (ins), 557 "fucompp", IIC_FUCOM>, DA; 558} 559 560let Defs = [EFLAGS, FPSW], Uses = [ST0] in { 561def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i) 562 (outs), (ins RST:$reg), 563 "fucomi\t$reg", IIC_FUCOMI>, DB; 564def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop 565 (outs), (ins RST:$reg), 566 "fucompi\t$reg", IIC_FUCOMI>, DF; 567} 568 569let Defs = [EFLAGS, FPSW] in { 570def COM_FIr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), 571 "fcomi\t$reg", IIC_FCOMI>, DB; 572def COM_FIPr : FPI<0xF0, AddRegFrm, (outs), (ins RST:$reg), 573 "fcompi\t$reg", IIC_FCOMI>, DF; 574} 575} // SchedRW 576 577// Floating point flag ops. 578let SchedRW = [WriteALU] in { 579let Defs = [AX], Uses = [FPSW] in 580def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags 581 (outs), (ins), "fnstsw\t{%ax|ax}", 582 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF; 583 584def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world 585 (outs), (ins i16mem:$dst), "fnstcw\t$dst", 586 [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; 587} // SchedRW 588let mayLoad = 1 in 589def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] 590 (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, 591 Sched<[WriteLoad]>; 592 593// FPU control instructions 594let SchedRW = [WriteMicrocoded] in { 595let Defs = [FPSW] in 596def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB; 597def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg), 598 "ffree\t$reg", IIC_FFREE>, DD; 599// Clear exceptions 600 601let Defs = [FPSW] in 602def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", [], IIC_FNCLEX>, DB; 603} // SchedRW 604 605// Operandless floating-point instructions for the disassembler. 606let SchedRW = [WriteMicrocoded] in { 607def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; 608 609def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", [], IIC_FNOP>, D9; 610def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", [], IIC_FXAM>, D9; 611def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", [], IIC_FLDL>, D9; 612def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", [], IIC_FLDL>, D9; 613def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", [], IIC_FLDL>, D9; 614def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", [], IIC_FLDL>, D9; 615def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", [], IIC_FLDL>, D9; 616def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", [], IIC_F2XM1>, D9; 617def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", [], IIC_FYL2X>, D9; 618def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", [], IIC_FPTAN>, D9; 619def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", [], IIC_FPATAN>, D9; 620def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", [], IIC_FXTRACT>, D9; 621def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", [], IIC_FPREM1>, D9; 622def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", [], IIC_FPSTP>, D9; 623def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", [], IIC_FPSTP>, D9; 624def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", [], IIC_FPREM>, D9; 625def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>, D9; 626def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", [], IIC_FSINCOS>, D9; 627def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", [], IIC_FRNDINT>, D9; 628def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", [], IIC_FSCALE>, D9; 629def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE; 630 631def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 632 "fxsave\t$dst", [], IIC_FXSAVE>, TB; 633def FXSAVE64 : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), 634 "fxsaveq\t$dst", [], IIC_FXSAVE>, TB, REX_W, 635 Requires<[In64BitMode]>; 636def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 637 "fxrstor\t$src", [], IIC_FXRSTOR>, TB; 638def FXRSTOR64 : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), 639 "fxrstorq\t$src", [], IIC_FXRSTOR>, TB, REX_W, 640 Requires<[In64BitMode]>; 641} // SchedRW 642 643//===----------------------------------------------------------------------===// 644// Non-Instruction Patterns 645//===----------------------------------------------------------------------===// 646 647// Required for RET of f32 / f64 / f80 values. 648def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; 649def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; 650def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; 651 652// Required for CALL which return f32 / f64 / f80 values. 653def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; 654def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, 655 RFP64:$src)>; 656def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; 657def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, 658 RFP80:$src)>; 659def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, 660 RFP80:$src)>; 661def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, 662 RFP80:$src)>; 663 664// Floating point constant -0.0 and -1.0 665def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; 666def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; 667def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; 668def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; 669def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; 670def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; 671 672// Used to conv. i64 to f64 since there isn't a SSE version. 673def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; 674 675// FP extensions map onto simple pseudo-value conversions if they are to/from 676// the FP stack. 677def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, 678 Requires<[FPStackf32]>; 679def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, 680 Requires<[FPStackf32]>; 681def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, 682 Requires<[FPStackf64]>; 683 684// FP truncations map onto simple pseudo-value conversions if they are to/from 685// the FP stack. We have validated that only value-preserving truncations make 686// it through isel. 687def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, 688 Requires<[FPStackf32]>; 689def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, 690 Requires<[FPStackf32]>; 691def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, 692 Requires<[FPStackf64]>; 693