X86ATTInstPrinter.cpp revision 263508 
1//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as AT&T-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86ATTInstPrinter.h"
17#include "MCTargetDesc/X86BaseInfo.h"
18#include "MCTargetDesc/X86MCTargetDesc.h"
19#include "X86InstComments.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/Format.h"
27#include "llvm/Support/FormattedStream.h"
28#include <map>
29using namespace llvm;
30
31// Include the auto-generated portion of the assembly writer.
32#define PRINT_ALIAS_INSTR
33#include "X86GenAsmWriter.inc"
34
35void X86ATTInstPrinter::printRegName(raw_ostream &OS,
36                                     unsigned RegNo) const {
37  OS << markup("<reg:")
38     << '%' << getRegisterName(RegNo)
39     << markup(">");
40}
41
42void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
43                                  StringRef Annot) {
44  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
45  uint64_t TSFlags = Desc.TSFlags;
46
47  if (TSFlags & X86II::LOCK)
48    OS << "\tlock\n";
49
50  // Try to print any aliases first.
51  if (!printAliasInstr(MI, OS))
52    printInstruction(MI, OS);
53
54  // Next always print the annotation.
55  printAnnotation(OS, Annot);
56
57  // If verbose assembly is enabled, we can print some informative comments.
58  if (CommentStream)
59    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
60}
61
62void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
63                                   raw_ostream &O) {
64  int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
65  switch (Imm) {
66  default: llvm_unreachable("Invalid ssecc argument!");
67  case    0: O << "eq"; break;
68  case    1: O << "lt"; break;
69  case    2: O << "le"; break;
70  case    3: O << "unord"; break;
71  case    4: O << "neq"; break;
72  case    5: O << "nlt"; break;
73  case    6: O << "nle"; break;
74  case    7: O << "ord"; break;
75  case    8: O << "eq_uq"; break;
76  case    9: O << "nge"; break;
77  case  0xa: O << "ngt"; break;
78  case  0xb: O << "false"; break;
79  case  0xc: O << "neq_oq"; break;
80  case  0xd: O << "ge"; break;
81  case  0xe: O << "gt"; break;
82  case  0xf: O << "true"; break;
83  }
84}
85
86void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
87                                   raw_ostream &O) {
88  int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
89  switch (Imm) {
90  default: llvm_unreachable("Invalid avxcc argument!");
91  case    0: O << "eq"; break;
92  case    1: O << "lt"; break;
93  case    2: O << "le"; break;
94  case    3: O << "unord"; break;
95  case    4: O << "neq"; break;
96  case    5: O << "nlt"; break;
97  case    6: O << "nle"; break;
98  case    7: O << "ord"; break;
99  case    8: O << "eq_uq"; break;
100  case    9: O << "nge"; break;
101  case  0xa: O << "ngt"; break;
102  case  0xb: O << "false"; break;
103  case  0xc: O << "neq_oq"; break;
104  case  0xd: O << "ge"; break;
105  case  0xe: O << "gt"; break;
106  case  0xf: O << "true"; break;
107  case 0x10: O << "eq_os"; break;
108  case 0x11: O << "lt_oq"; break;
109  case 0x12: O << "le_oq"; break;
110  case 0x13: O << "unord_s"; break;
111  case 0x14: O << "neq_us"; break;
112  case 0x15: O << "nlt_uq"; break;
113  case 0x16: O << "nle_uq"; break;
114  case 0x17: O << "ord_s"; break;
115  case 0x18: O << "eq_us"; break;
116  case 0x19: O << "nge_uq"; break;
117  case 0x1a: O << "ngt_uq"; break;
118  case 0x1b: O << "false_os"; break;
119  case 0x1c: O << "neq_os"; break;
120  case 0x1d: O << "ge_oq"; break;
121  case 0x1e: O << "gt_oq"; break;
122  case 0x1f: O << "true_us"; break;
123  }
124}
125
126/// printPCRelImm - This is used to print an immediate value that ends up
127/// being encoded as a pc-relative value (e.g. for jumps and calls).  These
128/// print slightly differently than normal immediates.  For example, a $ is not
129/// emitted.
130void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
131                                      raw_ostream &O) {
132  const MCOperand &Op = MI->getOperand(OpNo);
133  if (Op.isImm())
134    O << formatImm(Op.getImm());
135  else {
136    assert(Op.isExpr() && "unknown pcrel immediate operand");
137    // If a symbolic branch target was added as a constant expression then print
138    // that address in hex.
139    const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
140    int64_t Address;
141    if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
142      O << formatHex((uint64_t)Address);
143    }
144    else {
145      // Otherwise, just print the expression.
146      O << *Op.getExpr();
147    }
148  }
149}
150
151void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
152                                     raw_ostream &O) {
153  const MCOperand &Op = MI->getOperand(OpNo);
154  if (Op.isReg()) {
155    printRegName(O, Op.getReg());
156  } else if (Op.isImm()) {
157    // Print X86 immediates as signed values.
158    O << markup("<imm:")
159      << '$' << formatImm((int64_t)Op.getImm())
160      << markup(">");
161
162    if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
163      *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
164
165  } else {
166    assert(Op.isExpr() && "unknown operand kind in printOperand");
167    O << markup("<imm:")
168      << '$' << *Op.getExpr()
169      << markup(">");
170  }
171}
172
173void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
174                                          raw_ostream &O) {
175  const MCOperand &BaseReg  = MI->getOperand(Op);
176  const MCOperand &IndexReg = MI->getOperand(Op+2);
177  const MCOperand &DispSpec = MI->getOperand(Op+3);
178  const MCOperand &SegReg = MI->getOperand(Op+4);
179
180  O << markup("<mem:");
181
182  // If this has a segment register, print it.
183  if (SegReg.getReg()) {
184    printOperand(MI, Op+4, O);
185    O << ':';
186  }
187
188  if (DispSpec.isImm()) {
189    int64_t DispVal = DispSpec.getImm();
190    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
191      O << formatImm(DispVal);
192  } else {
193    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
194    O << *DispSpec.getExpr();
195  }
196
197  if (IndexReg.getReg() || BaseReg.getReg()) {
198    O << '(';
199    if (BaseReg.getReg())
200      printOperand(MI, Op, O);
201
202    if (IndexReg.getReg()) {
203      O << ',';
204      printOperand(MI, Op+2, O);
205      unsigned ScaleVal = MI->getOperand(Op+1).getImm();
206      if (ScaleVal != 1) {
207        O << ','
208          << markup("<imm:")
209          << ScaleVal // never printed in hex.
210          << markup(">");
211      }
212    }
213    O << ')';
214  }
215
216  O << markup(">");
217}
218
219void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
220                                       raw_ostream &O) {
221  const MCOperand &DispSpec = MI->getOperand(Op);
222
223  O << markup("<mem:");
224
225  if (DispSpec.isImm()) {
226    O << formatImm(DispSpec.getImm());
227  } else {
228    assert(DispSpec.isExpr() && "non-immediate displacement?");
229    O << *DispSpec.getExpr();
230  }
231
232  O << markup(">");
233}
234