SystemZISelLowering.h revision 263508 
1//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that SystemZ uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16#define LLVM_TARGET_SystemZ_ISELLOWERING_H
17
18#include "SystemZ.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/Target/TargetLowering.h"
22
23namespace llvm {
24namespace SystemZISD {
25  enum {
26    FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28    // Return with a flag operand.  Operand 0 is the chain operand.
29    RET_FLAG,
30
31    // Calls a function.  Operand 0 is the chain operand and operand 1
32    // is the target address.  The arguments start at operand 2.
33    // There is an optional glue operand at the end.
34    CALL,
35    SIBCALL,
36
37    // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38    // accesses (LARL).  Operand 0 is the address.
39    PCREL_WRAPPER,
40
41    // Used in cases where an offset is applied to a TargetGlobalAddress.
42    // Operand 0 is the full TargetGlobalAddress and operand 1 is a
43    // PCREL_WRAPPER for an anchor point.  This is used so that we can
44    // cheaply refer to either the full address or the anchor point
45    // as a register base.
46    PCREL_OFFSET,
47
48    // Integer comparisons.  There are three operands: the two values
49    // to compare, and an integer of type SystemZICMP.
50    ICMP,
51
52    // Floating-point comparisons.  The two operands are the values to compare.
53    FCMP,
54
55    // Test under mask.  The first operand is ANDed with the second operand
56    // and the condition codes are set on the result.  The third operand is
57    // a boolean that is true if the condition codes need to distinguish
58    // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
59    // register forms do but the memory forms don't).
60    TM,
61
62    // Branches if a condition is true.  Operand 0 is the chain operand;
63    // operand 1 is the 4-bit condition-code mask, with bit N in
64    // big-endian order meaning "branch if CC=N"; operand 2 is the
65    // target block and operand 3 is the flag operand.
66    BR_CCMASK,
67
68    // Selects between operand 0 and operand 1.  Operand 2 is the
69    // mask of condition-code values for which operand 0 should be
70    // chosen over operand 1; it has the same form as BR_CCMASK.
71    // Operand 3 is the flag operand.
72    SELECT_CCMASK,
73
74    // Evaluates to the gap between the stack pointer and the
75    // base of the dynamically-allocatable area.
76    ADJDYNALLOC,
77
78    // Extracts the value of a 32-bit access register.  Operand 0 is
79    // the number of the register.
80    EXTRACT_ACCESS,
81
82    // Wrappers around the ISD opcodes of the same name.  The output and
83    // first input operands are GR128s.  The trailing numbers are the
84    // widths of the second operand in bits.
85    UMUL_LOHI64,
86    SDIVREM32,
87    SDIVREM64,
88    UDIVREM32,
89    UDIVREM64,
90
91    // Use a series of MVCs to copy bytes from one memory location to another.
92    // The operands are:
93    // - the target address
94    // - the source address
95    // - the constant length
96    //
97    // This isn't a memory opcode because we'd need to attach two
98    // MachineMemOperands rather than one.
99    MVC,
100
101    // Like MVC, but implemented as a loop that handles X*256 bytes
102    // followed by straight-line code to handle the rest (if any).
103    // The value of X is passed as an additional operand.
104    MVC_LOOP,
105
106    // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
107    NC,
108    NC_LOOP,
109    OC,
110    OC_LOOP,
111    XC,
112    XC_LOOP,
113
114    // Use CLC to compare two blocks of memory, with the same comments
115    // as for MVC and MVC_LOOP.
116    CLC,
117    CLC_LOOP,
118
119    // Use an MVST-based sequence to implement stpcpy().
120    STPCPY,
121
122    // Use a CLST-based sequence to implement strcmp().  The two input operands
123    // are the addresses of the strings to compare.
124    STRCMP,
125
126    // Use an SRST-based sequence to search a block of memory.  The first
127    // operand is the end address, the second is the start, and the third
128    // is the character to search for.  CC is set to 1 on success and 2
129    // on failure.
130    SEARCH_STRING,
131
132    // Store the CC value in bits 29 and 28 of an integer.
133    IPM,
134
135    // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
136    // ATOMIC_LOAD_<op>.
137    //
138    // Operand 0: the address of the containing 32-bit-aligned field
139    // Operand 1: the second operand of <op>, in the high bits of an i32
140    //            for everything except ATOMIC_SWAPW
141    // Operand 2: how many bits to rotate the i32 left to bring the first
142    //            operand into the high bits
143    // Operand 3: the negative of operand 2, for rotating the other way
144    // Operand 4: the width of the field in bits (8 or 16)
145    ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
146    ATOMIC_LOADW_ADD,
147    ATOMIC_LOADW_SUB,
148    ATOMIC_LOADW_AND,
149    ATOMIC_LOADW_OR,
150    ATOMIC_LOADW_XOR,
151    ATOMIC_LOADW_NAND,
152    ATOMIC_LOADW_MIN,
153    ATOMIC_LOADW_MAX,
154    ATOMIC_LOADW_UMIN,
155    ATOMIC_LOADW_UMAX,
156
157    // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
158    //
159    // Operand 0: the address of the containing 32-bit-aligned field
160    // Operand 1: the compare value, in the low bits of an i32
161    // Operand 2: the swap value, in the low bits of an i32
162    // Operand 3: how many bits to rotate the i32 left to bring the first
163    //            operand into the high bits
164    // Operand 4: the negative of operand 2, for rotating the other way
165    // Operand 5: the width of the field in bits (8 or 16)
166    ATOMIC_CMP_SWAPW,
167
168    // Prefetch from the second operand using the 4-bit control code in
169    // the first operand.  The code is 1 for a load prefetch and 2 for
170    // a store prefetch.
171    PREFETCH
172  };
173
174  // Return true if OPCODE is some kind of PC-relative address.
175  inline bool isPCREL(unsigned Opcode) {
176    return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
177  }
178}
179
180namespace SystemZICMP {
181  // Describes whether an integer comparison needs to be signed or unsigned,
182  // or whether either type is OK.
183  enum {
184    Any,
185    UnsignedOnly,
186    SignedOnly
187  };
188}
189
190class SystemZSubtarget;
191class SystemZTargetMachine;
192
193class SystemZTargetLowering : public TargetLowering {
194public:
195  explicit SystemZTargetLowering(SystemZTargetMachine &TM);
196
197  // Override TargetLowering.
198  virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
199    return MVT::i32;
200  }
201  virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE;
202  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
203  virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
204  virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
205     LLVM_OVERRIDE;
206  virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
207    LLVM_OVERRIDE;
208  virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
209  virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
210  virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
211  virtual std::pair<unsigned, const TargetRegisterClass *>
212    getRegForInlineAsmConstraint(const std::string &Constraint,
213                                 MVT VT) const LLVM_OVERRIDE;
214  virtual TargetLowering::ConstraintType
215    getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
216  virtual TargetLowering::ConstraintWeight
217    getSingleConstraintMatchWeight(AsmOperandInfo &info,
218                                   const char *constraint) const LLVM_OVERRIDE;
219  virtual void
220    LowerAsmOperandForConstraint(SDValue Op,
221                                 std::string &Constraint,
222                                 std::vector<SDValue> &Ops,
223                                 SelectionDAG &DAG) const LLVM_OVERRIDE;
224  virtual MachineBasicBlock *
225    EmitInstrWithCustomInserter(MachineInstr *MI,
226                                MachineBasicBlock *BB) const LLVM_OVERRIDE;
227  virtual SDValue LowerOperation(SDValue Op,
228                                 SelectionDAG &DAG) const LLVM_OVERRIDE;
229  virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
230  virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
231  virtual SDValue
232    LowerFormalArguments(SDValue Chain,
233                         CallingConv::ID CallConv, bool isVarArg,
234                         const SmallVectorImpl<ISD::InputArg> &Ins,
235                         SDLoc DL, SelectionDAG &DAG,
236                         SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
237  virtual SDValue
238    LowerCall(CallLoweringInfo &CLI,
239              SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
240
241  virtual SDValue
242    LowerReturn(SDValue Chain,
243                CallingConv::ID CallConv, bool IsVarArg,
244                const SmallVectorImpl<ISD::OutputArg> &Outs,
245                const SmallVectorImpl<SDValue> &OutVals,
246                SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
247
248private:
249  const SystemZSubtarget &Subtarget;
250  const SystemZTargetMachine &TM;
251
252  // Implement LowerOperation for individual opcodes.
253  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
254  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
255  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
256  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
257                             SelectionDAG &DAG) const;
258  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
259                                SelectionDAG &DAG) const;
260  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
261                            SelectionDAG &DAG) const;
262  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
263  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
264  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
265  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
266  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
267  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
268  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
269  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
270  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
271  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
272  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
273  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
274                           unsigned Opcode) const;
275  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
276  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
277  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
278  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
279
280  // If the last instruction before MBBI in MBB was some form of COMPARE,
281  // try to replace it with a COMPARE AND BRANCH just before MBBI.
282  // CCMask and Target are the BRC-like operands for the branch.
283  // Return true if the change was made.
284  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
285                                  MachineBasicBlock::iterator MBBI,
286                                  unsigned CCMask,
287                                  MachineBasicBlock *Target) const;
288
289  // Implement EmitInstrWithCustomInserter for individual operation types.
290  MachineBasicBlock *emitSelect(MachineInstr *MI,
291                                MachineBasicBlock *BB) const;
292  MachineBasicBlock *emitCondStore(MachineInstr *MI,
293                                   MachineBasicBlock *BB,
294                                   unsigned StoreOpcode, unsigned STOCOpcode,
295                                   bool Invert) const;
296  MachineBasicBlock *emitExt128(MachineInstr *MI,
297                                MachineBasicBlock *MBB,
298                                bool ClearEven, unsigned SubReg) const;
299  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
300                                          MachineBasicBlock *BB,
301                                          unsigned BinOpcode, unsigned BitSize,
302                                          bool Invert = false) const;
303  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
304                                          MachineBasicBlock *MBB,
305                                          unsigned CompareOpcode,
306                                          unsigned KeepOldMask,
307                                          unsigned BitSize) const;
308  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
309                                        MachineBasicBlock *BB) const;
310  MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
311                                       MachineBasicBlock *BB,
312                                       unsigned Opcode) const;
313  MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
314                                       MachineBasicBlock *BB,
315                                       unsigned Opcode) const;
316};
317} // end namespace llvm
318
319#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
320