SystemZMCTargetDesc.h revision 263508
122347Spst//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// 222347Spst// 329964Sache// The LLVM Compiler Infrastructure 429964Sache// 522347Spst// This file is distributed under the University of Illinois Open Source 622347Spst// License. See LICENSE.TXT for details. 722347Spst// 822347Spst//===----------------------------------------------------------------------===// 922347Spst 1022347Spst#ifndef SYSTEMZMCTARGETDESC_H 1122347Spst#define SYSTEMZMCTARGETDESC_H 1222347Spst 1322347Spst#include "llvm/Support/DataTypes.h" 1422347Spst 1522347Spstnamespace llvm { 1622347Spst 1729964Sacheclass MCAsmBackend; 1822347Spstclass MCCodeEmitter; 1922347Spstclass MCContext; 2022347Spstclass MCInstrInfo; 2122347Spstclass MCObjectWriter; 2222347Spstclass MCRegisterInfo; 2322347Spstclass MCSubtargetInfo; 2422347Spstclass StringRef; 2522347Spstclass Target; 2622347Spstclass raw_ostream; 2722347Spst 2822347Spstextern Target TheSystemZTarget; 2922347Spst 3022347Spstnamespace SystemZMC { 3122347Spst // How many bytes are in the ABI-defined, caller-allocated part of 3222347Spst // a stack frame. 3322347Spst const int64_t CallFrameSize = 160; 3422347Spst 3522347Spst // The offset of the DWARF CFA from the incoming stack pointer. 3622347Spst const int64_t CFAOffsetFromInitialSP = CallFrameSize; 3722347Spst 3822347Spst // Maps of asm register numbers to LLVM register numbers, with 0 indicating 3922347Spst // an invalid register. In principle we could use 32-bit and 64-bit register 4022347Spst // classes directly, provided that we relegated the GPR allocation order 4122347Spst // in SystemZRegisterInfo.td to an AltOrder and left the default order 4222347Spst // as %r0-%r15. It seems better to provide the same interface for 4322347Spst // all classes though. 4422347Spst extern const unsigned GR32Regs[16]; 4522347Spst extern const unsigned GRH32Regs[16]; 4622347Spst extern const unsigned GR64Regs[16]; 4722347Spst extern const unsigned GR128Regs[16]; 4822347Spst extern const unsigned FP32Regs[16]; 4922347Spst extern const unsigned FP64Regs[16]; 5022347Spst extern const unsigned FP128Regs[16]; 5122347Spst 5222347Spst // Return the 0-based number of the first architectural register that 5322347Spst // contains the given LLVM register. E.g. R1D -> 1. 5422347Spst unsigned getFirstReg(unsigned Reg); 5522347Spst 5622347Spst // Return the given register as a GR64. 5722347Spst inline unsigned getRegAsGR64(unsigned Reg) { 5822347Spst return GR64Regs[getFirstReg(Reg)]; 5922347Spst } 6022347Spst 6122347Spst // Return the given register as a low GR32. 6222347Spst inline unsigned getRegAsGR32(unsigned Reg) { 6322347Spst return GR32Regs[getFirstReg(Reg)]; 6422347Spst } 6522347Spst 6622347Spst // Return the given register as a high GR32. 6722347Spst inline unsigned getRegAsGRH32(unsigned Reg) { 6822347Spst return GRH32Regs[getFirstReg(Reg)]; 6922347Spst } 7022347Spst} 7122347Spst 7222347SpstMCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, 7322347Spst const MCRegisterInfo &MRI, 7422347Spst const MCSubtargetInfo &STI, 7522347Spst MCContext &Ctx); 7622347Spst 7722347SpstMCAsmBackend *createSystemZMCAsmBackend(const Target &T, 7822347Spst const MCRegisterInfo &MRI, 7922347Spst StringRef TT, StringRef CPU); 8022347Spst 8129964SacheMCObjectWriter *createSystemZObjectWriter(raw_ostream &OS, uint8_t OSABI); 8222347Spst} // end namespace llvm 8322347Spst 8422347Spst// Defines symbolic names for SystemZ registers. 8522347Spst// This defines a mapping from register name to register number. 8622347Spst#define GET_REGINFO_ENUM 8722347Spst#include "SystemZGenRegisterInfo.inc" 8822347Spst 8922347Spst// Defines symbolic names for the SystemZ instructions. 9022347Spst#define GET_INSTRINFO_ENUM 9122347Spst#include "SystemZGenInstrInfo.inc" 9222347Spst 9322347Spst#define GET_SUBTARGETINFO_ENUM 9422347Spst#include "SystemZGenSubtargetInfo.inc" 9522347Spst 9622347Spst#endif 9722347Spst