SparcTargetMachine.cpp revision 263508 
1//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcTargetMachine.h"
14#include "Sparc.h"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/PassManager.h"
17#include "llvm/Support/TargetRegistry.h"
18using namespace llvm;
19
20extern "C" void LLVMInitializeSparcTarget() {
21  // Register the target.
22  RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23  RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
24}
25
26/// SparcTargetMachine ctor - Create an ILP32 architecture model
27///
28SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
29                                       StringRef CPU, StringRef FS,
30                                       const TargetOptions &Options,
31                                       Reloc::Model RM, CodeModel::Model CM,
32                                       CodeGenOpt::Level OL,
33                                       bool is64bit)
34  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35    Subtarget(TT, CPU, FS, is64bit),
36    DL(Subtarget.getDataLayout()),
37    InstrInfo(Subtarget),
38    TLInfo(*this), TSInfo(*this),
39    FrameLowering(Subtarget) {
40  initAsmInfo();
41}
42
43namespace {
44/// Sparc Code Generator Pass Configuration Options.
45class SparcPassConfig : public TargetPassConfig {
46public:
47  SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
48    : TargetPassConfig(TM, PM) {}
49
50  SparcTargetMachine &getSparcTargetMachine() const {
51    return getTM<SparcTargetMachine>();
52  }
53
54  virtual bool addInstSelector();
55  virtual bool addPreEmitPass();
56};
57} // namespace
58
59TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
60  return new SparcPassConfig(this, PM);
61}
62
63bool SparcPassConfig::addInstSelector() {
64  addPass(createSparcISelDag(getSparcTargetMachine()));
65  return false;
66}
67
68bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
69                                        JITCodeEmitter &JCE) {
70  // Machine code emitter pass for Sparc.
71  PM.add(createSparcJITCodeEmitterPass(*this, JCE));
72  return false;
73}
74
75/// addPreEmitPass - This pass may be implemented by targets that want to run
76/// passes immediately before machine code is emitted.  This should return
77/// true if -print-machineinstrs should print out the code after the passes.
78bool SparcPassConfig::addPreEmitPass(){
79  addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
80  return true;
81}
82
83void SparcV8TargetMachine::anchor() { }
84
85SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
86                                           StringRef TT, StringRef CPU,
87                                           StringRef FS,
88                                           const TargetOptions &Options,
89                                           Reloc::Model RM,
90                                           CodeModel::Model CM,
91                                           CodeGenOpt::Level OL)
92  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
93}
94
95void SparcV9TargetMachine::anchor() { }
96
97SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
98                                           StringRef TT,  StringRef CPU,
99                                           StringRef FS,
100                                           const TargetOptions &Options,
101                                           Reloc::Model RM,
102                                           CodeModel::Model CM,
103                                           CodeGenOpt::Level OL)
104  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
105}
106