SparcRegisterInfo.td revision 263508
1//===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Sparc register file 12//===----------------------------------------------------------------------===// 13 14class SparcReg<bits<16> Enc, string n> : Register<n> { 15 let HWEncoding = Enc; 16 let Namespace = "SP"; 17} 18 19class SparcCtrlReg<string n>: Register<n> { 20 let Namespace = "SP"; 21} 22 23let Namespace = "SP" in { 24def sub_even : SubRegIndex<32>; 25def sub_odd : SubRegIndex<32, 32>; 26def sub_even64 : SubRegIndex<64>; 27def sub_odd64 : SubRegIndex<64, 64>; 28} 29 30// Registers are identified with 5-bit ID numbers. 31// Ri - 32-bit integer registers 32class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 33 34// Rf - 32-bit floating-point registers 35class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 36 37// Rd - Slots in the FP register file for 64-bit floating-point values. 38class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 39 let SubRegs = subregs; 40 let SubRegIndices = [sub_even, sub_odd]; 41 let CoveredBySubRegs = 1; 42} 43 44// Rq - Slots in the FP register file for 128-bit floating-point values. 45class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 46 let SubRegs = subregs; 47 let SubRegIndices = [sub_even64, sub_odd64]; 48 let CoveredBySubRegs = 1; 49} 50 51// Control Registers 52def ICC : SparcCtrlReg<"ICC">; // This represents icc and xcc in 64-bit code. 53def FCC : SparcCtrlReg<"FCC">; 54 55// Y register 56def Y : SparcCtrlReg<"Y">; 57 58// Integer registers 59def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 60def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 61def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 62def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 63def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 64def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 65def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 66def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 67def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 68def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 69def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 70def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 71def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 72def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 73def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 74def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 75def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 76def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 77def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 78def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 79def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 80def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 81def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 82def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 83def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 84def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 85def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 86def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 87def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 88def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 89def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 90def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 91 92// Floating-point registers 93def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 94def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 95def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 96def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 97def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 98def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 99def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 100def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 101def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 102def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 103def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 104def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 105def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 106def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 107def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 108def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 109def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 110def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 111def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 112def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 113def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 114def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 115def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 116def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 117def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 118def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 119def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 120def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 121def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 122def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 123def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 124def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 125 126// Aliases of the F* registers used to hold 64-bit fp values (doubles) 127def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 128def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 129def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 130def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 131def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 132def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 133def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 134def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 135def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 136def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 137def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 138def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 139def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 140def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 141def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 142def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 143 144// Unaliased double precision floating point registers. 145// FIXME: Define DwarfRegNum for these registers. 146def D16 : SparcReg< 1, "F32">; 147def D17 : SparcReg< 3, "F34">; 148def D18 : SparcReg< 5, "F36">; 149def D19 : SparcReg< 7, "F38">; 150def D20 : SparcReg< 9, "F40">; 151def D21 : SparcReg<11, "F42">; 152def D22 : SparcReg<13, "F44">; 153def D23 : SparcReg<15, "F46">; 154def D24 : SparcReg<17, "F48">; 155def D25 : SparcReg<19, "F50">; 156def D26 : SparcReg<21, "F52">; 157def D27 : SparcReg<23, "F54">; 158def D28 : SparcReg<25, "F56">; 159def D29 : SparcReg<27, "F58">; 160def D30 : SparcReg<29, "F60">; 161def D31 : SparcReg<31, "F62">; 162 163// Aliases of the F* registers used to hold 128-bit for values (long doubles). 164def Q0 : Rq< 0, "F0", [D0, D1]>; 165def Q1 : Rq< 4, "F4", [D2, D3]>; 166def Q2 : Rq< 8, "F8", [D4, D5]>; 167def Q3 : Rq<12, "F12", [D6, D7]>; 168def Q4 : Rq<16, "F16", [D8, D9]>; 169def Q5 : Rq<20, "F20", [D10, D11]>; 170def Q6 : Rq<24, "F24", [D12, D13]>; 171def Q7 : Rq<28, "F28", [D14, D15]>; 172def Q8 : Rq< 1, "F32", [D16, D17]>; 173def Q9 : Rq< 5, "F36", [D18, D19]>; 174def Q10 : Rq< 9, "F40", [D20, D21]>; 175def Q11 : Rq<13, "F44", [D22, D23]>; 176def Q12 : Rq<17, "F48", [D24, D25]>; 177def Q13 : Rq<21, "F52", [D26, D27]>; 178def Q14 : Rq<25, "F56", [D28, D29]>; 179def Q15 : Rq<29, "F60", [D30, D31]>; 180 181// Register classes. 182// 183// FIXME: the register order should be defined in terms of the preferred 184// allocation order... 185// 186// This register class should not be used to hold i64 values, use the I64Regs 187// register class for that. The i64 type is included here to allow i64 patterns 188// using the integer instructions. 189def IntRegs : RegisterClass<"SP", [i32, i64], 32, 190 (add (sequence "I%u", 0, 7), 191 (sequence "G%u", 0, 7), 192 (sequence "L%u", 0, 7), 193 (sequence "O%u", 0, 7))>; 194 195// Register class for 64-bit mode, with a 64-bit spill slot size. 196// These are the same as the 32-bit registers, so TableGen will consider this 197// to be a sub-class of IntRegs. That works out because requiring a 64-bit 198// spill slot is a stricter constraint than only requiring a 32-bit spill slot. 199def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 200 201// Floating point register classes. 202def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 203 204def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 205 206def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 207