SparcInstrFormats.td revision 263763 
1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
11          : Instruction {
12  field bits<32> Inst;
13
14  let Namespace = "SP";
15  let Size = 4;
16
17  bits<2> op;
18  let Inst{31-30} = op;               // Top two bits are the 'op' field
19
20  dag OutOperandList = outs;
21  dag InOperandList = ins;
22  let AsmString   = asmstr;
23  let Pattern = pattern;
24
25  let DecoderNamespace = "Sparc";
26  field bits<32> SoftFail = 0;
27}
28
29//===----------------------------------------------------------------------===//
30// Format #2 instruction classes in the Sparc
31//===----------------------------------------------------------------------===//
32
33// Format 2 instructions
34class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35   : InstSP<outs, ins, asmstr, pattern> {
36  bits<3>  op2;
37  bits<22> imm22;
38  let op          = 0;    // op = 0
39  let Inst{24-22} = op2;
40  let Inst{21-0}  = imm22;
41}
42
43// Specific F2 classes: SparcV8 manual, page 44
44//
45class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46   : F2<outs, ins, asmstr, pattern> {
47  bits<5>  rd;
48
49  let op2         = op2Val;
50
51  let Inst{29-25} = rd;
52}
53
54class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
55           list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
56  bits<4>   cond;
57  bit       annul = 0;     // currently unused
58
59  let op2         = op2Val;
60
61  let Inst{29}    = annul;
62  let Inst{28-25} = cond;
63}
64
65class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr,
66           list<dag> pattern>
67   : InstSP<outs, ins, asmstr, pattern> {
68  bit      annul;
69  bits<4>  cond;
70  bit      pred;
71  bits<19> imm19;
72
73  let op          = 0;    // op = 0
74
75  bit annul       = 0;    // currently unused
76  let pred        = 1;    // default is predict taken
77
78  let Inst{29}    = annul;
79  let Inst{28-25} = cond;
80  let Inst{24-22} = op2Val;
81  let Inst{21-20} = ccVal;
82  let Inst{19}    = pred;
83  let Inst{18-0}  = imm19;
84}
85
86//===----------------------------------------------------------------------===//
87// Format #3 instruction classes in the Sparc
88//===----------------------------------------------------------------------===//
89
90class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
91    : InstSP<outs, ins, asmstr, pattern> {
92  bits<5> rd;
93  bits<6> op3;
94  bits<5> rs1;
95  let op{1} = 1;   // Op = 2 or 3
96  let Inst{29-25} = rd;
97  let Inst{24-19} = op3;
98  let Inst{18-14} = rs1;
99}
100
101// Specific F3 classes: SparcV8 manual, page 44
102//
103class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
104           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
105  bits<5> rs2;
106
107  let op         = opVal;
108  let op3        = op3val;
109
110  let Inst{13}   = 0;     // i field = 0
111  let Inst{12-5} = asi;   // address space identifier
112  let Inst{4-0}  = rs2;
113}
114
115class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
116       list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
117                                                     asmstr, pattern>;
118
119class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
120           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
121  bits<13> simm13;
122
123  let op         = opVal;
124  let op3        = op3val;
125
126  let Inst{13}   = 1;     // i field = 1
127  let Inst{12-0} = simm13;
128}
129
130// floating-point
131class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
132           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
133  bits<5> rs2;
134
135  let op         = opVal;
136  let op3        = op3val;
137
138  let Inst{13-5} = opfval;   // fp opcode
139  let Inst{4-0}  = rs2;
140}
141
142// floating-point unary operations.
143class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
144           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
145  bits<5> rs2;
146
147  let op         = opVal;
148  let op3        = op3val;
149  let rs1        = 0;
150
151  let Inst{13-5} = opfval;   // fp opcode
152  let Inst{4-0}  = rs2;
153}
154
155// floating-point compares.
156class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
157           string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
158  bits<5> rs2;
159
160  let op         = opVal;
161  let op3        = op3val;
162  let rd         = 0;
163
164  let Inst{13-5} = opfval;   // fp opcode
165  let Inst{4-0}  = rs2;
166}
167
168// Shift by register rs2.
169class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
170            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
171  bit x = xVal;           // 1 for 64-bit shifts.
172  bits<5> rs2;
173
174  let op         = opVal;
175  let op3        = op3val;
176
177  let Inst{13}   = 0;     // i field = 0
178  let Inst{12}   = x;     // extended registers.
179  let Inst{4-0}  = rs2;
180}
181
182// Shift by immediate.
183class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
184            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
185  bit x = xVal;           // 1 for 64-bit shifts.
186  bits<6> shcnt;          // shcnt32 / shcnt64.
187
188  let op         = opVal;
189  let op3        = op3val;
190
191  let Inst{13}   = 1;     // i field = 1
192  let Inst{12}   = x;     // extended registers.
193  let Inst{5-0}  = shcnt;
194}
195
196// Define rr and ri shift instructions with patterns.
197multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
198                ValueType VT, RegisterClass RC> {
199  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
200                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
201                 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
202  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
203                 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
204                 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
205}
206
207class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
208      : InstSP<outs, ins, asmstr, pattern> {
209  bits<5> rd;
210
211  let op          = 2;
212  let Inst{29-25} = rd;
213  let Inst{24-19} = op3;
214}
215
216
217class F4_1<bits<6> op3, dag outs, dag ins,
218            string asmstr, list<dag> pattern>
219      : F4<op3, outs, ins, asmstr, pattern> {
220
221  bits<3> cc;
222  bits<4> cond;
223  bits<5> rs2;
224
225  let Inst{4-0}   = rs2;
226  let Inst{11}    = cc{0};
227  let Inst{12}    = cc{1};
228  let Inst{13}    = 0;
229  let Inst{17-14} = cond;
230  let Inst{18}    = cc{2};
231
232}
233
234class F4_2<bits<6> op3, dag outs, dag ins,
235            string asmstr, list<dag> pattern>
236      : F4<op3, outs, ins, asmstr, pattern> {
237  bits<3>  cc;
238  bits<4>  cond;
239  bits<11> simm11;
240
241  let Inst{10-0}  = simm11;
242  let Inst{11}    = cc{0};
243  let Inst{12}    = cc{1};
244  let Inst{13}    = 1;
245  let Inst{17-14} = cond;
246  let Inst{18}    = cc{2};
247}
248
249class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
250           string asmstr, list<dag> pattern>
251      : F4<op3, outs, ins, asmstr, pattern> {
252  bits<4> cond;
253  bits<3> opf_cc;
254  bits<5> rs2;
255
256  let Inst{18}     = 0;
257  let Inst{17-14}  = cond;
258  let Inst{13-11}  = opf_cc;
259  let Inst{10-5}   = opf_low;
260  let Inst{4-0}    = rs2;
261}
262