SparcISelLowering.cpp revision 263763
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "MCTargetDesc/SparcMCExpr.h" 17#include "SparcMachineFunctionInfo.h" 18#include "SparcRegisterInfo.h" 19#include "SparcTargetMachine.h" 20#include "SparcTargetObjectFile.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/SelectionDAG.h" 27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28#include "llvm/IR/DerivedTypes.h" 29#include "llvm/IR/Function.h" 30#include "llvm/IR/Module.h" 31#include "llvm/Support/ErrorHandling.h" 32using namespace llvm; 33 34 35//===----------------------------------------------------------------------===// 36// Calling Convention Implementation 37//===----------------------------------------------------------------------===// 38 39static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, CCState &State) 42{ 43 assert (ArgFlags.isSRet()); 44 45 // Assign SRet argument. 46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 47 0, 48 LocVT, LocInfo)); 49 return true; 50} 51 52static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 54 ISD::ArgFlagsTy &ArgFlags, CCState &State) 55{ 56 static const uint16_t RegList[] = { 57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 58 }; 59 // Try to get first reg. 60 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 62 } else { 63 // Assign whole thing in stack. 64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 65 State.AllocateStack(8,4), 66 LocVT, LocInfo)); 67 return true; 68 } 69 70 // Try to get second reg. 71 if (unsigned Reg = State.AllocateReg(RegList, 6)) 72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 73 else 74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 75 State.AllocateStack(4,4), 76 LocVT, LocInfo)); 77 return true; 78} 79 80// Allocate a full-sized argument for the 64-bit ABI. 81static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 83 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 85 || LocVT.getSizeInBits() == 64) && 86 "Can't handle non-64 bits locations"); 87 88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; 90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; 91 unsigned Offset = State.AllocateStack(size, alignment); 92 unsigned Reg = 0; 93 94 if (LocVT == MVT::i64 && Offset < 6*8) 95 // Promote integers to %i0-%i5. 96 Reg = SP::I0 + Offset/8; 97 else if (LocVT == MVT::f64 && Offset < 16*8) 98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 99 Reg = SP::D0 + Offset/8; 100 else if (LocVT == MVT::f32 && Offset < 16*8) 101 // Promote floats to %f1, %f3, ... 102 Reg = SP::F1 + Offset/4; 103 else if (LocVT == MVT::f128 && Offset < 16*8) 104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). 105 Reg = SP::Q0 + Offset/16; 106 107 // Promote to register when possible, otherwise use the stack slot. 108 if (Reg) { 109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 110 return true; 111 } 112 113 // This argument goes on the stack in an 8-byte slot. 114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 115 // the right-aligned float. The first 4 bytes of the stack slot are undefined. 116 if (LocVT == MVT::f32) 117 Offset += 4; 118 119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 120 return true; 121} 122 123// Allocate a half-sized argument for the 64-bit ABI. 124// 125// This is used when passing { float, int } structs by value in registers. 126static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 127 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 128 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 130 unsigned Offset = State.AllocateStack(4, 4); 131 132 if (LocVT == MVT::f32 && Offset < 16*8) { 133 // Promote floats to %f0-%f31. 134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 135 LocVT, LocInfo)); 136 return true; 137 } 138 139 if (LocVT == MVT::i32 && Offset < 6*8) { 140 // Promote integers to %i0-%i5, using half the register. 141 unsigned Reg = SP::I0 + Offset/8; 142 LocVT = MVT::i64; 143 LocInfo = CCValAssign::AExt; 144 145 // Set the Custom bit if this i32 goes in the high bits of a register. 146 if (Offset % 8 == 0) 147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 148 LocVT, LocInfo)); 149 else 150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 151 return true; 152 } 153 154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 155 return true; 156} 157 158#include "SparcGenCallingConv.inc" 159 160// The calling conventions in SparcCallingConv.td are described in terms of the 161// callee's register window. This function translates registers to the 162// corresponding caller window %o register. 163static unsigned toCallerWindow(unsigned Reg) { 164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 165 if (Reg >= SP::I0 && Reg <= SP::I7) 166 return Reg - SP::I0 + SP::O0; 167 return Reg; 168} 169 170SDValue 171SparcTargetLowering::LowerReturn(SDValue Chain, 172 CallingConv::ID CallConv, bool IsVarArg, 173 const SmallVectorImpl<ISD::OutputArg> &Outs, 174 const SmallVectorImpl<SDValue> &OutVals, 175 SDLoc DL, SelectionDAG &DAG) const { 176 if (Subtarget->is64Bit()) 177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 179} 180 181SDValue 182SparcTargetLowering::LowerReturn_32(SDValue Chain, 183 CallingConv::ID CallConv, bool IsVarArg, 184 const SmallVectorImpl<ISD::OutputArg> &Outs, 185 const SmallVectorImpl<SDValue> &OutVals, 186 SDLoc DL, SelectionDAG &DAG) const { 187 MachineFunction &MF = DAG.getMachineFunction(); 188 189 // CCValAssign - represent the assignment of the return value to locations. 190 SmallVector<CCValAssign, 16> RVLocs; 191 192 // CCState - Info about the registers and stack slot. 193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 194 DAG.getTarget(), RVLocs, *DAG.getContext()); 195 196 // Analyze return values. 197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 198 199 SDValue Flag; 200 SmallVector<SDValue, 4> RetOps(1, Chain); 201 // Make room for the return address offset. 202 RetOps.push_back(SDValue()); 203 204 // Copy the result values into the output registers. 205 for (unsigned i = 0; i != RVLocs.size(); ++i) { 206 CCValAssign &VA = RVLocs[i]; 207 assert(VA.isRegLoc() && "Can only return in registers!"); 208 209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 210 OutVals[i], Flag); 211 212 // Guarantee that all emitted copies are stuck together with flags. 213 Flag = Chain.getValue(1); 214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 215 } 216 217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot 218 // If the function returns a struct, copy the SRetReturnReg to I0 219 if (MF.getFunction()->hasStructRetAttr()) { 220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 221 unsigned Reg = SFI->getSRetReturnReg(); 222 if (!Reg) 223 llvm_unreachable("sret virtual register not created in the entry block"); 224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 226 Flag = Chain.getValue(1); 227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 228 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 229 } 230 231 RetOps[0] = Chain; // Update chain. 232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 233 234 // Add the flag if we have it. 235 if (Flag.getNode()) 236 RetOps.push_back(Flag); 237 238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 239 &RetOps[0], RetOps.size()); 240} 241 242// Lower return values for the 64-bit ABI. 243// Return values are passed the exactly the same way as function arguments. 244SDValue 245SparcTargetLowering::LowerReturn_64(SDValue Chain, 246 CallingConv::ID CallConv, bool IsVarArg, 247 const SmallVectorImpl<ISD::OutputArg> &Outs, 248 const SmallVectorImpl<SDValue> &OutVals, 249 SDLoc DL, SelectionDAG &DAG) const { 250 // CCValAssign - represent the assignment of the return value to locations. 251 SmallVector<CCValAssign, 16> RVLocs; 252 253 // CCState - Info about the registers and stack slot. 254 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 255 DAG.getTarget(), RVLocs, *DAG.getContext()); 256 257 // Analyze return values. 258 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); 259 260 SDValue Flag; 261 SmallVector<SDValue, 4> RetOps(1, Chain); 262 263 // The second operand on the return instruction is the return address offset. 264 // The return address is always %i7+8 with the 64-bit ABI. 265 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 266 267 // Copy the result values into the output registers. 268 for (unsigned i = 0; i != RVLocs.size(); ++i) { 269 CCValAssign &VA = RVLocs[i]; 270 assert(VA.isRegLoc() && "Can only return in registers!"); 271 SDValue OutVal = OutVals[i]; 272 273 // Integer return values must be sign or zero extended by the callee. 274 switch (VA.getLocInfo()) { 275 case CCValAssign::SExt: 276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 277 break; 278 case CCValAssign::ZExt: 279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 280 break; 281 case CCValAssign::AExt: 282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 283 default: 284 break; 285 } 286 287 // The custom bit on an i32 return value indicates that it should be passed 288 // in the high bits of the register. 289 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 290 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 291 DAG.getConstant(32, MVT::i32)); 292 293 // The next value may go in the low bits of the same register. 294 // Handle both at once. 295 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 296 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 297 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 298 // Skip the next value, it's already done. 299 ++i; 300 } 301 } 302 303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 304 305 // Guarantee that all emitted copies are stuck together with flags. 306 Flag = Chain.getValue(1); 307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 308 } 309 310 RetOps[0] = Chain; // Update chain. 311 312 // Add the flag if we have it. 313 if (Flag.getNode()) 314 RetOps.push_back(Flag); 315 316 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 317 &RetOps[0], RetOps.size()); 318} 319 320SDValue SparcTargetLowering:: 321LowerFormalArguments(SDValue Chain, 322 CallingConv::ID CallConv, 323 bool IsVarArg, 324 const SmallVectorImpl<ISD::InputArg> &Ins, 325 SDLoc DL, 326 SelectionDAG &DAG, 327 SmallVectorImpl<SDValue> &InVals) const { 328 if (Subtarget->is64Bit()) 329 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 330 DL, DAG, InVals); 331 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 332 DL, DAG, InVals); 333} 334 335/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 336/// passed in either one or two GPRs, including FP values. TODO: we should 337/// pass FP values in FP registers for fastcc functions. 338SDValue SparcTargetLowering:: 339LowerFormalArguments_32(SDValue Chain, 340 CallingConv::ID CallConv, 341 bool isVarArg, 342 const SmallVectorImpl<ISD::InputArg> &Ins, 343 SDLoc dl, 344 SelectionDAG &DAG, 345 SmallVectorImpl<SDValue> &InVals) const { 346 MachineFunction &MF = DAG.getMachineFunction(); 347 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 348 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 349 350 // Assign locations to all of the incoming arguments. 351 SmallVector<CCValAssign, 16> ArgLocs; 352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 353 getTargetMachine(), ArgLocs, *DAG.getContext()); 354 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 355 356 const unsigned StackOffset = 92; 357 358 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 359 CCValAssign &VA = ArgLocs[i]; 360 361 if (i == 0 && Ins[i].Flags.isSRet()) { 362 // Get SRet from [%fp+64]. 363 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 364 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 365 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 366 MachinePointerInfo(), 367 false, false, false, 0); 368 InVals.push_back(Arg); 369 continue; 370 } 371 372 if (VA.isRegLoc()) { 373 if (VA.needsCustom()) { 374 assert(VA.getLocVT() == MVT::f64); 375 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 376 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 377 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 378 379 assert(i+1 < e); 380 CCValAssign &NextVA = ArgLocs[++i]; 381 382 SDValue LoVal; 383 if (NextVA.isMemLoc()) { 384 int FrameIdx = MF.getFrameInfo()-> 385 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 386 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 387 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 388 MachinePointerInfo(), 389 false, false, false, 0); 390 } else { 391 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 392 &SP::IntRegsRegClass); 393 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 394 } 395 SDValue WholeValue = 396 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 397 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 398 InVals.push_back(WholeValue); 399 continue; 400 } 401 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 402 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 403 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 404 if (VA.getLocVT() == MVT::f32) 405 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 406 else if (VA.getLocVT() != MVT::i32) { 407 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 408 DAG.getValueType(VA.getLocVT())); 409 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 410 } 411 InVals.push_back(Arg); 412 continue; 413 } 414 415 assert(VA.isMemLoc()); 416 417 unsigned Offset = VA.getLocMemOffset()+StackOffset; 418 419 if (VA.needsCustom()) { 420 assert(VA.getValVT() == MVT::f64); 421 // If it is double-word aligned, just load. 422 if (Offset % 8 == 0) { 423 int FI = MF.getFrameInfo()->CreateFixedObject(8, 424 Offset, 425 true); 426 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 427 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 428 MachinePointerInfo(), 429 false,false, false, 0); 430 InVals.push_back(Load); 431 continue; 432 } 433 434 int FI = MF.getFrameInfo()->CreateFixedObject(4, 435 Offset, 436 true); 437 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 438 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 439 MachinePointerInfo(), 440 false, false, false, 0); 441 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 442 Offset+4, 443 true); 444 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 445 446 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 447 MachinePointerInfo(), 448 false, false, false, 0); 449 450 SDValue WholeValue = 451 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 452 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 453 InVals.push_back(WholeValue); 454 continue; 455 } 456 457 int FI = MF.getFrameInfo()->CreateFixedObject(4, 458 Offset, 459 true); 460 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 461 SDValue Load ; 462 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 463 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 464 MachinePointerInfo(), 465 false, false, false, 0); 466 } else { 467 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 468 // Sparc is big endian, so add an offset based on the ObjectVT. 469 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 470 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 471 DAG.getConstant(Offset, MVT::i32)); 472 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 473 MachinePointerInfo(), 474 VA.getValVT(), false, false,0); 475 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 476 } 477 InVals.push_back(Load); 478 } 479 480 if (MF.getFunction()->hasStructRetAttr()) { 481 // Copy the SRet Argument to SRetReturnReg. 482 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 483 unsigned Reg = SFI->getSRetReturnReg(); 484 if (!Reg) { 485 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 486 SFI->setSRetReturnReg(Reg); 487 } 488 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 489 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 490 } 491 492 // Store remaining ArgRegs to the stack if this is a varargs function. 493 if (isVarArg) { 494 static const uint16_t ArgRegs[] = { 495 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 496 }; 497 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 498 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 499 unsigned ArgOffset = CCInfo.getNextStackOffset(); 500 if (NumAllocated == 6) 501 ArgOffset += StackOffset; 502 else { 503 assert(!ArgOffset); 504 ArgOffset = 68+4*NumAllocated; 505 } 506 507 // Remember the vararg offset for the va_start implementation. 508 FuncInfo->setVarArgsFrameOffset(ArgOffset); 509 510 std::vector<SDValue> OutChains; 511 512 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 513 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 514 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 515 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 516 517 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 518 true); 519 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 520 521 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 522 MachinePointerInfo(), 523 false, false, 0)); 524 ArgOffset += 4; 525 } 526 527 if (!OutChains.empty()) { 528 OutChains.push_back(Chain); 529 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 530 &OutChains[0], OutChains.size()); 531 } 532 } 533 534 return Chain; 535} 536 537// Lower formal arguments for the 64 bit ABI. 538SDValue SparcTargetLowering:: 539LowerFormalArguments_64(SDValue Chain, 540 CallingConv::ID CallConv, 541 bool IsVarArg, 542 const SmallVectorImpl<ISD::InputArg> &Ins, 543 SDLoc DL, 544 SelectionDAG &DAG, 545 SmallVectorImpl<SDValue> &InVals) const { 546 MachineFunction &MF = DAG.getMachineFunction(); 547 548 // Analyze arguments according to CC_Sparc64. 549 SmallVector<CCValAssign, 16> ArgLocs; 550 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 551 getTargetMachine(), ArgLocs, *DAG.getContext()); 552 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 553 554 // The argument array begins at %fp+BIAS+128, after the register save area. 555 const unsigned ArgArea = 128; 556 557 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 558 CCValAssign &VA = ArgLocs[i]; 559 if (VA.isRegLoc()) { 560 // This argument is passed in a register. 561 // All integer register arguments are promoted by the caller to i64. 562 563 // Create a virtual register for the promoted live-in value. 564 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 565 getRegClassFor(VA.getLocVT())); 566 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 567 568 // Get the high bits for i32 struct elements. 569 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 570 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 571 DAG.getConstant(32, MVT::i32)); 572 573 // The caller promoted the argument, so insert an Assert?ext SDNode so we 574 // won't promote the value again in this function. 575 switch (VA.getLocInfo()) { 576 case CCValAssign::SExt: 577 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 578 DAG.getValueType(VA.getValVT())); 579 break; 580 case CCValAssign::ZExt: 581 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 582 DAG.getValueType(VA.getValVT())); 583 break; 584 default: 585 break; 586 } 587 588 // Truncate the register down to the argument type. 589 if (VA.isExtInLoc()) 590 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 591 592 InVals.push_back(Arg); 593 continue; 594 } 595 596 // The registers are exhausted. This argument was passed on the stack. 597 assert(VA.isMemLoc()); 598 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 599 // beginning of the arguments area at %fp+BIAS+128. 600 unsigned Offset = VA.getLocMemOffset() + ArgArea; 601 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 602 // Adjust offset for extended arguments, SPARC is big-endian. 603 // The caller will have written the full slot with extended bytes, but we 604 // prefer our own extending loads. 605 if (VA.isExtInLoc()) 606 Offset += 8 - ValSize; 607 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 608 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 609 DAG.getFrameIndex(FI, getPointerTy()), 610 MachinePointerInfo::getFixedStack(FI), 611 false, false, false, 0)); 612 } 613 614 if (!IsVarArg) 615 return Chain; 616 617 // This function takes variable arguments, some of which may have been passed 618 // in registers %i0-%i5. Variable floating point arguments are never passed 619 // in floating point registers. They go on %i0-%i5 or on the stack like 620 // integer arguments. 621 // 622 // The va_start intrinsic needs to know the offset to the first variable 623 // argument. 624 unsigned ArgOffset = CCInfo.getNextStackOffset(); 625 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 626 // Skip the 128 bytes of register save area. 627 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + 628 Subtarget->getStackPointerBias()); 629 630 // Save the variable arguments that were passed in registers. 631 // The caller is required to reserve stack space for 6 arguments regardless 632 // of how many arguments were actually passed. 633 SmallVector<SDValue, 8> OutChains; 634 for (; ArgOffset < 6*8; ArgOffset += 8) { 635 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); 636 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 637 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); 638 OutChains.push_back(DAG.getStore(Chain, DL, VArg, 639 DAG.getFrameIndex(FI, getPointerTy()), 640 MachinePointerInfo::getFixedStack(FI), 641 false, false, 0)); 642 } 643 644 if (!OutChains.empty()) 645 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 646 &OutChains[0], OutChains.size()); 647 648 return Chain; 649} 650 651SDValue 652SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 653 SmallVectorImpl<SDValue> &InVals) const { 654 if (Subtarget->is64Bit()) 655 return LowerCall_64(CLI, InVals); 656 return LowerCall_32(CLI, InVals); 657} 658 659static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, 660 ImmutableCallSite *CS) { 661 if (CS) 662 return CS->hasFnAttr(Attribute::ReturnsTwice); 663 664 const Function *CalleeFn = 0; 665 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 666 CalleeFn = dyn_cast<Function>(G->getGlobal()); 667 } else if (ExternalSymbolSDNode *E = 668 dyn_cast<ExternalSymbolSDNode>(Callee)) { 669 const Function *Fn = DAG.getMachineFunction().getFunction(); 670 const Module *M = Fn->getParent(); 671 const char *CalleeName = E->getSymbol(); 672 CalleeFn = M->getFunction(CalleeName); 673 } 674 675 if (!CalleeFn) 676 return false; 677 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice); 678} 679 680// Lower a call for the 32-bit ABI. 681SDValue 682SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 683 SmallVectorImpl<SDValue> &InVals) const { 684 SelectionDAG &DAG = CLI.DAG; 685 SDLoc &dl = CLI.DL; 686 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 687 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 688 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 689 SDValue Chain = CLI.Chain; 690 SDValue Callee = CLI.Callee; 691 bool &isTailCall = CLI.IsTailCall; 692 CallingConv::ID CallConv = CLI.CallConv; 693 bool isVarArg = CLI.IsVarArg; 694 695 // Sparc target does not yet support tail call optimization. 696 isTailCall = false; 697 698 // Analyze operands of the call, assigning locations to each operand. 699 SmallVector<CCValAssign, 16> ArgLocs; 700 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 701 DAG.getTarget(), ArgLocs, *DAG.getContext()); 702 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 703 704 // Get the size of the outgoing arguments stack space requirement. 705 unsigned ArgsSize = CCInfo.getNextStackOffset(); 706 707 // Keep stack frames 8-byte aligned. 708 ArgsSize = (ArgsSize+7) & ~7; 709 710 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 711 712 // Create local copies for byval args. 713 SmallVector<SDValue, 8> ByValArgs; 714 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 715 ISD::ArgFlagsTy Flags = Outs[i].Flags; 716 if (!Flags.isByVal()) 717 continue; 718 719 SDValue Arg = OutVals[i]; 720 unsigned Size = Flags.getByValSize(); 721 unsigned Align = Flags.getByValAlign(); 722 723 int FI = MFI->CreateStackObject(Size, Align, false); 724 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 725 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 726 727 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 728 false, // isVolatile, 729 (Size <= 32), // AlwaysInline if size <= 32 730 MachinePointerInfo(), MachinePointerInfo()); 731 ByValArgs.push_back(FIPtr); 732 } 733 734 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 735 dl); 736 737 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 738 SmallVector<SDValue, 8> MemOpChains; 739 740 const unsigned StackOffset = 92; 741 bool hasStructRetAttr = false; 742 // Walk the register/memloc assignments, inserting copies/loads. 743 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 744 i != e; 745 ++i, ++realArgIdx) { 746 CCValAssign &VA = ArgLocs[i]; 747 SDValue Arg = OutVals[realArgIdx]; 748 749 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 750 751 // Use local copy if it is a byval arg. 752 if (Flags.isByVal()) 753 Arg = ByValArgs[byvalArgIdx++]; 754 755 // Promote the value if needed. 756 switch (VA.getLocInfo()) { 757 default: llvm_unreachable("Unknown loc info!"); 758 case CCValAssign::Full: break; 759 case CCValAssign::SExt: 760 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 761 break; 762 case CCValAssign::ZExt: 763 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 764 break; 765 case CCValAssign::AExt: 766 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 767 break; 768 case CCValAssign::BCvt: 769 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 770 break; 771 } 772 773 if (Flags.isSRet()) { 774 assert(VA.needsCustom()); 775 // store SRet argument in %sp+64 776 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 777 SDValue PtrOff = DAG.getIntPtrConstant(64); 778 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 779 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 780 MachinePointerInfo(), 781 false, false, 0)); 782 hasStructRetAttr = true; 783 continue; 784 } 785 786 if (VA.needsCustom()) { 787 assert(VA.getLocVT() == MVT::f64); 788 789 if (VA.isMemLoc()) { 790 unsigned Offset = VA.getLocMemOffset() + StackOffset; 791 // if it is double-word aligned, just store. 792 if (Offset % 8 == 0) { 793 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 794 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 795 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 796 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 797 MachinePointerInfo(), 798 false, false, 0)); 799 continue; 800 } 801 } 802 803 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 804 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 805 Arg, StackPtr, MachinePointerInfo(), 806 false, false, 0); 807 // Sparc is big-endian, so the high part comes first. 808 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 809 MachinePointerInfo(), false, false, false, 0); 810 // Increment the pointer to the other half. 811 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 812 DAG.getIntPtrConstant(4)); 813 // Load the low part. 814 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 815 MachinePointerInfo(), false, false, false, 0); 816 817 if (VA.isRegLoc()) { 818 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 819 assert(i+1 != e); 820 CCValAssign &NextVA = ArgLocs[++i]; 821 if (NextVA.isRegLoc()) { 822 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 823 } else { 824 // Store the low part in stack. 825 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 826 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 827 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 828 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 829 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 830 MachinePointerInfo(), 831 false, false, 0)); 832 } 833 } else { 834 unsigned Offset = VA.getLocMemOffset() + StackOffset; 835 // Store the high part. 836 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 837 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 838 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 839 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 840 MachinePointerInfo(), 841 false, false, 0)); 842 // Store the low part. 843 PtrOff = DAG.getIntPtrConstant(Offset+4); 844 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 845 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 846 MachinePointerInfo(), 847 false, false, 0)); 848 } 849 continue; 850 } 851 852 // Arguments that can be passed on register must be kept at 853 // RegsToPass vector 854 if (VA.isRegLoc()) { 855 if (VA.getLocVT() != MVT::f32) { 856 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 857 continue; 858 } 859 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 860 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 861 continue; 862 } 863 864 assert(VA.isMemLoc()); 865 866 // Create a store off the stack pointer for this argument. 867 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 868 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 869 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 870 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 871 MachinePointerInfo(), 872 false, false, 0)); 873 } 874 875 876 // Emit all stores, make sure the occur before any copies into physregs. 877 if (!MemOpChains.empty()) 878 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 879 &MemOpChains[0], MemOpChains.size()); 880 881 // Build a sequence of copy-to-reg nodes chained together with token 882 // chain and flag operands which copy the outgoing args into registers. 883 // The InFlag in necessary since all emitted instructions must be 884 // stuck together. 885 SDValue InFlag; 886 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 887 unsigned Reg = toCallerWindow(RegsToPass[i].first); 888 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 889 InFlag = Chain.getValue(1); 890 } 891 892 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 893 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 894 895 // If the callee is a GlobalAddress node (quite common, every direct call is) 896 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 897 // Likewise ExternalSymbol -> TargetExternalSymbol. 898 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) 899 ? SparcMCExpr::VK_Sparc_WPLT30 : 0); 900 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 901 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); 902 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 903 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); 904 905 // Returns a chain & a flag for retval copy to use 906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 907 SmallVector<SDValue, 8> Ops; 908 Ops.push_back(Chain); 909 Ops.push_back(Callee); 910 if (hasStructRetAttr) 911 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 912 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 913 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 914 RegsToPass[i].second.getValueType())); 915 916 // Add a register mask operand representing the call-preserved registers. 917 const SparcRegisterInfo *TRI = 918 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 919 const uint32_t *Mask = ((hasReturnsTwice) 920 ? TRI->getRTCallPreservedMask(CallConv) 921 : TRI->getCallPreservedMask(CallConv)); 922 assert(Mask && "Missing call preserved mask for calling convention"); 923 Ops.push_back(DAG.getRegisterMask(Mask)); 924 925 if (InFlag.getNode()) 926 Ops.push_back(InFlag); 927 928 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 929 InFlag = Chain.getValue(1); 930 931 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 932 DAG.getIntPtrConstant(0, true), InFlag, dl); 933 InFlag = Chain.getValue(1); 934 935 // Assign locations to each value returned by this call. 936 SmallVector<CCValAssign, 16> RVLocs; 937 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 938 DAG.getTarget(), RVLocs, *DAG.getContext()); 939 940 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 941 942 // Copy all of the result registers out of their specified physreg. 943 for (unsigned i = 0; i != RVLocs.size(); ++i) { 944 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 945 RVLocs[i].getValVT(), InFlag).getValue(1); 946 InFlag = Chain.getValue(2); 947 InVals.push_back(Chain.getValue(0)); 948 } 949 950 return Chain; 951} 952 953// This functions returns true if CalleeName is a ABI function that returns 954// a long double (fp128). 955static bool isFP128ABICall(const char *CalleeName) 956{ 957 static const char *const ABICalls[] = 958 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div", 959 "_Q_sqrt", "_Q_neg", 960 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq", 961 "_Q_lltoq", "_Q_ulltoq", 962 0 963 }; 964 for (const char * const *I = ABICalls; *I != 0; ++I) 965 if (strcmp(CalleeName, *I) == 0) 966 return true; 967 return false; 968} 969 970unsigned 971SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 972{ 973 const Function *CalleeFn = 0; 974 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 975 CalleeFn = dyn_cast<Function>(G->getGlobal()); 976 } else if (ExternalSymbolSDNode *E = 977 dyn_cast<ExternalSymbolSDNode>(Callee)) { 978 const Function *Fn = DAG.getMachineFunction().getFunction(); 979 const Module *M = Fn->getParent(); 980 const char *CalleeName = E->getSymbol(); 981 CalleeFn = M->getFunction(CalleeName); 982 if (!CalleeFn && isFP128ABICall(CalleeName)) 983 return 16; // Return sizeof(fp128) 984 } 985 986 if (!CalleeFn) 987 return 0; 988 989 assert(CalleeFn->hasStructRetAttr() && 990 "Callee does not have the StructRet attribute."); 991 992 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 993 Type *ElementTy = Ty->getElementType(); 994 return getDataLayout()->getTypeAllocSize(ElementTy); 995} 996 997 998// Fixup floating point arguments in the ... part of a varargs call. 999// 1000// The SPARC v9 ABI requires that floating point arguments are treated the same 1001// as integers when calling a varargs function. This does not apply to the 1002// fixed arguments that are part of the function's prototype. 1003// 1004// This function post-processes a CCValAssign array created by 1005// AnalyzeCallOperands(). 1006static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, 1007 ArrayRef<ISD::OutputArg> Outs) { 1008 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1009 const CCValAssign &VA = ArgLocs[i]; 1010 MVT ValTy = VA.getLocVT(); 1011 // FIXME: What about f32 arguments? C promotes them to f64 when calling 1012 // varargs functions. 1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) 1014 continue; 1015 // The fixed arguments to a varargs function still go in FP registers. 1016 if (Outs[VA.getValNo()].IsFixed) 1017 continue; 1018 1019 // This floating point argument should be reassigned. 1020 CCValAssign NewVA; 1021 1022 // Determine the offset into the argument array. 1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; 1024 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; 1025 unsigned Offset = argSize * (VA.getLocReg() - firstReg); 1026 assert(Offset < 16*8 && "Offset out of range, bad register enum?"); 1027 1028 if (Offset < 6*8) { 1029 // This argument should go in %i0-%i5. 1030 unsigned IReg = SP::I0 + Offset/8; 1031 if (ValTy == MVT::f64) 1032 // Full register, just bitconvert into i64. 1033 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), 1034 IReg, MVT::i64, CCValAssign::BCvt); 1035 else { 1036 assert(ValTy == MVT::f128 && "Unexpected type!"); 1037 // Full register, just bitconvert into i128 -- We will lower this into 1038 // two i64s in LowerCall_64. 1039 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), 1040 IReg, MVT::i128, CCValAssign::BCvt); 1041 } 1042 } else { 1043 // This needs to go to memory, we're out of integer registers. 1044 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), 1045 Offset, VA.getLocVT(), VA.getLocInfo()); 1046 } 1047 ArgLocs[i] = NewVA; 1048 } 1049} 1050 1051// Lower a call for the 64-bit ABI. 1052SDValue 1053SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 1054 SmallVectorImpl<SDValue> &InVals) const { 1055 SelectionDAG &DAG = CLI.DAG; 1056 SDLoc DL = CLI.DL; 1057 SDValue Chain = CLI.Chain; 1058 1059 // Sparc target does not yet support tail call optimization. 1060 CLI.IsTailCall = false; 1061 1062 // Analyze operands of the call, assigning locations to each operand. 1063 SmallVector<CCValAssign, 16> ArgLocs; 1064 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1065 DAG.getTarget(), ArgLocs, *DAG.getContext()); 1066 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 1067 1068 // Get the size of the outgoing arguments stack space requirement. 1069 // The stack offset computed by CC_Sparc64 includes all arguments. 1070 // Called functions expect 6 argument words to exist in the stack frame, used 1071 // or not. 1072 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 1073 1074 // Keep stack frames 16-byte aligned. 1075 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 1076 1077 // Varargs calls require special treatment. 1078 if (CLI.IsVarArg) 1079 fixupVariableFloatArgs(ArgLocs, CLI.Outs); 1080 1081 // Adjust the stack pointer to make room for the arguments. 1082 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 1083 // with more than 6 arguments. 1084 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1085 DL); 1086 1087 // Collect the set of registers to pass to the function and their values. 1088 // This will be emitted as a sequence of CopyToReg nodes glued to the call 1089 // instruction. 1090 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1091 1092 // Collect chains from all the memory opeations that copy arguments to the 1093 // stack. They must follow the stack pointer adjustment above and precede the 1094 // call instruction itself. 1095 SmallVector<SDValue, 8> MemOpChains; 1096 1097 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1098 const CCValAssign &VA = ArgLocs[i]; 1099 SDValue Arg = CLI.OutVals[i]; 1100 1101 // Promote the value if needed. 1102 switch (VA.getLocInfo()) { 1103 default: 1104 llvm_unreachable("Unknown location info!"); 1105 case CCValAssign::Full: 1106 break; 1107 case CCValAssign::SExt: 1108 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 1109 break; 1110 case CCValAssign::ZExt: 1111 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 1112 break; 1113 case CCValAssign::AExt: 1114 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 1115 break; 1116 case CCValAssign::BCvt: 1117 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But 1118 // SPARC does not support i128 natively. Lower it into two i64, see below. 1119 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 1120 || VA.getLocVT() != MVT::i128) 1121 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 1122 break; 1123 } 1124 1125 if (VA.isRegLoc()) { 1126 if (VA.needsCustom() && VA.getValVT() == MVT::f128 1127 && VA.getLocVT() == MVT::i128) { 1128 // Store and reload into the interger register reg and reg+1. 1129 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); 1130 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; 1131 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1132 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset); 1133 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 1134 HiPtrOff); 1135 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8); 1136 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 1137 LoPtrOff); 1138 1139 // Store to %sp+BIAS+128+Offset 1140 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff, 1141 MachinePointerInfo(), 1142 false, false, 0); 1143 // Load into Reg and Reg+1 1144 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, 1145 MachinePointerInfo(), 1146 false, false, false, 0); 1147 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, 1148 MachinePointerInfo(), 1149 false, false, false, 0); 1150 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), 1151 Hi64)); 1152 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), 1153 Lo64)); 1154 continue; 1155 } 1156 1157 // The custom bit on an i32 return value indicates that it should be 1158 // passed in the high bits of the register. 1159 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 1160 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 1161 DAG.getConstant(32, MVT::i32)); 1162 1163 // The next value may go in the low bits of the same register. 1164 // Handle both at once. 1165 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 1166 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 1167 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 1168 CLI.OutVals[i+1]); 1169 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 1170 // Skip the next value, it's already done. 1171 ++i; 1172 } 1173 } 1174 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 1175 continue; 1176 } 1177 1178 assert(VA.isMemLoc()); 1179 1180 // Create a store off the stack pointer for this argument. 1181 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1182 // The argument area starts at %fp+BIAS+128 in the callee frame, 1183 // %sp+BIAS+128 in ours. 1184 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 1185 Subtarget->getStackPointerBias() + 1186 128); 1187 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 1188 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 1189 MachinePointerInfo(), 1190 false, false, 0)); 1191 } 1192 1193 // Emit all stores, make sure they occur before the call. 1194 if (!MemOpChains.empty()) 1195 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 1196 &MemOpChains[0], MemOpChains.size()); 1197 1198 // Build a sequence of CopyToReg nodes glued together with token chain and 1199 // glue operands which copy the outgoing args into registers. The InGlue is 1200 // necessary since all emitted instructions must be stuck together in order 1201 // to pass the live physical registers. 1202 SDValue InGlue; 1203 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1204 Chain = DAG.getCopyToReg(Chain, DL, 1205 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1206 InGlue = Chain.getValue(1); 1207 } 1208 1209 // If the callee is a GlobalAddress node (quite common, every direct call is) 1210 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1211 // Likewise ExternalSymbol -> TargetExternalSymbol. 1212 SDValue Callee = CLI.Callee; 1213 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 1214 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) 1215 ? SparcMCExpr::VK_Sparc_WPLT30 : 0); 1216 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1217 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 1218 TF); 1219 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1220 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF); 1221 1222 // Build the operands for the call instruction itself. 1223 SmallVector<SDValue, 8> Ops; 1224 Ops.push_back(Chain); 1225 Ops.push_back(Callee); 1226 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1227 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1228 RegsToPass[i].second.getValueType())); 1229 1230 // Add a register mask operand representing the call-preserved registers. 1231 const SparcRegisterInfo *TRI = 1232 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 1233 const uint32_t *Mask = ((hasReturnsTwice) 1234 ? TRI->getRTCallPreservedMask(CLI.CallConv) 1235 : TRI->getCallPreservedMask(CLI.CallConv)); 1236 assert(Mask && "Missing call preserved mask for calling convention"); 1237 Ops.push_back(DAG.getRegisterMask(Mask)); 1238 1239 // Make sure the CopyToReg nodes are glued to the call instruction which 1240 // consumes the registers. 1241 if (InGlue.getNode()) 1242 Ops.push_back(InGlue); 1243 1244 // Now the call itself. 1245 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1246 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1247 InGlue = Chain.getValue(1); 1248 1249 // Revert the stack pointer immediately after the call. 1250 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1251 DAG.getIntPtrConstant(0, true), InGlue, DL); 1252 InGlue = Chain.getValue(1); 1253 1254 // Now extract the return values. This is more or less the same as 1255 // LowerFormalArguments_64. 1256 1257 // Assign locations to each value returned by this call. 1258 SmallVector<CCValAssign, 16> RVLocs; 1259 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1260 DAG.getTarget(), RVLocs, *DAG.getContext()); 1261 1262 // Set inreg flag manually for codegen generated library calls that 1263 // return float. 1264 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0) 1265 CLI.Ins[0].Flags.setInReg(); 1266 1267 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); 1268 1269 // Copy all of the result registers out of their specified physreg. 1270 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1271 CCValAssign &VA = RVLocs[i]; 1272 unsigned Reg = toCallerWindow(VA.getLocReg()); 1273 1274 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1275 // reside in the same register in the high and low bits. Reuse the 1276 // CopyFromReg previous node to avoid duplicate copies. 1277 SDValue RV; 1278 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1279 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1280 RV = Chain.getValue(0); 1281 1282 // But usually we'll create a new CopyFromReg for a different register. 1283 if (!RV.getNode()) { 1284 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1285 Chain = RV.getValue(1); 1286 InGlue = Chain.getValue(2); 1287 } 1288 1289 // Get the high bits for i32 struct elements. 1290 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1291 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1292 DAG.getConstant(32, MVT::i32)); 1293 1294 // The callee promoted the return value, so insert an Assert?ext SDNode so 1295 // we won't promote the value again in this function. 1296 switch (VA.getLocInfo()) { 1297 case CCValAssign::SExt: 1298 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1299 DAG.getValueType(VA.getValVT())); 1300 break; 1301 case CCValAssign::ZExt: 1302 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1303 DAG.getValueType(VA.getValVT())); 1304 break; 1305 default: 1306 break; 1307 } 1308 1309 // Truncate the register down to the return value type. 1310 if (VA.isExtInLoc()) 1311 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1312 1313 InVals.push_back(RV); 1314 } 1315 1316 return Chain; 1317} 1318 1319//===----------------------------------------------------------------------===// 1320// TargetLowering Implementation 1321//===----------------------------------------------------------------------===// 1322 1323/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1324/// condition. 1325static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1326 switch (CC) { 1327 default: llvm_unreachable("Unknown integer condition code!"); 1328 case ISD::SETEQ: return SPCC::ICC_E; 1329 case ISD::SETNE: return SPCC::ICC_NE; 1330 case ISD::SETLT: return SPCC::ICC_L; 1331 case ISD::SETGT: return SPCC::ICC_G; 1332 case ISD::SETLE: return SPCC::ICC_LE; 1333 case ISD::SETGE: return SPCC::ICC_GE; 1334 case ISD::SETULT: return SPCC::ICC_CS; 1335 case ISD::SETULE: return SPCC::ICC_LEU; 1336 case ISD::SETUGT: return SPCC::ICC_GU; 1337 case ISD::SETUGE: return SPCC::ICC_CC; 1338 } 1339} 1340 1341/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1342/// FCC condition. 1343static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1344 switch (CC) { 1345 default: llvm_unreachable("Unknown fp condition code!"); 1346 case ISD::SETEQ: 1347 case ISD::SETOEQ: return SPCC::FCC_E; 1348 case ISD::SETNE: 1349 case ISD::SETUNE: return SPCC::FCC_NE; 1350 case ISD::SETLT: 1351 case ISD::SETOLT: return SPCC::FCC_L; 1352 case ISD::SETGT: 1353 case ISD::SETOGT: return SPCC::FCC_G; 1354 case ISD::SETLE: 1355 case ISD::SETOLE: return SPCC::FCC_LE; 1356 case ISD::SETGE: 1357 case ISD::SETOGE: return SPCC::FCC_GE; 1358 case ISD::SETULT: return SPCC::FCC_UL; 1359 case ISD::SETULE: return SPCC::FCC_ULE; 1360 case ISD::SETUGT: return SPCC::FCC_UG; 1361 case ISD::SETUGE: return SPCC::FCC_UGE; 1362 case ISD::SETUO: return SPCC::FCC_U; 1363 case ISD::SETO: return SPCC::FCC_O; 1364 case ISD::SETONE: return SPCC::FCC_LG; 1365 case ISD::SETUEQ: return SPCC::FCC_UE; 1366 } 1367} 1368 1369SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1370 : TargetLowering(TM, new SparcELFTargetObjectFile()) { 1371 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1372 1373 // Set up the register classes. 1374 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1375 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1376 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1377 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); 1378 if (Subtarget->is64Bit()) 1379 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1380 1381 // Turn FP extload into load/fextend 1382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 1384 1385 // Sparc doesn't have i1 sign extending load 1386 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1387 1388 // Turn FP truncstore into trunc + store. 1389 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1390 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 1391 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 1392 1393 // Custom legalize GlobalAddress nodes into LO/HI parts. 1394 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1395 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1396 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1397 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); 1398 1399 // Sparc doesn't have sext_inreg, replace them with shl/sra 1400 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1403 1404 // Sparc has no REM or DIVREM operations. 1405 setOperationAction(ISD::UREM, MVT::i32, Expand); 1406 setOperationAction(ISD::SREM, MVT::i32, Expand); 1407 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1408 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1409 1410 // ... nor does SparcV9. 1411 if (Subtarget->is64Bit()) { 1412 setOperationAction(ISD::UREM, MVT::i64, Expand); 1413 setOperationAction(ISD::SREM, MVT::i64, Expand); 1414 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1415 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1416 } 1417 1418 // Custom expand fp<->sint 1419 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1420 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1421 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 1422 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 1423 1424 // Custom Expand fp<->uint 1425 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 1426 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 1427 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 1428 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 1429 1430 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1431 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1432 1433 // Sparc has no select or setcc: expand to SELECT_CC. 1434 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1435 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1436 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1437 setOperationAction(ISD::SELECT, MVT::f128, Expand); 1438 1439 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1440 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1441 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1442 setOperationAction(ISD::SETCC, MVT::f128, Expand); 1443 1444 // Sparc doesn't have BRCOND either, it has BR_CC. 1445 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1446 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1447 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1448 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1449 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1450 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1451 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 1452 1453 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1454 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1455 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1456 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 1457 1458 if (Subtarget->is64Bit()) { 1459 setOperationAction(ISD::ADDC, MVT::i64, Custom); 1460 setOperationAction(ISD::ADDE, MVT::i64, Custom); 1461 setOperationAction(ISD::SUBC, MVT::i64, Custom); 1462 setOperationAction(ISD::SUBE, MVT::i64, Custom); 1463 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 1464 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 1465 setOperationAction(ISD::SELECT, MVT::i64, Expand); 1466 setOperationAction(ISD::SETCC, MVT::i64, Expand); 1467 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1468 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1469 1470 setOperationAction(ISD::CTPOP, MVT::i64, 1471 Subtarget->usePopc() ? Legal : Expand); 1472 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 1473 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 1474 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 1475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 1476 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1477 setOperationAction(ISD::ROTL , MVT::i64, Expand); 1478 setOperationAction(ISD::ROTR , MVT::i64, Expand); 1479 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 1480 } 1481 1482 // ATOMICs. 1483 // FIXME: We insert fences for each atomics and generate sub-optimal code 1484 // for PSO/TSO. Also, implement other atomicrmw operations. 1485 1486 setInsertFencesForAtomic(true); 1487 1488 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); 1489 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, 1490 (Subtarget->isV9() ? Legal: Expand)); 1491 1492 1493 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); 1494 1495 // Custom Lower Atomic LOAD/STORE 1496 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 1497 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 1498 1499 if (Subtarget->is64Bit()) { 1500 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); 1501 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); 1502 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 1503 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); 1504 } 1505 1506 if (!Subtarget->isV9()) { 1507 // SparcV8 does not have FNEGD and FABSD. 1508 setOperationAction(ISD::FNEG, MVT::f64, Custom); 1509 setOperationAction(ISD::FABS, MVT::f64, Custom); 1510 } 1511 1512 setOperationAction(ISD::FSIN , MVT::f128, Expand); 1513 setOperationAction(ISD::FCOS , MVT::f128, Expand); 1514 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 1515 setOperationAction(ISD::FREM , MVT::f128, Expand); 1516 setOperationAction(ISD::FMA , MVT::f128, Expand); 1517 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1518 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1519 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1520 setOperationAction(ISD::FREM , MVT::f64, Expand); 1521 setOperationAction(ISD::FMA , MVT::f64, Expand); 1522 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1523 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1524 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1525 setOperationAction(ISD::FREM , MVT::f32, Expand); 1526 setOperationAction(ISD::FMA , MVT::f32, Expand); 1527 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1528 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1529 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1531 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1532 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1533 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1534 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 1535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1537 setOperationAction(ISD::FPOW , MVT::f128, Expand); 1538 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1539 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1540 1541 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1542 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1543 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1544 1545 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1546 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1547 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1548 1549 if (Subtarget->is64Bit()) { 1550 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1551 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1552 setOperationAction(ISD::MULHU, MVT::i64, Expand); 1553 setOperationAction(ISD::MULHS, MVT::i64, Expand); 1554 1555 setOperationAction(ISD::UMULO, MVT::i64, Custom); 1556 setOperationAction(ISD::SMULO, MVT::i64, Custom); 1557 1558 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 1559 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 1560 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 1561 } 1562 1563 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1564 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1565 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1566 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1567 1568 setOperationAction(ISD::TRAP , MVT::Other, Legal); 1569 1570 // Use the default implementation. 1571 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1572 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1573 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1574 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1575 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1576 1577 setExceptionPointerRegister(SP::I0); 1578 setExceptionSelectorRegister(SP::I1); 1579 1580 setStackPointerRegisterToSaveRestore(SP::O6); 1581 1582 setOperationAction(ISD::CTPOP, MVT::i32, 1583 Subtarget->usePopc() ? Legal : Expand); 1584 1585 if (Subtarget->isV9() && Subtarget->hasHardQuad()) { 1586 setOperationAction(ISD::LOAD, MVT::f128, Legal); 1587 setOperationAction(ISD::STORE, MVT::f128, Legal); 1588 } else { 1589 setOperationAction(ISD::LOAD, MVT::f128, Custom); 1590 setOperationAction(ISD::STORE, MVT::f128, Custom); 1591 } 1592 1593 if (Subtarget->hasHardQuad()) { 1594 setOperationAction(ISD::FADD, MVT::f128, Legal); 1595 setOperationAction(ISD::FSUB, MVT::f128, Legal); 1596 setOperationAction(ISD::FMUL, MVT::f128, Legal); 1597 setOperationAction(ISD::FDIV, MVT::f128, Legal); 1598 setOperationAction(ISD::FSQRT, MVT::f128, Legal); 1599 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); 1600 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); 1601 if (Subtarget->isV9()) { 1602 setOperationAction(ISD::FNEG, MVT::f128, Legal); 1603 setOperationAction(ISD::FABS, MVT::f128, Legal); 1604 } else { 1605 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1606 setOperationAction(ISD::FABS, MVT::f128, Custom); 1607 } 1608 1609 if (!Subtarget->is64Bit()) { 1610 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1611 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1612 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1613 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1614 } 1615 1616 } else { 1617 // Custom legalize f128 operations. 1618 1619 setOperationAction(ISD::FADD, MVT::f128, Custom); 1620 setOperationAction(ISD::FSUB, MVT::f128, Custom); 1621 setOperationAction(ISD::FMUL, MVT::f128, Custom); 1622 setOperationAction(ISD::FDIV, MVT::f128, Custom); 1623 setOperationAction(ISD::FSQRT, MVT::f128, Custom); 1624 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1625 setOperationAction(ISD::FABS, MVT::f128, Custom); 1626 1627 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 1628 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 1629 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 1630 1631 // Setup Runtime library names. 1632 if (Subtarget->is64Bit()) { 1633 setLibcallName(RTLIB::ADD_F128, "_Qp_add"); 1634 setLibcallName(RTLIB::SUB_F128, "_Qp_sub"); 1635 setLibcallName(RTLIB::MUL_F128, "_Qp_mul"); 1636 setLibcallName(RTLIB::DIV_F128, "_Qp_div"); 1637 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt"); 1638 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi"); 1639 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui"); 1640 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq"); 1641 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq"); 1642 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox"); 1643 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux"); 1644 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq"); 1645 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq"); 1646 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq"); 1647 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq"); 1648 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos"); 1649 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod"); 1650 } else { 1651 setLibcallName(RTLIB::ADD_F128, "_Q_add"); 1652 setLibcallName(RTLIB::SUB_F128, "_Q_sub"); 1653 setLibcallName(RTLIB::MUL_F128, "_Q_mul"); 1654 setLibcallName(RTLIB::DIV_F128, "_Q_div"); 1655 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt"); 1656 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi"); 1657 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou"); 1658 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq"); 1659 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq"); 1660 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1661 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1662 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1663 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1664 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq"); 1665 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq"); 1666 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos"); 1667 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod"); 1668 } 1669 } 1670 1671 setMinFunctionAlignment(2); 1672 1673 computeRegisterProperties(); 1674} 1675 1676const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1677 switch (Opcode) { 1678 default: return 0; 1679 case SPISD::CMPICC: return "SPISD::CMPICC"; 1680 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1681 case SPISD::BRICC: return "SPISD::BRICC"; 1682 case SPISD::BRXCC: return "SPISD::BRXCC"; 1683 case SPISD::BRFCC: return "SPISD::BRFCC"; 1684 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1685 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1686 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1687 case SPISD::Hi: return "SPISD::Hi"; 1688 case SPISD::Lo: return "SPISD::Lo"; 1689 case SPISD::FTOI: return "SPISD::FTOI"; 1690 case SPISD::ITOF: return "SPISD::ITOF"; 1691 case SPISD::FTOX: return "SPISD::FTOX"; 1692 case SPISD::XTOF: return "SPISD::XTOF"; 1693 case SPISD::CALL: return "SPISD::CALL"; 1694 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1695 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1696 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1697 case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; 1698 case SPISD::TLS_LD: return "SPISD::TLS_LD"; 1699 case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; 1700 } 1701} 1702 1703EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 1704 if (!VT.isVector()) 1705 return MVT::i32; 1706 return VT.changeVectorElementTypeToInteger(); 1707} 1708 1709/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1710/// be zero. Op is expected to be a target specific node. Used by DAG 1711/// combiner. 1712void SparcTargetLowering::computeMaskedBitsForTargetNode 1713 (const SDValue Op, 1714 APInt &KnownZero, 1715 APInt &KnownOne, 1716 const SelectionDAG &DAG, 1717 unsigned Depth) const { 1718 APInt KnownZero2, KnownOne2; 1719 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1720 1721 switch (Op.getOpcode()) { 1722 default: break; 1723 case SPISD::SELECT_ICC: 1724 case SPISD::SELECT_XCC: 1725 case SPISD::SELECT_FCC: 1726 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1727 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1728 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1729 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1730 1731 // Only known if known in both the LHS and RHS. 1732 KnownOne &= KnownOne2; 1733 KnownZero &= KnownZero2; 1734 break; 1735 } 1736} 1737 1738// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1739// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1740static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1741 ISD::CondCode CC, unsigned &SPCC) { 1742 if (isa<ConstantSDNode>(RHS) && 1743 cast<ConstantSDNode>(RHS)->isNullValue() && 1744 CC == ISD::SETNE && 1745 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1746 LHS.getOpcode() == SPISD::SELECT_XCC) && 1747 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1748 (LHS.getOpcode() == SPISD::SELECT_FCC && 1749 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1750 isa<ConstantSDNode>(LHS.getOperand(0)) && 1751 isa<ConstantSDNode>(LHS.getOperand(1)) && 1752 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1753 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1754 SDValue CMPCC = LHS.getOperand(3); 1755 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1756 LHS = CMPCC.getOperand(0); 1757 RHS = CMPCC.getOperand(1); 1758 } 1759} 1760 1761// Convert to a target node and set target flags. 1762SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, 1763 SelectionDAG &DAG) const { 1764 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) 1765 return DAG.getTargetGlobalAddress(GA->getGlobal(), 1766 SDLoc(GA), 1767 GA->getValueType(0), 1768 GA->getOffset(), TF); 1769 1770 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) 1771 return DAG.getTargetConstantPool(CP->getConstVal(), 1772 CP->getValueType(0), 1773 CP->getAlignment(), 1774 CP->getOffset(), TF); 1775 1776 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) 1777 return DAG.getTargetBlockAddress(BA->getBlockAddress(), 1778 Op.getValueType(), 1779 0, 1780 TF); 1781 1782 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) 1783 return DAG.getTargetExternalSymbol(ES->getSymbol(), 1784 ES->getValueType(0), TF); 1785 1786 llvm_unreachable("Unhandled address SDNode"); 1787} 1788 1789// Split Op into high and low parts according to HiTF and LoTF. 1790// Return an ADD node combining the parts. 1791SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, 1792 unsigned HiTF, unsigned LoTF, 1793 SelectionDAG &DAG) const { 1794 SDLoc DL(Op); 1795 EVT VT = Op.getValueType(); 1796 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); 1797 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); 1798 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1799} 1800 1801// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, 1802// or ExternalSymbol SDNode. 1803SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { 1804 SDLoc DL(Op); 1805 EVT VT = getPointerTy(); 1806 1807 // Handle PIC mode first. 1808 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1809 // This is the pic32 code model, the GOT is known to be smaller than 4GB. 1810 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22, 1811 SparcMCExpr::VK_Sparc_GOT10, DAG); 1812 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); 1813 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); 1814 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1815 // function has calls. 1816 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1817 MFI->setHasCalls(true); 1818 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, 1819 MachinePointerInfo::getGOT(), false, false, false, 0); 1820 } 1821 1822 // This is one of the absolute code models. 1823 switch(getTargetMachine().getCodeModel()) { 1824 default: 1825 llvm_unreachable("Unsupported absolute code model"); 1826 case CodeModel::Small: 1827 // abs32. 1828 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, 1829 SparcMCExpr::VK_Sparc_LO, DAG); 1830 case CodeModel::Medium: { 1831 // abs44. 1832 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44, 1833 SparcMCExpr::VK_Sparc_M44, DAG); 1834 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); 1835 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG); 1836 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); 1837 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); 1838 } 1839 case CodeModel::Large: { 1840 // abs64. 1841 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH, 1842 SparcMCExpr::VK_Sparc_HM, DAG); 1843 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); 1844 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, 1845 SparcMCExpr::VK_Sparc_LO, DAG); 1846 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1847 } 1848 } 1849} 1850 1851SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1852 SelectionDAG &DAG) const { 1853 return makeAddress(Op, DAG); 1854} 1855 1856SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1857 SelectionDAG &DAG) const { 1858 return makeAddress(Op, DAG); 1859} 1860 1861SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, 1862 SelectionDAG &DAG) const { 1863 return makeAddress(Op, DAG); 1864} 1865 1866SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1867 SelectionDAG &DAG) const { 1868 1869 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1870 SDLoc DL(GA); 1871 const GlobalValue *GV = GA->getGlobal(); 1872 EVT PtrVT = getPointerTy(); 1873 1874 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1875 1876 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1877 unsigned HiTF = ((model == TLSModel::GeneralDynamic) 1878 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22 1879 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22); 1880 unsigned LoTF = ((model == TLSModel::GeneralDynamic) 1881 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10 1882 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10); 1883 unsigned addTF = ((model == TLSModel::GeneralDynamic) 1884 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD 1885 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD); 1886 unsigned callTF = ((model == TLSModel::GeneralDynamic) 1887 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL 1888 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL); 1889 1890 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG); 1891 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1892 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo, 1893 withTargetFlags(Op, addTF, DAG)); 1894 1895 SDValue Chain = DAG.getEntryNode(); 1896 SDValue InFlag; 1897 1898 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL); 1899 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); 1900 InFlag = Chain.getValue(1); 1901 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); 1902 SDValue Symbol = withTargetFlags(Op, callTF, DAG); 1903 1904 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1905 SmallVector<SDValue, 4> Ops; 1906 Ops.push_back(Chain); 1907 Ops.push_back(Callee); 1908 Ops.push_back(Symbol); 1909 Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); 1910 const uint32_t *Mask = getTargetMachine() 1911 .getRegisterInfo()->getCallPreservedMask(CallingConv::C); 1912 assert(Mask && "Missing call preserved mask for calling convention"); 1913 Ops.push_back(DAG.getRegisterMask(Mask)); 1914 Ops.push_back(InFlag); 1915 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size()); 1916 InFlag = Chain.getValue(1); 1917 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true), 1918 DAG.getIntPtrConstant(0, true), InFlag, DL); 1919 InFlag = Chain.getValue(1); 1920 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); 1921 1922 if (model != TLSModel::LocalDynamic) 1923 return Ret; 1924 1925 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1926 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG)); 1927 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1928 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG)); 1929 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1930 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo, 1931 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG)); 1932 } 1933 1934 if (model == TLSModel::InitialExec) { 1935 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX 1936 : SparcMCExpr::VK_Sparc_TLS_IE_LD); 1937 1938 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1939 1940 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1941 // function has calls. 1942 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1943 MFI->setHasCalls(true); 1944 1945 SDValue TGA = makeHiLoPair(Op, 1946 SparcMCExpr::VK_Sparc_TLS_IE_HI22, 1947 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG); 1948 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); 1949 SDValue Offset = DAG.getNode(SPISD::TLS_LD, 1950 DL, PtrVT, Ptr, 1951 withTargetFlags(Op, ldTF, DAG)); 1952 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, 1953 DAG.getRegister(SP::G7, PtrVT), Offset, 1954 withTargetFlags(Op, 1955 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG)); 1956 } 1957 1958 assert(model == TLSModel::LocalExec); 1959 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1960 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG)); 1961 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1962 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG)); 1963 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1964 1965 return DAG.getNode(ISD::ADD, DL, PtrVT, 1966 DAG.getRegister(SP::G7, PtrVT), Offset); 1967} 1968 1969SDValue 1970SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 1971 SDValue Arg, SDLoc DL, 1972 SelectionDAG &DAG) const { 1973 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1974 EVT ArgVT = Arg.getValueType(); 1975 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1976 1977 ArgListEntry Entry; 1978 Entry.Node = Arg; 1979 Entry.Ty = ArgTy; 1980 1981 if (ArgTy->isFP128Ty()) { 1982 // Create a stack object and pass the pointer to the library function. 1983 int FI = MFI->CreateStackObject(16, 8, false); 1984 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 1985 Chain = DAG.getStore(Chain, 1986 DL, 1987 Entry.Node, 1988 FIPtr, 1989 MachinePointerInfo(), 1990 false, 1991 false, 1992 8); 1993 1994 Entry.Node = FIPtr; 1995 Entry.Ty = PointerType::getUnqual(ArgTy); 1996 } 1997 Args.push_back(Entry); 1998 return Chain; 1999} 2000 2001SDValue 2002SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, 2003 const char *LibFuncName, 2004 unsigned numArgs) const { 2005 2006 ArgListTy Args; 2007 2008 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2009 2010 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy()); 2011 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext()); 2012 Type *RetTyABI = RetTy; 2013 SDValue Chain = DAG.getEntryNode(); 2014 SDValue RetPtr; 2015 2016 if (RetTy->isFP128Ty()) { 2017 // Create a Stack Object to receive the return value of type f128. 2018 ArgListEntry Entry; 2019 int RetFI = MFI->CreateStackObject(16, 8, false); 2020 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy()); 2021 Entry.Node = RetPtr; 2022 Entry.Ty = PointerType::getUnqual(RetTy); 2023 if (!Subtarget->is64Bit()) 2024 Entry.isSRet = true; 2025 Entry.isReturned = false; 2026 Args.push_back(Entry); 2027 RetTyABI = Type::getVoidTy(*DAG.getContext()); 2028 } 2029 2030 assert(Op->getNumOperands() >= numArgs && "Not enough operands!"); 2031 for (unsigned i = 0, e = numArgs; i != e; ++i) { 2032 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG); 2033 } 2034 TargetLowering:: 2035 CallLoweringInfo CLI(Chain, 2036 RetTyABI, 2037 false, false, false, false, 2038 0, CallingConv::C, 2039 false, false, true, 2040 Callee, Args, DAG, SDLoc(Op)); 2041 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 2042 2043 // chain is in second result. 2044 if (RetTyABI == RetTy) 2045 return CallInfo.first; 2046 2047 assert (RetTy->isFP128Ty() && "Unexpected return type!"); 2048 2049 Chain = CallInfo.second; 2050 2051 // Load RetPtr to get the return value. 2052 return DAG.getLoad(Op.getValueType(), 2053 SDLoc(Op), 2054 Chain, 2055 RetPtr, 2056 MachinePointerInfo(), 2057 false, false, false, 8); 2058} 2059 2060SDValue 2061SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, 2062 unsigned &SPCC, 2063 SDLoc DL, 2064 SelectionDAG &DAG) const { 2065 2066 const char *LibCall = 0; 2067 bool is64Bit = Subtarget->is64Bit(); 2068 switch(SPCC) { 2069 default: llvm_unreachable("Unhandled conditional code!"); 2070 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break; 2071 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break; 2072 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break; 2073 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break; 2074 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break; 2075 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break; 2076 case SPCC::FCC_UL : 2077 case SPCC::FCC_ULE: 2078 case SPCC::FCC_UG : 2079 case SPCC::FCC_UGE: 2080 case SPCC::FCC_U : 2081 case SPCC::FCC_O : 2082 case SPCC::FCC_LG : 2083 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break; 2084 } 2085 2086 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy()); 2087 Type *RetTy = Type::getInt32Ty(*DAG.getContext()); 2088 ArgListTy Args; 2089 SDValue Chain = DAG.getEntryNode(); 2090 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG); 2091 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG); 2092 2093 TargetLowering:: 2094 CallLoweringInfo CLI(Chain, 2095 RetTy, 2096 false, false, false, false, 2097 0, CallingConv::C, 2098 false, false, true, 2099 Callee, Args, DAG, DL); 2100 2101 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 2102 2103 // result is in first, and chain is in second result. 2104 SDValue Result = CallInfo.first; 2105 2106 switch(SPCC) { 2107 default: { 2108 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2109 SPCC = SPCC::ICC_NE; 2110 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2111 } 2112 case SPCC::FCC_UL : { 2113 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); 2114 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2115 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2116 SPCC = SPCC::ICC_NE; 2117 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2118 } 2119 case SPCC::FCC_ULE: { 2120 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType()); 2121 SPCC = SPCC::ICC_NE; 2122 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2123 } 2124 case SPCC::FCC_UG : { 2125 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2126 SPCC = SPCC::ICC_G; 2127 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2128 } 2129 case SPCC::FCC_UGE: { 2130 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2131 SPCC = SPCC::ICC_NE; 2132 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2133 } 2134 2135 case SPCC::FCC_U : { 2136 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2137 SPCC = SPCC::ICC_E; 2138 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2139 } 2140 case SPCC::FCC_O : { 2141 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2142 SPCC = SPCC::ICC_NE; 2143 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2144 } 2145 case SPCC::FCC_LG : { 2146 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2147 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2148 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2149 SPCC = SPCC::ICC_NE; 2150 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2151 } 2152 case SPCC::FCC_UE : { 2153 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2154 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2155 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2156 SPCC = SPCC::ICC_E; 2157 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2158 } 2159 } 2160} 2161 2162static SDValue 2163LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, 2164 const SparcTargetLowering &TLI) { 2165 2166 if (Op.getOperand(0).getValueType() == MVT::f64) 2167 return TLI.LowerF128Op(Op, DAG, 2168 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1); 2169 2170 if (Op.getOperand(0).getValueType() == MVT::f32) 2171 return TLI.LowerF128Op(Op, DAG, 2172 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1); 2173 2174 llvm_unreachable("fpextend with non-float operand!"); 2175 return SDValue(0, 0); 2176} 2177 2178static SDValue 2179LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, 2180 const SparcTargetLowering &TLI) { 2181 // FP_ROUND on f64 and f32 are legal. 2182 if (Op.getOperand(0).getValueType() != MVT::f128) 2183 return Op; 2184 2185 if (Op.getValueType() == MVT::f64) 2186 return TLI.LowerF128Op(Op, DAG, 2187 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1); 2188 if (Op.getValueType() == MVT::f32) 2189 return TLI.LowerF128Op(Op, DAG, 2190 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1); 2191 2192 llvm_unreachable("fpround to non-float!"); 2193 return SDValue(0, 0); 2194} 2195 2196static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, 2197 const SparcTargetLowering &TLI, 2198 bool hasHardQuad) { 2199 SDLoc dl(Op); 2200 EVT VT = Op.getValueType(); 2201 assert(VT == MVT::i32 || VT == MVT::i64); 2202 2203 // Expand f128 operations to fp128 abi calls. 2204 if (Op.getOperand(0).getValueType() == MVT::f128 2205 && (!hasHardQuad || !TLI.isTypeLegal(VT))) { 2206 const char *libName = TLI.getLibcallName(VT == MVT::i32 2207 ? RTLIB::FPTOSINT_F128_I32 2208 : RTLIB::FPTOSINT_F128_I64); 2209 return TLI.LowerF128Op(Op, DAG, libName, 1); 2210 } 2211 2212 // Expand if the resulting type is illegal. 2213 if (!TLI.isTypeLegal(VT)) 2214 return SDValue(0, 0); 2215 2216 // Otherwise, Convert the fp value to integer in an FP register. 2217 if (VT == MVT::i32) 2218 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 2219 else 2220 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); 2221 2222 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 2223} 2224 2225static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2226 const SparcTargetLowering &TLI, 2227 bool hasHardQuad) { 2228 SDLoc dl(Op); 2229 EVT OpVT = Op.getOperand(0).getValueType(); 2230 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); 2231 2232 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; 2233 2234 // Expand f128 operations to fp128 ABI calls. 2235 if (Op.getValueType() == MVT::f128 2236 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { 2237 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 2238 ? RTLIB::SINTTOFP_I32_F128 2239 : RTLIB::SINTTOFP_I64_F128); 2240 return TLI.LowerF128Op(Op, DAG, libName, 1); 2241 } 2242 2243 // Expand if the operand type is illegal. 2244 if (!TLI.isTypeLegal(OpVT)) 2245 return SDValue(0, 0); 2246 2247 // Otherwise, Convert the int value to FP in an FP register. 2248 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); 2249 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; 2250 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp); 2251} 2252 2253static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, 2254 const SparcTargetLowering &TLI, 2255 bool hasHardQuad) { 2256 SDLoc dl(Op); 2257 EVT VT = Op.getValueType(); 2258 2259 // Expand if it does not involve f128 or the target has support for 2260 // quad floating point instructions and the resulting type is legal. 2261 if (Op.getOperand(0).getValueType() != MVT::f128 || 2262 (hasHardQuad && TLI.isTypeLegal(VT))) 2263 return SDValue(0, 0); 2264 2265 assert(VT == MVT::i32 || VT == MVT::i64); 2266 2267 return TLI.LowerF128Op(Op, DAG, 2268 TLI.getLibcallName(VT == MVT::i32 2269 ? RTLIB::FPTOUINT_F128_I32 2270 : RTLIB::FPTOUINT_F128_I64), 2271 1); 2272} 2273 2274static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2275 const SparcTargetLowering &TLI, 2276 bool hasHardQuad) { 2277 SDLoc dl(Op); 2278 EVT OpVT = Op.getOperand(0).getValueType(); 2279 assert(OpVT == MVT::i32 || OpVT == MVT::i64); 2280 2281 // Expand if it does not involve f128 or the target has support for 2282 // quad floating point instructions and the operand type is legal. 2283 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) 2284 return SDValue(0, 0); 2285 2286 return TLI.LowerF128Op(Op, DAG, 2287 TLI.getLibcallName(OpVT == MVT::i32 2288 ? RTLIB::UINTTOFP_I32_F128 2289 : RTLIB::UINTTOFP_I64_F128), 2290 1); 2291} 2292 2293static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 2294 const SparcTargetLowering &TLI, 2295 bool hasHardQuad) { 2296 SDValue Chain = Op.getOperand(0); 2297 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2298 SDValue LHS = Op.getOperand(2); 2299 SDValue RHS = Op.getOperand(3); 2300 SDValue Dest = Op.getOperand(4); 2301 SDLoc dl(Op); 2302 unsigned Opc, SPCC = ~0U; 2303 2304 // If this is a br_cc of a "setcc", and if the setcc got lowered into 2305 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2306 LookThroughSetCC(LHS, RHS, CC, SPCC); 2307 2308 // Get the condition flag. 2309 SDValue CompareFlag; 2310 if (LHS.getValueType().isInteger()) { 2311 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2312 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2313 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 2314 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 2315 } else { 2316 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2317 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2318 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2319 Opc = SPISD::BRICC; 2320 } else { 2321 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2322 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2323 Opc = SPISD::BRFCC; 2324 } 2325 } 2326 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 2327 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2328} 2329 2330static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 2331 const SparcTargetLowering &TLI, 2332 bool hasHardQuad) { 2333 SDValue LHS = Op.getOperand(0); 2334 SDValue RHS = Op.getOperand(1); 2335 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2336 SDValue TrueVal = Op.getOperand(2); 2337 SDValue FalseVal = Op.getOperand(3); 2338 SDLoc dl(Op); 2339 unsigned Opc, SPCC = ~0U; 2340 2341 // If this is a select_cc of a "setcc", and if the setcc got lowered into 2342 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2343 LookThroughSetCC(LHS, RHS, CC, SPCC); 2344 2345 SDValue CompareFlag; 2346 if (LHS.getValueType().isInteger()) { 2347 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2348 Opc = LHS.getValueType() == MVT::i32 ? 2349 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 2350 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2351 } else { 2352 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2353 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2354 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2355 Opc = SPISD::SELECT_ICC; 2356 } else { 2357 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2358 Opc = SPISD::SELECT_FCC; 2359 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2360 } 2361 } 2362 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 2363 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2364} 2365 2366static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 2367 const SparcTargetLowering &TLI) { 2368 MachineFunction &MF = DAG.getMachineFunction(); 2369 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 2370 2371 // Need frame address to find the address of VarArgsFrameIndex. 2372 MF.getFrameInfo()->setFrameAddressIsTaken(true); 2373 2374 // vastart just stores the address of the VarArgsFrameIndex slot into the 2375 // memory location argument. 2376 SDLoc DL(Op); 2377 SDValue Offset = 2378 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), 2379 DAG.getRegister(SP::I6, TLI.getPointerTy()), 2380 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); 2381 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2382 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), 2383 MachinePointerInfo(SV), false, false, 0); 2384} 2385 2386static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 2387 SDNode *Node = Op.getNode(); 2388 EVT VT = Node->getValueType(0); 2389 SDValue InChain = Node->getOperand(0); 2390 SDValue VAListPtr = Node->getOperand(1); 2391 EVT PtrVT = VAListPtr.getValueType(); 2392 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2393 SDLoc DL(Node); 2394 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr, 2395 MachinePointerInfo(SV), false, false, false, 0); 2396 // Increment the pointer, VAList, to the next vaarg. 2397 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, 2398 DAG.getIntPtrConstant(VT.getSizeInBits()/8)); 2399 // Store the incremented VAList to the legalized pointer. 2400 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, 2401 VAListPtr, MachinePointerInfo(SV), false, false, 0); 2402 // Load the actual argument out of the pointer VAList. 2403 // We can't count on greater alignment than the word size. 2404 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), 2405 false, false, false, 2406 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); 2407} 2408 2409static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 2410 const SparcSubtarget *Subtarget) { 2411 SDValue Chain = Op.getOperand(0); // Legalize the chain. 2412 SDValue Size = Op.getOperand(1); // Legalize the size. 2413 EVT VT = Size->getValueType(0); 2414 SDLoc dl(Op); 2415 2416 unsigned SPReg = SP::O6; 2417 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 2418 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 2419 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 2420 2421 // The resultant pointer is actually 16 words from the bottom of the stack, 2422 // to provide a register spill area. 2423 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96; 2424 regSpillArea += Subtarget->getStackPointerBias(); 2425 2426 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, 2427 DAG.getConstant(regSpillArea, VT)); 2428 SDValue Ops[2] = { NewVal, Chain }; 2429 return DAG.getMergeValues(Ops, 2, dl); 2430} 2431 2432 2433static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 2434 SDLoc dl(Op); 2435 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 2436 dl, MVT::Other, DAG.getEntryNode()); 2437 return Chain; 2438} 2439 2440static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, 2441 const SparcSubtarget *Subtarget) { 2442 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2443 MFI->setFrameAddressIsTaken(true); 2444 2445 EVT VT = Op.getValueType(); 2446 SDLoc dl(Op); 2447 unsigned FrameReg = SP::I6; 2448 unsigned stackBias = Subtarget->getStackPointerBias(); 2449 2450 SDValue FrameAddr; 2451 2452 if (depth == 0) { 2453 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2454 if (Subtarget->is64Bit()) 2455 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2456 DAG.getIntPtrConstant(stackBias)); 2457 return FrameAddr; 2458 } 2459 2460 // flush first to make sure the windowed registers' values are in stack 2461 SDValue Chain = getFLUSHW(Op, DAG); 2462 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 2463 2464 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56; 2465 2466 while (depth--) { 2467 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2468 DAG.getIntPtrConstant(Offset)); 2469 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(), 2470 false, false, false, 0); 2471 } 2472 if (Subtarget->is64Bit()) 2473 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2474 DAG.getIntPtrConstant(stackBias)); 2475 return FrameAddr; 2476} 2477 2478 2479static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, 2480 const SparcSubtarget *Subtarget) { 2481 2482 uint64_t depth = Op.getConstantOperandVal(0); 2483 2484 return getFRAMEADDR(depth, Op, DAG, Subtarget); 2485 2486} 2487 2488static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, 2489 const SparcTargetLowering &TLI, 2490 const SparcSubtarget *Subtarget) { 2491 MachineFunction &MF = DAG.getMachineFunction(); 2492 MachineFrameInfo *MFI = MF.getFrameInfo(); 2493 MFI->setReturnAddressIsTaken(true); 2494 2495 EVT VT = Op.getValueType(); 2496 SDLoc dl(Op); 2497 uint64_t depth = Op.getConstantOperandVal(0); 2498 2499 SDValue RetAddr; 2500 if (depth == 0) { 2501 unsigned RetReg = MF.addLiveIn(SP::I7, 2502 TLI.getRegClassFor(TLI.getPointerTy())); 2503 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 2504 return RetAddr; 2505 } 2506 2507 // Need frame address to find return address of the caller. 2508 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget); 2509 2510 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60; 2511 SDValue Ptr = DAG.getNode(ISD::ADD, 2512 dl, VT, 2513 FrameAddr, 2514 DAG.getIntPtrConstant(Offset)); 2515 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, 2516 MachinePointerInfo(), false, false, false, 0); 2517 2518 return RetAddr; 2519} 2520 2521static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) 2522{ 2523 SDLoc dl(Op); 2524 2525 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); 2526 assert(opcode == ISD::FNEG || opcode == ISD::FABS); 2527 2528 // Lower fneg/fabs on f64 to fneg/fabs on f32. 2529 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. 2530 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd. 2531 2532 SDValue SrcReg64 = Op.getOperand(0); 2533 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, 2534 SrcReg64); 2535 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, 2536 SrcReg64); 2537 2538 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); 2539 2540 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2541 dl, MVT::f64), 0); 2542 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, 2543 DstReg64, Hi32); 2544 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, 2545 DstReg64, Lo32); 2546 return DstReg64; 2547} 2548 2549// Lower a f128 load into two f64 loads. 2550static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) 2551{ 2552 SDLoc dl(Op); 2553 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode()); 2554 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF 2555 && "Unexpected node type"); 2556 2557 unsigned alignment = LdNode->getAlignment(); 2558 if (alignment > 8) 2559 alignment = 8; 2560 2561 SDValue Hi64 = DAG.getLoad(MVT::f64, 2562 dl, 2563 LdNode->getChain(), 2564 LdNode->getBasePtr(), 2565 LdNode->getPointerInfo(), 2566 false, false, false, alignment); 2567 EVT addrVT = LdNode->getBasePtr().getValueType(); 2568 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2569 LdNode->getBasePtr(), 2570 DAG.getConstant(8, addrVT)); 2571 SDValue Lo64 = DAG.getLoad(MVT::f64, 2572 dl, 2573 LdNode->getChain(), 2574 LoPtr, 2575 LdNode->getPointerInfo(), 2576 false, false, false, alignment); 2577 2578 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2579 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2580 2581 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2582 dl, MVT::f128); 2583 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2584 MVT::f128, 2585 SDValue(InFP128, 0), 2586 Hi64, 2587 SubRegEven); 2588 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2589 MVT::f128, 2590 SDValue(InFP128, 0), 2591 Lo64, 2592 SubRegOdd); 2593 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1), 2594 SDValue(Lo64.getNode(), 1) }; 2595 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2596 &OutChains[0], 2); 2597 SDValue Ops[2] = {SDValue(InFP128,0), OutChain}; 2598 return DAG.getMergeValues(Ops, 2, dl); 2599} 2600 2601// Lower a f128 store into two f64 stores. 2602static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { 2603 SDLoc dl(Op); 2604 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); 2605 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF 2606 && "Unexpected node type"); 2607 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2608 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2609 2610 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2611 dl, 2612 MVT::f64, 2613 StNode->getValue(), 2614 SubRegEven); 2615 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2616 dl, 2617 MVT::f64, 2618 StNode->getValue(), 2619 SubRegOdd); 2620 2621 unsigned alignment = StNode->getAlignment(); 2622 if (alignment > 8) 2623 alignment = 8; 2624 2625 SDValue OutChains[2]; 2626 OutChains[0] = DAG.getStore(StNode->getChain(), 2627 dl, 2628 SDValue(Hi64, 0), 2629 StNode->getBasePtr(), 2630 MachinePointerInfo(), 2631 false, false, alignment); 2632 EVT addrVT = StNode->getBasePtr().getValueType(); 2633 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2634 StNode->getBasePtr(), 2635 DAG.getConstant(8, addrVT)); 2636 OutChains[1] = DAG.getStore(StNode->getChain(), 2637 dl, 2638 SDValue(Lo64, 0), 2639 LoPtr, 2640 MachinePointerInfo(), 2641 false, false, alignment); 2642 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2643 &OutChains[0], 2); 2644} 2645 2646static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { 2647 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) && "invalid"); 2648 2649 if (Op.getValueType() == MVT::f64) 2650 return LowerF64Op(Op, DAG, Op.getOpcode()); 2651 if (Op.getValueType() != MVT::f128) 2652 return Op; 2653 2654 // Lower fabs/fneg on f128 to fabs/fneg on f64 2655 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64 2656 2657 SDLoc dl(Op); 2658 SDValue SrcReg128 = Op.getOperand(0); 2659 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, 2660 SrcReg128); 2661 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, 2662 SrcReg128); 2663 if (isV9) 2664 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); 2665 else 2666 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode()); 2667 2668 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2669 dl, MVT::f128), 0); 2670 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, 2671 DstReg128, Hi64); 2672 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, 2673 DstReg128, Lo64); 2674 return DstReg128; 2675} 2676 2677static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 2678 2679 if (Op.getValueType() != MVT::i64) 2680 return Op; 2681 2682 SDLoc dl(Op); 2683 SDValue Src1 = Op.getOperand(0); 2684 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); 2685 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, 2686 DAG.getConstant(32, MVT::i64)); 2687 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); 2688 2689 SDValue Src2 = Op.getOperand(1); 2690 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2691 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, 2692 DAG.getConstant(32, MVT::i64)); 2693 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); 2694 2695 2696 bool hasChain = false; 2697 unsigned hiOpc = Op.getOpcode(); 2698 switch (Op.getOpcode()) { 2699 default: llvm_unreachable("Invalid opcode"); 2700 case ISD::ADDC: hiOpc = ISD::ADDE; break; 2701 case ISD::ADDE: hasChain = true; break; 2702 case ISD::SUBC: hiOpc = ISD::SUBE; break; 2703 case ISD::SUBE: hasChain = true; break; 2704 } 2705 SDValue Lo; 2706 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); 2707 if (hasChain) { 2708 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo, 2709 Op.getOperand(2)); 2710 } else { 2711 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo); 2712 } 2713 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1)); 2714 SDValue Carry = Hi.getValue(1); 2715 2716 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); 2717 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); 2718 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, 2719 DAG.getConstant(32, MVT::i64)); 2720 2721 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); 2722 SDValue Ops[2] = { Dst, Carry }; 2723 return DAG.getMergeValues(Ops, 2, dl); 2724} 2725 2726// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode() 2727// in LegalizeDAG.cpp except the order of arguments to the library function. 2728static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, 2729 const SparcTargetLowering &TLI) 2730{ 2731 unsigned opcode = Op.getOpcode(); 2732 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); 2733 2734 bool isSigned = (opcode == ISD::SMULO); 2735 EVT VT = MVT::i64; 2736 EVT WideVT = MVT::i128; 2737 SDLoc dl(Op); 2738 SDValue LHS = Op.getOperand(0); 2739 2740 if (LHS.getValueType() != VT) 2741 return Op; 2742 2743 SDValue ShiftAmt = DAG.getConstant(63, VT); 2744 2745 SDValue RHS = Op.getOperand(1); 2746 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); 2747 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); 2748 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; 2749 2750 SDValue MulResult = TLI.makeLibCall(DAG, 2751 RTLIB::MUL_I128, WideVT, 2752 Args, 4, isSigned, dl).first; 2753 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, 2754 MulResult, DAG.getIntPtrConstant(0)); 2755 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, 2756 MulResult, DAG.getIntPtrConstant(1)); 2757 if (isSigned) { 2758 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); 2759 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); 2760 } else { 2761 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT), 2762 ISD::SETNE); 2763 } 2764 // MulResult is a node with an illegal type. Because such things are not 2765 // generally permitted during this phase of legalization, delete the 2766 // node. The above EXTRACT_ELEMENT nodes should have been folded. 2767 DAG.DeleteNode(MulResult.getNode()); 2768 2769 SDValue Ops[2] = { BottomHalf, TopHalf } ; 2770 return DAG.getMergeValues(Ops, 2, dl); 2771} 2772 2773static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) { 2774 // Monotonic load/stores are legal. 2775 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 2776 return Op; 2777 2778 // Otherwise, expand with a fence. 2779 return SDValue(); 2780} 2781 2782 2783SDValue SparcTargetLowering:: 2784LowerOperation(SDValue Op, SelectionDAG &DAG) const { 2785 2786 bool hasHardQuad = Subtarget->hasHardQuad(); 2787 bool isV9 = Subtarget->isV9(); 2788 2789 switch (Op.getOpcode()) { 2790 default: llvm_unreachable("Should not custom lower this!"); 2791 2792 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, 2793 Subtarget); 2794 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, 2795 Subtarget); 2796 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2797 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2798 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 2799 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2800 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, 2801 hasHardQuad); 2802 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, 2803 hasHardQuad); 2804 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, 2805 hasHardQuad); 2806 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, 2807 hasHardQuad); 2808 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, 2809 hasHardQuad); 2810 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, 2811 hasHardQuad); 2812 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 2813 case ISD::VAARG: return LowerVAARG(Op, DAG); 2814 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, 2815 Subtarget); 2816 2817 case ISD::LOAD: return LowerF128Load(Op, DAG); 2818 case ISD::STORE: return LowerF128Store(Op, DAG); 2819 case ISD::FADD: return LowerF128Op(Op, DAG, 2820 getLibcallName(RTLIB::ADD_F128), 2); 2821 case ISD::FSUB: return LowerF128Op(Op, DAG, 2822 getLibcallName(RTLIB::SUB_F128), 2); 2823 case ISD::FMUL: return LowerF128Op(Op, DAG, 2824 getLibcallName(RTLIB::MUL_F128), 2); 2825 case ISD::FDIV: return LowerF128Op(Op, DAG, 2826 getLibcallName(RTLIB::DIV_F128), 2); 2827 case ISD::FSQRT: return LowerF128Op(Op, DAG, 2828 getLibcallName(RTLIB::SQRT_F128),1); 2829 case ISD::FABS: 2830 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); 2831 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); 2832 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); 2833 case ISD::ADDC: 2834 case ISD::ADDE: 2835 case ISD::SUBC: 2836 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 2837 case ISD::UMULO: 2838 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); 2839 case ISD::ATOMIC_LOAD: 2840 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); 2841 } 2842} 2843 2844MachineBasicBlock * 2845SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 2846 MachineBasicBlock *BB) const { 2847 switch (MI->getOpcode()) { 2848 default: llvm_unreachable("Unknown SELECT_CC!"); 2849 case SP::SELECT_CC_Int_ICC: 2850 case SP::SELECT_CC_FP_ICC: 2851 case SP::SELECT_CC_DFP_ICC: 2852 case SP::SELECT_CC_QFP_ICC: 2853 return expandSelectCC(MI, BB, SP::BCOND); 2854 case SP::SELECT_CC_Int_FCC: 2855 case SP::SELECT_CC_FP_FCC: 2856 case SP::SELECT_CC_DFP_FCC: 2857 case SP::SELECT_CC_QFP_FCC: 2858 return expandSelectCC(MI, BB, SP::FBCOND); 2859 2860 case SP::ATOMIC_LOAD_ADD_32: 2861 return expandAtomicRMW(MI, BB, SP::ADDrr); 2862 case SP::ATOMIC_LOAD_ADD_64: 2863 return expandAtomicRMW(MI, BB, SP::ADDXrr); 2864 case SP::ATOMIC_LOAD_SUB_32: 2865 return expandAtomicRMW(MI, BB, SP::SUBrr); 2866 case SP::ATOMIC_LOAD_SUB_64: 2867 return expandAtomicRMW(MI, BB, SP::SUBXrr); 2868 case SP::ATOMIC_LOAD_AND_32: 2869 return expandAtomicRMW(MI, BB, SP::ANDrr); 2870 case SP::ATOMIC_LOAD_AND_64: 2871 return expandAtomicRMW(MI, BB, SP::ANDXrr); 2872 case SP::ATOMIC_LOAD_OR_32: 2873 return expandAtomicRMW(MI, BB, SP::ORrr); 2874 case SP::ATOMIC_LOAD_OR_64: 2875 return expandAtomicRMW(MI, BB, SP::ORXrr); 2876 case SP::ATOMIC_LOAD_XOR_32: 2877 return expandAtomicRMW(MI, BB, SP::XORrr); 2878 case SP::ATOMIC_LOAD_XOR_64: 2879 return expandAtomicRMW(MI, BB, SP::XORXrr); 2880 case SP::ATOMIC_LOAD_NAND_32: 2881 return expandAtomicRMW(MI, BB, SP::ANDrr); 2882 case SP::ATOMIC_LOAD_NAND_64: 2883 return expandAtomicRMW(MI, BB, SP::ANDXrr); 2884 2885 case SP::ATOMIC_SWAP_64: 2886 return expandAtomicRMW(MI, BB, 0); 2887 2888 case SP::ATOMIC_LOAD_MAX_32: 2889 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G); 2890 case SP::ATOMIC_LOAD_MAX_64: 2891 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G); 2892 case SP::ATOMIC_LOAD_MIN_32: 2893 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE); 2894 case SP::ATOMIC_LOAD_MIN_64: 2895 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE); 2896 case SP::ATOMIC_LOAD_UMAX_32: 2897 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU); 2898 case SP::ATOMIC_LOAD_UMAX_64: 2899 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU); 2900 case SP::ATOMIC_LOAD_UMIN_32: 2901 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU); 2902 case SP::ATOMIC_LOAD_UMIN_64: 2903 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU); 2904 } 2905} 2906 2907MachineBasicBlock* 2908SparcTargetLowering::expandSelectCC(MachineInstr *MI, 2909 MachineBasicBlock *BB, 2910 unsigned BROpcode) const { 2911 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 2912 DebugLoc dl = MI->getDebugLoc(); 2913 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 2914 2915 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2916 // control-flow pattern. The incoming instruction knows the destination vreg 2917 // to set, the condition code register to branch on, the true/false values to 2918 // select between, and a branch opcode to use. 2919 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2920 MachineFunction::iterator It = BB; 2921 ++It; 2922 2923 // thisMBB: 2924 // ... 2925 // TrueVal = ... 2926 // [f]bCC copy1MBB 2927 // fallthrough --> copy0MBB 2928 MachineBasicBlock *thisMBB = BB; 2929 MachineFunction *F = BB->getParent(); 2930 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 2931 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 2932 F->insert(It, copy0MBB); 2933 F->insert(It, sinkMBB); 2934 2935 // Transfer the remainder of BB and its successor edges to sinkMBB. 2936 sinkMBB->splice(sinkMBB->begin(), BB, 2937 llvm::next(MachineBasicBlock::iterator(MI)), 2938 BB->end()); 2939 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 2940 2941 // Add the true and fallthrough blocks as its successors. 2942 BB->addSuccessor(copy0MBB); 2943 BB->addSuccessor(sinkMBB); 2944 2945 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 2946 2947 // copy0MBB: 2948 // %FalseValue = ... 2949 // # fallthrough to sinkMBB 2950 BB = copy0MBB; 2951 2952 // Update machine-CFG edges 2953 BB->addSuccessor(sinkMBB); 2954 2955 // sinkMBB: 2956 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2957 // ... 2958 BB = sinkMBB; 2959 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 2960 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 2961 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 2962 2963 MI->eraseFromParent(); // The pseudo instruction is gone now. 2964 return BB; 2965} 2966 2967MachineBasicBlock* 2968SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, 2969 MachineBasicBlock *MBB, 2970 unsigned Opcode, 2971 unsigned CondCode) const { 2972 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 2973 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 2974 DebugLoc DL = MI->getDebugLoc(); 2975 2976 // MI is an atomic read-modify-write instruction of the form: 2977 // 2978 // rd = atomicrmw<op> addr, rs2 2979 // 2980 // All three operands are registers. 2981 unsigned DestReg = MI->getOperand(0).getReg(); 2982 unsigned AddrReg = MI->getOperand(1).getReg(); 2983 unsigned Rs2Reg = MI->getOperand(2).getReg(); 2984 2985 // SelectionDAG has already inserted memory barriers before and after MI, so 2986 // we simply have to implement the operatiuon in terms of compare-and-swap. 2987 // 2988 // %val0 = load %addr 2989 // loop: 2990 // %val = phi %val0, %dest 2991 // %upd = op %val, %rs2 2992 // %dest = cas %addr, %val, %upd 2993 // cmp %val, %dest 2994 // bne loop 2995 // done: 2996 // 2997 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); 2998 const TargetRegisterClass *ValueRC = 2999 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 3000 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC); 3001 3002 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) 3003 .addReg(AddrReg).addImm(0); 3004 3005 // Split the basic block MBB before MI and insert the loop block in the hole. 3006 MachineFunction::iterator MFI = MBB; 3007 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 3008 MachineFunction *MF = MBB->getParent(); 3009 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3010 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3011 ++MFI; 3012 MF->insert(MFI, LoopMBB); 3013 MF->insert(MFI, DoneMBB); 3014 3015 // Move MI and following instructions to DoneMBB. 3016 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end()); 3017 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB); 3018 3019 // Connect the CFG again. 3020 MBB->addSuccessor(LoopMBB); 3021 LoopMBB->addSuccessor(LoopMBB); 3022 LoopMBB->addSuccessor(DoneMBB); 3023 3024 // Build the loop block. 3025 unsigned ValReg = MRI.createVirtualRegister(ValueRC); 3026 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP). 3027 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg); 3028 3029 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg) 3030 .addReg(Val0Reg).addMBB(MBB) 3031 .addReg(DestReg).addMBB(LoopMBB); 3032 3033 if (CondCode) { 3034 // This is one of the min/max operations. We need a CMPrr followed by a 3035 // MOVXCC/MOVICC. 3036 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg); 3037 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) 3038 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode); 3039 } else if (Opcode) { 3040 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) 3041 .addReg(ValReg).addReg(Rs2Reg); 3042 } 3043 3044 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 || 3045 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) { 3046 unsigned TmpReg = UpdReg; 3047 UpdReg = MRI.createVirtualRegister(ValueRC); 3048 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); 3049 } 3050 3051 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) 3052 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg) 3053 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 3054 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); 3055 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) 3056 .addMBB(LoopMBB).addImm(SPCC::ICC_NE); 3057 3058 MI->eraseFromParent(); 3059 return DoneMBB; 3060} 3061 3062//===----------------------------------------------------------------------===// 3063// Sparc Inline Assembly Support 3064//===----------------------------------------------------------------------===// 3065 3066/// getConstraintType - Given a constraint letter, return the type of 3067/// constraint it is for this target. 3068SparcTargetLowering::ConstraintType 3069SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 3070 if (Constraint.size() == 1) { 3071 switch (Constraint[0]) { 3072 default: break; 3073 case 'r': return C_RegisterClass; 3074 case 'I': // SIMM13 3075 return C_Other; 3076 } 3077 } 3078 3079 return TargetLowering::getConstraintType(Constraint); 3080} 3081 3082TargetLowering::ConstraintWeight SparcTargetLowering:: 3083getSingleConstraintMatchWeight(AsmOperandInfo &info, 3084 const char *constraint) const { 3085 ConstraintWeight weight = CW_Invalid; 3086 Value *CallOperandVal = info.CallOperandVal; 3087 // If we don't have a value, we can't do a match, 3088 // but allow it at the lowest weight. 3089 if (CallOperandVal == NULL) 3090 return CW_Default; 3091 3092 // Look at the constraint type. 3093 switch (*constraint) { 3094 default: 3095 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3096 break; 3097 case 'I': // SIMM13 3098 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 3099 if (isInt<13>(C->getSExtValue())) 3100 weight = CW_Constant; 3101 } 3102 break; 3103 } 3104 return weight; 3105} 3106 3107/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3108/// vector. If it is invalid, don't add anything to Ops. 3109void SparcTargetLowering:: 3110LowerAsmOperandForConstraint(SDValue Op, 3111 std::string &Constraint, 3112 std::vector<SDValue> &Ops, 3113 SelectionDAG &DAG) const { 3114 SDValue Result(0, 0); 3115 3116 // Only support length 1 constraints for now. 3117 if (Constraint.length() > 1) 3118 return; 3119 3120 char ConstraintLetter = Constraint[0]; 3121 switch (ConstraintLetter) { 3122 default: break; 3123 case 'I': 3124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3125 if (isInt<13>(C->getSExtValue())) { 3126 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType()); 3127 break; 3128 } 3129 return; 3130 } 3131 } 3132 3133 if (Result.getNode()) { 3134 Ops.push_back(Result); 3135 return; 3136 } 3137 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3138} 3139 3140std::pair<unsigned, const TargetRegisterClass*> 3141SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3142 MVT VT) const { 3143 if (Constraint.size() == 1) { 3144 switch (Constraint[0]) { 3145 case 'r': 3146 return std::make_pair(0U, &SP::IntRegsRegClass); 3147 } 3148 } else if (!Constraint.empty() && Constraint.size() <= 5 3149 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') { 3150 // constraint = '{r<d>}' 3151 // Remove the braces from around the name. 3152 StringRef name(Constraint.data()+1, Constraint.size()-2); 3153 // Handle register aliases: 3154 // r0-r7 -> g0-g7 3155 // r8-r15 -> o0-o7 3156 // r16-r23 -> l0-l7 3157 // r24-r31 -> i0-i7 3158 uint64_t intVal = 0; 3159 if (name.substr(0, 1).equals("r") 3160 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) { 3161 const char regTypes[] = { 'g', 'o', 'l', 'i' }; 3162 char regType = regTypes[intVal/8]; 3163 char regIdx = '0' + (intVal % 8); 3164 char tmp[] = { '{', regType, regIdx, '}', 0 }; 3165 std::string newConstraint = std::string(tmp); 3166 return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); 3167 } 3168 } 3169 3170 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3171} 3172 3173bool 3174SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3175 // The Sparc target isn't yet aware of offsets. 3176 return false; 3177} 3178 3179void SparcTargetLowering::ReplaceNodeResults(SDNode *N, 3180 SmallVectorImpl<SDValue>& Results, 3181 SelectionDAG &DAG) const { 3182 3183 SDLoc dl(N); 3184 3185 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL; 3186 3187 switch (N->getOpcode()) { 3188 default: 3189 llvm_unreachable("Do not know how to custom type legalize this operation!"); 3190 3191 case ISD::FP_TO_SINT: 3192 case ISD::FP_TO_UINT: 3193 // Custom lower only if it involves f128 or i64. 3194 if (N->getOperand(0).getValueType() != MVT::f128 3195 || N->getValueType(0) != MVT::i64) 3196 return; 3197 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) 3198 ? RTLIB::FPTOSINT_F128_I64 3199 : RTLIB::FPTOUINT_F128_I64); 3200 3201 Results.push_back(LowerF128Op(SDValue(N, 0), 3202 DAG, 3203 getLibcallName(libCall), 3204 1)); 3205 return; 3206 3207 case ISD::SINT_TO_FP: 3208 case ISD::UINT_TO_FP: 3209 // Custom lower only if it involves f128 or i64. 3210 if (N->getValueType(0) != MVT::f128 3211 || N->getOperand(0).getValueType() != MVT::i64) 3212 return; 3213 3214 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) 3215 ? RTLIB::SINTTOFP_I64_F128 3216 : RTLIB::UINTTOFP_I64_F128); 3217 3218 Results.push_back(LowerF128Op(SDValue(N, 0), 3219 DAG, 3220 getLibcallName(libCall), 3221 1)); 3222 return; 3223 } 3224} 3225