R600MachineScheduler.h revision 263508
1101043Sdes//===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===// 2101043Sdes// 3101043Sdes// The LLVM Compiler Infrastructure 4101043Sdes// 5101043Sdes// This file is distributed under the University of Illinois Open Source 6101043Sdes// License. See LICENSE.TXT for details. 7101043Sdes// 8101043Sdes//===----------------------------------------------------------------------===// 9101043Sdes// 10101043Sdes/// \file 11101043Sdes/// \brief R600 Machine Scheduler interface 12101043Sdes// 13101043Sdes//===----------------------------------------------------------------------===// 14101043Sdes 15101043Sdes#ifndef R600MACHINESCHEDULER_H_ 16101043Sdes#define R600MACHINESCHEDULER_H_ 17101043Sdes 18101043Sdes#include "R600InstrInfo.h" 19101043Sdes#include "llvm/ADT/PriorityQueue.h" 20101043Sdes#include "llvm/CodeGen/MachineScheduler.h" 21101043Sdes#include "llvm/Support/Debug.h" 22101043Sdes 23101043Sdesusing namespace llvm; 24101043Sdes 25101043Sdesnamespace llvm { 26101043Sdes 27101043Sdesclass R600SchedStrategy : public MachineSchedStrategy { 28101043Sdes 29101043Sdes const ScheduleDAGMI *DAG; 30101043Sdes const R600InstrInfo *TII; 31101043Sdes const R600RegisterInfo *TRI; 32101043Sdes MachineRegisterInfo *MRI; 33101043Sdes 34101043Sdes enum InstKind { 35101043Sdes IDAlu, 36101043Sdes IDFetch, 37101043Sdes IDOther, 38101043Sdes IDLast 39101043Sdes }; 40101043Sdes 41101043Sdes enum AluKind { 42101163Sdes AluAny, 43101163Sdes AluT_X, 44101043Sdes AluT_Y, 45101043Sdes AluT_Z, 46101043Sdes AluT_W, 47101043Sdes AluT_XYZW, 48101043Sdes AluPredX, 49101043Sdes AluTrans, 50101043Sdes AluDiscarded, // LLVM Instructions that are going to be eliminated 51101043Sdes AluLast 52101043Sdes }; 53101043Sdes 54101043Sdes std::vector<SUnit *> Available[IDLast], Pending[IDLast]; 55101043Sdes std::vector<SUnit *> AvailableAlus[AluLast]; 56101043Sdes std::vector<SUnit *> PhysicalRegCopy; 57101043Sdes 58101043Sdes InstKind CurInstKind; 59101043Sdes int CurEmitted; 60101043Sdes InstKind NextInstKind; 61101043Sdes 62101043Sdes unsigned AluInstCount; 63101043Sdes unsigned FetchInstCount; 64101043Sdes 65101043Sdes int InstKindLimit[IDLast]; 66101043Sdes 67101043Sdes int OccupedSlotsMask; 68101043Sdes 69101043Sdespublic: 70101043Sdes R600SchedStrategy() : 71101043Sdes DAG(0), TII(0), TRI(0), MRI(0) { 72101043Sdes } 73101043Sdes 74101043Sdes virtual ~R600SchedStrategy() { 75101043Sdes } 76101043Sdes 77101043Sdes virtual void initialize(ScheduleDAGMI *dag); 78101043Sdes virtual SUnit *pickNode(bool &IsTopNode); 79101043Sdes virtual void schedNode(SUnit *SU, bool IsTopNode); 80101043Sdes virtual void releaseTopNode(SUnit *SU); 81101043Sdes virtual void releaseBottomNode(SUnit *SU); 82101043Sdes 83101043Sdesprivate: 84101043Sdes std::vector<MachineInstr *> InstructionsGroupCandidate; 85101043Sdes bool VLIW5; 86101043Sdes 87101043Sdes int getInstKind(SUnit *SU); 88101043Sdes bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const; 89101043Sdes AluKind getAluKind(SUnit *SU) const; 90101043Sdes void LoadAlu(); 91101043Sdes unsigned AvailablesAluCount() const; 92101043Sdes SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu); 93101043Sdes void PrepareNextSlot(); 94101043Sdes SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU); 95101043Sdes 96101043Sdes void AssignSlot(MachineInstr *MI, unsigned Slot); 97101043Sdes SUnit* pickAlu(); 98101043Sdes SUnit* pickOther(int QID); 99101043Sdes void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst); 100101043Sdes}; 101101043Sdes 102101043Sdes} // namespace llvm 103101043Sdes 104101043Sdes#endif /* R600MACHINESCHEDULER_H_ */ 105101043Sdes