AMDGPUMCInstLower.cpp revision 263508
1//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 12// 13//===----------------------------------------------------------------------===// 14// 15 16#include "AMDGPUMCInstLower.h" 17#include "AMDGPUAsmPrinter.h" 18#include "InstPrinter/AMDGPUInstPrinter.h" 19#include "R600InstrInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/MachineInstr.h" 22#include "llvm/IR/Constants.h" 23#include "llvm/MC/MCCodeEmitter.h" 24#include "llvm/MC/MCExpr.h" 25#include "llvm/MC/MCInst.h" 26#include "llvm/MC/MCObjectStreamer.h" 27#include "llvm/MC/MCStreamer.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/Format.h" 30#include <algorithm> 31 32using namespace llvm; 33 34AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx): 35 Ctx(ctx) 36{ } 37 38void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 39 OutMI.setOpcode(MI->getOpcode()); 40 41 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) { 42 const MachineOperand &MO = MI->getOperand(i); 43 44 MCOperand MCOp; 45 switch (MO.getType()) { 46 default: 47 llvm_unreachable("unknown operand type"); 48 case MachineOperand::MO_FPImmediate: { 49 const APFloat &FloatValue = MO.getFPImm()->getValueAPF(); 50 assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle && 51 "Only floating point immediates are supported at the moment."); 52 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat()); 53 break; 54 } 55 case MachineOperand::MO_Immediate: 56 MCOp = MCOperand::CreateImm(MO.getImm()); 57 break; 58 case MachineOperand::MO_Register: 59 MCOp = MCOperand::CreateReg(MO.getReg()); 60 break; 61 case MachineOperand::MO_MachineBasicBlock: 62 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create( 63 MO.getMBB()->getSymbol(), Ctx)); 64 } 65 OutMI.addOperand(MCOp); 66 } 67} 68 69void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { 70 AMDGPUMCInstLower MCInstLowering(OutContext); 71 72 if (MI->isBundle()) { 73 const MachineBasicBlock *MBB = MI->getParent(); 74 MachineBasicBlock::const_instr_iterator I = MI; 75 ++I; 76 while (I != MBB->end() && I->isInsideBundle()) { 77 EmitInstruction(I); 78 ++I; 79 } 80 } else { 81 MCInst TmpInst; 82 MCInstLowering.lower(MI, TmpInst); 83 OutStreamer.EmitInstruction(TmpInst); 84 85 if (DisasmEnabled) { 86 // Disassemble instruction/operands to text. 87 DisasmLines.resize(DisasmLines.size() + 1); 88 std::string &DisasmLine = DisasmLines.back(); 89 raw_string_ostream DisasmStream(DisasmLine); 90 91 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(), 92 *TM.getRegisterInfo()); 93 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef()); 94 95 // Disassemble instruction/operands to hex representation. 96 SmallVector<MCFixup, 4> Fixups; 97 SmallVector<char, 16> CodeBytes; 98 raw_svector_ostream CodeStream(CodeBytes); 99 100 MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer; 101 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); 102 InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups); 103 CodeStream.flush(); 104 105 HexLines.resize(HexLines.size() + 1); 106 std::string &HexLine = HexLines.back(); 107 raw_string_ostream HexStream(HexLine); 108 109 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 110 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 111 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 112 } 113 114 DisasmStream.flush(); 115 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 116 } 117 } 118} 119