PPCFrameLowering.h revision 263508 
1//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef POWERPC_FRAMEINFO_H
14#define POWERPC_FRAMEINFO_H
15
16#include "PPC.h"
17#include "PPCSubtarget.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/Target/TargetFrameLowering.h"
20#include "llvm/Target/TargetMachine.h"
21
22namespace llvm {
23  class PPCSubtarget;
24
25class PPCFrameLowering: public TargetFrameLowering {
26  const PPCSubtarget &Subtarget;
27
28public:
29  PPCFrameLowering(const PPCSubtarget &sti)
30    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
31        (sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0),
32      Subtarget(sti) {
33  }
34
35  unsigned determineFrameLayout(MachineFunction &MF,
36                                bool UpdateMF = true,
37                                bool UseEstimate = false) const;
38
39  /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
40  /// the function.
41  void emitPrologue(MachineFunction &MF) const;
42  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
43
44  bool hasFP(const MachineFunction &MF) const;
45  bool needsFP(const MachineFunction &MF) const;
46  void replaceFPWithRealFP(MachineFunction &MF) const;
47
48  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
49                                            RegScavenger *RS = NULL) const;
50  void processFunctionBeforeFrameFinalized(MachineFunction &MF,
51                                       RegScavenger *RS = NULL) const;
52  void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
53
54  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
55                                 MachineBasicBlock::iterator MI,
56                                 const std::vector<CalleeSavedInfo> &CSI,
57                                 const TargetRegisterInfo *TRI) const;
58
59  void eliminateCallFramePseudoInstr(MachineFunction &MF,
60                                     MachineBasicBlock &MBB,
61                                     MachineBasicBlock::iterator I) const;
62
63  bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
64                                   MachineBasicBlock::iterator MI,
65                                   const std::vector<CalleeSavedInfo> &CSI,
66                                   const TargetRegisterInfo *TRI) const;
67
68  /// targetHandlesStackFrameRounding - Returns true if the target is
69  /// responsible for rounding up the stack frame (probably at emitPrologue
70  /// time).
71  bool targetHandlesStackFrameRounding() const { return true; }
72
73  /// getReturnSaveOffset - Return the previous frame offset to save the
74  /// return address.
75  static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
76    if (isDarwinABI)
77      return isPPC64 ? 16 : 8;
78    // SVR4 ABI:
79    return isPPC64 ? 16 : 4;
80  }
81
82  /// getFramePointerSaveOffset - Return the previous frame offset to save the
83  /// frame pointer.
84  static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
85    // For the Darwin ABI:
86    // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
87    // for saving the frame pointer (if needed.)  While the published ABI has
88    // not used this slot since at least MacOSX 10.2, there is older code
89    // around that does use it, and that needs to continue to work.
90    if (isDarwinABI)
91      return isPPC64 ? -8U : -4U;
92
93    // SVR4 ABI: First slot in the general register save area.
94    return isPPC64 ? -8U : -4U;
95  }
96
97  /// getBasePointerSaveOffset - Return the previous frame offset to save the
98  /// base pointer.
99  static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
100    if (isDarwinABI)
101      return isPPC64 ? -16U : -8U;
102
103    // SVR4 ABI: First slot in the general register save area.
104    return isPPC64 ? -16U : -8U;
105  }
106
107  /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
108  ///
109  static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
110    if (isDarwinABI || isPPC64)
111      return 6 * (isPPC64 ? 8 : 4);
112
113    // SVR4 ABI:
114    return 8;
115  }
116
117  /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
118  /// argument area.
119  static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
120    // For the Darwin ABI / 64-bit SVR4 ABI:
121    // The prolog code of the callee may store up to 8 GPR argument registers to
122    // the stack, allowing va_start to index over them in memory if its varargs.
123    // Because we cannot tell if this is needed on the caller side, we have to
124    // conservatively assume that it is needed.  As such, make sure we have at
125    // least enough stack space for the caller to store the 8 GPRs.
126    if (isDarwinABI || isPPC64)
127      return 8 * (isPPC64 ? 8 : 4);
128
129    // 32-bit SVR4 ABI:
130    // There is no default stack allocated for the 8 first GPR arguments.
131    return 0;
132  }
133
134  /// getMinCallFrameSize - Return the minimum size a call frame can be using
135  /// the PowerPC ABI.
136  static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
137    // The call frame needs to be at least big enough for linkage and 8 args.
138    return getLinkageSize(isPPC64, isDarwinABI) +
139           getMinCallArgumentsSize(isPPC64, isDarwinABI);
140  }
141
142  // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
143  const SpillSlot *
144  getCalleeSavedSpillSlots(unsigned &NumEntries) const {
145    if (Subtarget.isDarwinABI()) {
146      NumEntries = 1;
147      if (Subtarget.isPPC64()) {
148        static const SpillSlot darwin64Offsets = {PPC::X31, -8};
149        return &darwin64Offsets;
150      } else {
151        static const SpillSlot darwinOffsets = {PPC::R31, -4};
152        return &darwinOffsets;
153      }
154    }
155
156    // Early exit if not using the SVR4 ABI.
157    if (!Subtarget.isSVR4ABI()) {
158      NumEntries = 0;
159      return 0;
160    }
161
162    // Note that the offsets here overlap, but this is fixed up in
163    // processFunctionBeforeFrameFinalized.
164
165    static const SpillSlot Offsets[] = {
166      // Floating-point register save area offsets.
167      {PPC::F31, -8},
168      {PPC::F30, -16},
169      {PPC::F29, -24},
170      {PPC::F28, -32},
171      {PPC::F27, -40},
172      {PPC::F26, -48},
173      {PPC::F25, -56},
174      {PPC::F24, -64},
175      {PPC::F23, -72},
176      {PPC::F22, -80},
177      {PPC::F21, -88},
178      {PPC::F20, -96},
179      {PPC::F19, -104},
180      {PPC::F18, -112},
181      {PPC::F17, -120},
182      {PPC::F16, -128},
183      {PPC::F15, -136},
184      {PPC::F14, -144},
185
186      // General register save area offsets.
187      {PPC::R31, -4},
188      {PPC::R30, -8},
189      {PPC::R29, -12},
190      {PPC::R28, -16},
191      {PPC::R27, -20},
192      {PPC::R26, -24},
193      {PPC::R25, -28},
194      {PPC::R24, -32},
195      {PPC::R23, -36},
196      {PPC::R22, -40},
197      {PPC::R21, -44},
198      {PPC::R20, -48},
199      {PPC::R19, -52},
200      {PPC::R18, -56},
201      {PPC::R17, -60},
202      {PPC::R16, -64},
203      {PPC::R15, -68},
204      {PPC::R14, -72},
205
206      // CR save area offset.  We map each of the nonvolatile CR fields
207      // to the slot for CR2, which is the first of the nonvolatile CR
208      // fields to be assigned, so that we only allocate one save slot.
209      // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
210      {PPC::CR2, -4},
211
212      // VRSAVE save area offset.
213      {PPC::VRSAVE, -4},
214
215      // Vector register save area
216      {PPC::V31, -16},
217      {PPC::V30, -32},
218      {PPC::V29, -48},
219      {PPC::V28, -64},
220      {PPC::V27, -80},
221      {PPC::V26, -96},
222      {PPC::V25, -112},
223      {PPC::V24, -128},
224      {PPC::V23, -144},
225      {PPC::V22, -160},
226      {PPC::V21, -176},
227      {PPC::V20, -192}
228    };
229
230    static const SpillSlot Offsets64[] = {
231      // Floating-point register save area offsets.
232      {PPC::F31, -8},
233      {PPC::F30, -16},
234      {PPC::F29, -24},
235      {PPC::F28, -32},
236      {PPC::F27, -40},
237      {PPC::F26, -48},
238      {PPC::F25, -56},
239      {PPC::F24, -64},
240      {PPC::F23, -72},
241      {PPC::F22, -80},
242      {PPC::F21, -88},
243      {PPC::F20, -96},
244      {PPC::F19, -104},
245      {PPC::F18, -112},
246      {PPC::F17, -120},
247      {PPC::F16, -128},
248      {PPC::F15, -136},
249      {PPC::F14, -144},
250
251      // General register save area offsets.
252      {PPC::X31, -8},
253      {PPC::X30, -16},
254      {PPC::X29, -24},
255      {PPC::X28, -32},
256      {PPC::X27, -40},
257      {PPC::X26, -48},
258      {PPC::X25, -56},
259      {PPC::X24, -64},
260      {PPC::X23, -72},
261      {PPC::X22, -80},
262      {PPC::X21, -88},
263      {PPC::X20, -96},
264      {PPC::X19, -104},
265      {PPC::X18, -112},
266      {PPC::X17, -120},
267      {PPC::X16, -128},
268      {PPC::X15, -136},
269      {PPC::X14, -144},
270
271      // VRSAVE save area offset.
272      {PPC::VRSAVE, -4},
273
274      // Vector register save area
275      {PPC::V31, -16},
276      {PPC::V30, -32},
277      {PPC::V29, -48},
278      {PPC::V28, -64},
279      {PPC::V27, -80},
280      {PPC::V26, -96},
281      {PPC::V25, -112},
282      {PPC::V24, -128},
283      {PPC::V23, -144},
284      {PPC::V22, -160},
285      {PPC::V21, -176},
286      {PPC::V20, -192}
287    };
288
289    if (Subtarget.isPPC64()) {
290      NumEntries = array_lengthof(Offsets64);
291
292      return Offsets64;
293    } else {
294      NumEntries = array_lengthof(Offsets);
295
296      return Offsets;
297    }
298  }
299};
300
301} // End llvm namespace
302
303#endif
304