PPCFrameLowering.cpp revision 263508
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrBuilder.h" 16#include "PPCInstrInfo.h" 17#include "PPCMachineFunctionInfo.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/IR/Function.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29/// VRRegNo - Map from a numbered VR register to its enum value. 30/// 31static const uint16_t VRRegNo[] = { 32 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 33 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 34 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 35 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 36}; 37 38/// RemoveVRSaveCode - We have found that this function does not need any code 39/// to manipulate the VRSAVE register, even though it uses vector registers. 40/// This can happen when the only registers used are known to be live in or out 41/// of the function. Remove all of the VRSAVE related code from the function. 42/// FIXME: The removal of the code results in a compile failure at -O0 when the 43/// function contains a function call, as the GPR containing original VRSAVE 44/// contents is spilled and reloaded around the call. Without the prolog code, 45/// the spill instruction refers to an undefined register. This code needs 46/// to account for all uses of that GPR. 47static void RemoveVRSaveCode(MachineInstr *MI) { 48 MachineBasicBlock *Entry = MI->getParent(); 49 MachineFunction *MF = Entry->getParent(); 50 51 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 52 MachineBasicBlock::iterator MBBI = MI; 53 ++MBBI; 54 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 55 MBBI->eraseFromParent(); 56 57 bool RemovedAllMTVRSAVEs = true; 58 // See if we can find and remove the MTVRSAVE instruction from all of the 59 // epilog blocks. 60 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 61 // If last instruction is a return instruction, add an epilogue 62 if (!I->empty() && I->back().isReturn()) { 63 bool FoundIt = false; 64 for (MBBI = I->end(); MBBI != I->begin(); ) { 65 --MBBI; 66 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 67 MBBI->eraseFromParent(); // remove it. 68 FoundIt = true; 69 break; 70 } 71 } 72 RemovedAllMTVRSAVEs &= FoundIt; 73 } 74 } 75 76 // If we found and removed all MTVRSAVE instructions, remove the read of 77 // VRSAVE as well. 78 if (RemovedAllMTVRSAVEs) { 79 MBBI = MI; 80 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 81 --MBBI; 82 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 83 MBBI->eraseFromParent(); 84 } 85 86 // Finally, nuke the UPDATE_VRSAVE. 87 MI->eraseFromParent(); 88} 89 90// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 91// instruction selector. Based on the vector registers that have been used, 92// transform this into the appropriate ORI instruction. 93static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 94 MachineFunction *MF = MI->getParent()->getParent(); 95 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 96 DebugLoc dl = MI->getDebugLoc(); 97 98 unsigned UsedRegMask = 0; 99 for (unsigned i = 0; i != 32; ++i) 100 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 101 UsedRegMask |= 1 << (31-i); 102 103 // Live in and live out values already must be in the mask, so don't bother 104 // marking them. 105 for (MachineRegisterInfo::livein_iterator 106 I = MF->getRegInfo().livein_begin(), 107 E = MF->getRegInfo().livein_end(); I != E; ++I) { 108 unsigned RegNo = TRI->getEncodingValue(I->first); 109 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 110 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 111 } 112 113 // Live out registers appear as use operands on return instructions. 114 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 115 UsedRegMask != 0 && BI != BE; ++BI) { 116 const MachineBasicBlock &MBB = *BI; 117 if (MBB.empty() || !MBB.back().isReturn()) 118 continue; 119 const MachineInstr &Ret = MBB.back(); 120 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 121 const MachineOperand &MO = Ret.getOperand(I); 122 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 123 continue; 124 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 125 UsedRegMask &= ~(1 << (31-RegNo)); 126 } 127 } 128 129 // If no registers are used, turn this into a copy. 130 if (UsedRegMask == 0) { 131 // Remove all VRSAVE code. 132 RemoveVRSaveCode(MI); 133 return; 134 } 135 136 unsigned SrcReg = MI->getOperand(1).getReg(); 137 unsigned DstReg = MI->getOperand(0).getReg(); 138 139 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 140 if (DstReg != SrcReg) 141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 142 .addReg(SrcReg) 143 .addImm(UsedRegMask); 144 else 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 146 .addReg(SrcReg, RegState::Kill) 147 .addImm(UsedRegMask); 148 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 149 if (DstReg != SrcReg) 150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 151 .addReg(SrcReg) 152 .addImm(UsedRegMask >> 16); 153 else 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 155 .addReg(SrcReg, RegState::Kill) 156 .addImm(UsedRegMask >> 16); 157 } else { 158 if (DstReg != SrcReg) 159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 160 .addReg(SrcReg) 161 .addImm(UsedRegMask >> 16); 162 else 163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 164 .addReg(SrcReg, RegState::Kill) 165 .addImm(UsedRegMask >> 16); 166 167 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 168 .addReg(DstReg, RegState::Kill) 169 .addImm(UsedRegMask & 0xFFFF); 170 } 171 172 // Remove the old UPDATE_VRSAVE instruction. 173 MI->eraseFromParent(); 174} 175 176static bool spillsCR(const MachineFunction &MF) { 177 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 178 return FuncInfo->isCRSpilled(); 179} 180 181static bool spillsVRSAVE(const MachineFunction &MF) { 182 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 183 return FuncInfo->isVRSAVESpilled(); 184} 185 186static bool hasSpills(const MachineFunction &MF) { 187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 188 return FuncInfo->hasSpills(); 189} 190 191static bool hasNonRISpills(const MachineFunction &MF) { 192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 193 return FuncInfo->hasNonRISpills(); 194} 195 196/// determineFrameLayout - Determine the size of the frame and maximum call 197/// frame size. 198unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 199 bool UpdateMF, 200 bool UseEstimate) const { 201 MachineFrameInfo *MFI = MF.getFrameInfo(); 202 203 // Get the number of bytes to allocate from the FrameInfo 204 unsigned FrameSize = 205 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 206 207 // Get stack alignments. The frame must be aligned to the greatest of these: 208 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 209 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 210 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 211 212 const PPCRegisterInfo *RegInfo = 213 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 214 215 // If we are a leaf function, and use up to 224 bytes of stack space, 216 // don't have a frame pointer, calls, or dynamic alloca then we do not need 217 // to adjust the stack pointer (we fit in the Red Zone). 218 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 219 // stackless code if all local vars are reg-allocated. 220 bool DisableRedZone = MF.getFunction()->getAttributes(). 221 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 222 if (!DisableRedZone && 223 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 224 !Subtarget.isSVR4ABI() || // allocated locals. 225 FrameSize == 0) && 226 FrameSize <= 224 && // Fits in red zone. 227 !MFI->hasVarSizedObjects() && // No dynamic alloca. 228 !MFI->adjustsStack() && // No calls. 229 !RegInfo->hasBasePointer(MF)) { // No special alignment. 230 // No need for frame 231 if (UpdateMF) 232 MFI->setStackSize(0); 233 return 0; 234 } 235 236 // Get the maximum call frame size of all the calls. 237 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 238 239 // Maximum call frame needs to be at least big enough for linkage and 8 args. 240 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 241 Subtarget.isDarwinABI()); 242 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 243 244 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 245 // that allocations will be aligned. 246 if (MFI->hasVarSizedObjects()) 247 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 248 249 // Update maximum call frame size. 250 if (UpdateMF) 251 MFI->setMaxCallFrameSize(maxCallFrameSize); 252 253 // Include call frame size in total. 254 FrameSize += maxCallFrameSize; 255 256 // Make sure the frame is aligned. 257 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 258 259 // Update frame info. 260 if (UpdateMF) 261 MFI->setStackSize(FrameSize); 262 263 return FrameSize; 264} 265 266// hasFP - Return true if the specified function actually has a dedicated frame 267// pointer register. 268bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 269 const MachineFrameInfo *MFI = MF.getFrameInfo(); 270 // FIXME: This is pretty much broken by design: hasFP() might be called really 271 // early, before the stack layout was calculated and thus hasFP() might return 272 // true or false here depending on the time of call. 273 return (MFI->getStackSize()) && needsFP(MF); 274} 275 276// needsFP - Return true if the specified function should have a dedicated frame 277// pointer register. This is true if the function has variable sized allocas or 278// if frame pointer elimination is disabled. 279bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 280 const MachineFrameInfo *MFI = MF.getFrameInfo(); 281 282 // Naked functions have no stack frame pushed, so we don't have a frame 283 // pointer. 284 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 285 Attribute::Naked)) 286 return false; 287 288 return MF.getTarget().Options.DisableFramePointerElim(MF) || 289 MFI->hasVarSizedObjects() || 290 (MF.getTarget().Options.GuaranteedTailCallOpt && 291 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 292} 293 294void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 295 bool is31 = needsFP(MF); 296 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 297 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 298 299 const PPCRegisterInfo *RegInfo = 300 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 301 bool HasBP = RegInfo->hasBasePointer(MF); 302 unsigned BPReg = HasBP ? (unsigned) PPC::R30 : FPReg; 303 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 304 305 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 306 BI != BE; ++BI) 307 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 308 --MBBI; 309 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 310 MachineOperand &MO = MBBI->getOperand(I); 311 if (!MO.isReg()) 312 continue; 313 314 switch (MO.getReg()) { 315 case PPC::FP: 316 MO.setReg(FPReg); 317 break; 318 case PPC::FP8: 319 MO.setReg(FP8Reg); 320 break; 321 case PPC::BP: 322 MO.setReg(BPReg); 323 break; 324 case PPC::BP8: 325 MO.setReg(BP8Reg); 326 break; 327 328 } 329 } 330 } 331} 332 333void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 334 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 335 MachineBasicBlock::iterator MBBI = MBB.begin(); 336 MachineFrameInfo *MFI = MF.getFrameInfo(); 337 const PPCInstrInfo &TII = 338 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 339 const PPCRegisterInfo *RegInfo = 340 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 341 342 MachineModuleInfo &MMI = MF.getMMI(); 343 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 344 DebugLoc dl; 345 bool needsFrameMoves = MMI.hasDebugInfo() || 346 MF.getFunction()->needsUnwindTableEntry(); 347 348 // Get processor type. 349 bool isPPC64 = Subtarget.isPPC64(); 350 // Get the ABI. 351 bool isDarwinABI = Subtarget.isDarwinABI(); 352 bool isSVR4ABI = Subtarget.isSVR4ABI(); 353 assert((isDarwinABI || isSVR4ABI) && 354 "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 355 356 // Prepare for frame info. 357 MCSymbol *FrameLabel = 0; 358 359 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 360 // process it. 361 if (!isSVR4ABI) 362 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 363 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 364 HandleVRSaveUpdate(MBBI, TII); 365 break; 366 } 367 } 368 369 // Move MBBI back to the beginning of the function. 370 MBBI = MBB.begin(); 371 372 // Work out frame sizes. 373 unsigned FrameSize = determineFrameLayout(MF); 374 int NegFrameSize = -FrameSize; 375 if (!isInt<32>(NegFrameSize)) 376 llvm_unreachable("Unhandled stack size!"); 377 378 if (MFI->isFrameAddressTaken()) 379 replaceFPWithRealFP(MF); 380 381 // Check if the link register (LR) must be saved. 382 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 383 bool MustSaveLR = FI->mustSaveLR(); 384 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 385 // Do we have a frame pointer and/or base pointer for this function? 386 bool HasFP = hasFP(MF); 387 bool HasBP = RegInfo->hasBasePointer(MF); 388 389 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 390 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30; 391 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 392 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 393 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 394 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 395 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 396 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 397 : PPC::MFLR ); 398 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 399 : PPC::STW ); 400 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 401 : PPC::STWU ); 402 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 403 : PPC::STWUX); 404 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 405 : PPC::LIS ); 406 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 407 : PPC::ORI ); 408 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 409 : PPC::OR ); 410 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 411 : PPC::SUBFC); 412 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 413 : PPC::SUBFIC); 414 415 // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 416 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 417 // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 418 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 419 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 420 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 421 422 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 423 424 int FPOffset = 0; 425 if (HasFP) { 426 if (isSVR4ABI) { 427 MachineFrameInfo *FFI = MF.getFrameInfo(); 428 int FPIndex = FI->getFramePointerSaveIndex(); 429 assert(FPIndex && "No Frame Pointer Save Slot!"); 430 FPOffset = FFI->getObjectOffset(FPIndex); 431 } else { 432 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 433 } 434 } 435 436 int BPOffset = 0; 437 if (HasBP) { 438 if (isSVR4ABI) { 439 MachineFrameInfo *FFI = MF.getFrameInfo(); 440 int BPIndex = FI->getBasePointerSaveIndex(); 441 assert(BPIndex && "No Base Pointer Save Slot!"); 442 BPOffset = FFI->getObjectOffset(BPIndex); 443 } else { 444 BPOffset = 445 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI); 446 } 447 } 448 449 // Get stack alignments. 450 unsigned MaxAlign = MFI->getMaxAlignment(); 451 if (HasBP && MaxAlign > 1) 452 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 453 "Invalid alignment!"); 454 455 // Frames of 32KB & larger require special handling because they cannot be 456 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 457 bool isLargeFrame = !isInt<16>(NegFrameSize); 458 459 if (MustSaveLR) 460 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 461 462 assert((isPPC64 || MustSaveCRs.empty()) && 463 "Prologue CR saving supported only in 64-bit mode"); 464 465 if (!MustSaveCRs.empty()) { // will only occur for PPC64 466 MachineInstrBuilder MIB = 467 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); 468 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 469 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 470 } 471 472 if (HasFP) 473 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 474 BuildMI(MBB, MBBI, dl, StoreInst) 475 .addReg(FPReg) 476 .addImm(FPOffset) 477 .addReg(SPReg); 478 479 if (HasBP) 480 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 481 BuildMI(MBB, MBBI, dl, StoreInst) 482 .addReg(BPReg) 483 .addImm(BPOffset) 484 .addReg(SPReg); 485 486 if (MustSaveLR) 487 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 488 BuildMI(MBB, MBBI, dl, StoreInst) 489 .addReg(ScratchReg) 490 .addImm(LROffset) 491 .addReg(SPReg); 492 493 if (!MustSaveCRs.empty()) // will only occur for PPC64 494 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 495 .addReg(TempReg, getKillRegState(true)) 496 .addImm(8) 497 .addReg(SPReg); 498 499 // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 500 if (!FrameSize) return; 501 502 // Adjust stack pointer: r1 += NegFrameSize. 503 // If there is a preferred stack alignment, align R1 now 504 505 if (HasBP) { 506 // Save a copy of r1 as the base pointer. 507 BuildMI(MBB, MBBI, dl, OrInst, BPReg) 508 .addReg(SPReg) 509 .addReg(SPReg); 510 } 511 512 if (HasBP && MaxAlign > 1) { 513 if (isPPC64) 514 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 515 .addReg(SPReg) 516 .addImm(0) 517 .addImm(64 - Log2_32(MaxAlign)); 518 else // PPC32... 519 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 520 .addReg(SPReg) 521 .addImm(0) 522 .addImm(32 - Log2_32(MaxAlign)) 523 .addImm(31); 524 if (!isLargeFrame) { 525 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 526 .addReg(ScratchReg, RegState::Kill) 527 .addImm(NegFrameSize); 528 } else { 529 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 530 .addImm(NegFrameSize >> 16); 531 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 532 .addReg(TempReg, RegState::Kill) 533 .addImm(NegFrameSize & 0xFFFF); 534 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 535 .addReg(ScratchReg, RegState::Kill) 536 .addReg(TempReg, RegState::Kill); 537 } 538 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 539 .addReg(SPReg, RegState::Kill) 540 .addReg(SPReg) 541 .addReg(ScratchReg); 542 543 } else if (!isLargeFrame) { 544 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 545 .addReg(SPReg) 546 .addImm(NegFrameSize) 547 .addReg(SPReg); 548 549 } else { 550 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 551 .addImm(NegFrameSize >> 16); 552 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 553 .addReg(ScratchReg, RegState::Kill) 554 .addImm(NegFrameSize & 0xFFFF); 555 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 556 .addReg(SPReg, RegState::Kill) 557 .addReg(SPReg) 558 .addReg(ScratchReg); 559 } 560 561 // Add the "machine moves" for the instructions we generated above, but in 562 // reverse order. 563 if (needsFrameMoves) { 564 // Mark effective beginning of when frame pointer becomes valid. 565 FrameLabel = MMI.getContext().CreateTempSymbol(); 566 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 567 568 // Show update of SP. 569 assert(NegFrameSize); 570 MMI.addFrameInst( 571 MCCFIInstruction::createDefCfaOffset(FrameLabel, NegFrameSize)); 572 573 if (HasFP) { 574 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 575 MMI.addFrameInst( 576 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset)); 577 } 578 579 if (HasBP) { 580 unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 581 MMI.addFrameInst( 582 MCCFIInstruction::createOffset(FrameLabel, Reg, BPOffset)); 583 } 584 585 if (MustSaveLR) { 586 unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 587 MMI.addFrameInst( 588 MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset)); 589 } 590 } 591 592 MCSymbol *ReadyLabel = 0; 593 594 // If there is a frame pointer, copy R1 into R31 595 if (HasFP) { 596 BuildMI(MBB, MBBI, dl, OrInst, FPReg) 597 .addReg(SPReg) 598 .addReg(SPReg); 599 600 if (needsFrameMoves) { 601 ReadyLabel = MMI.getContext().CreateTempSymbol(); 602 603 // Mark effective beginning of when frame pointer is ready. 604 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 605 606 unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 607 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg)); 608 } 609 } 610 611 if (needsFrameMoves) { 612 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 613 614 // Add callee saved registers to move list. 615 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 616 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 617 unsigned Reg = CSI[I].getReg(); 618 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 619 620 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 621 // subregisters of CR2. We just need to emit a move of CR2. 622 if (PPC::CRBITRCRegClass.contains(Reg)) 623 continue; 624 625 // For SVR4, don't emit a move for the CR spill slot if we haven't 626 // spilled CRs. 627 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 628 && MustSaveCRs.empty()) 629 continue; 630 631 // For 64-bit SVR4 when we have spilled CRs, the spill location 632 // is SP+8, not a frame-relative slot. 633 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 634 MMI.addFrameInst(MCCFIInstruction::createOffset( 635 Label, MRI->getDwarfRegNum(PPC::CR2, true), 8)); 636 continue; 637 } 638 639 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 640 MMI.addFrameInst(MCCFIInstruction::createOffset( 641 Label, MRI->getDwarfRegNum(Reg, true), Offset)); 642 } 643 } 644} 645 646void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 647 MachineBasicBlock &MBB) const { 648 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 649 assert(MBBI != MBB.end() && "Returning block has no terminator"); 650 const PPCInstrInfo &TII = 651 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 652 const PPCRegisterInfo *RegInfo = 653 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 654 655 unsigned RetOpcode = MBBI->getOpcode(); 656 DebugLoc dl; 657 658 assert((RetOpcode == PPC::BLR || 659 RetOpcode == PPC::TCRETURNri || 660 RetOpcode == PPC::TCRETURNdi || 661 RetOpcode == PPC::TCRETURNai || 662 RetOpcode == PPC::TCRETURNri8 || 663 RetOpcode == PPC::TCRETURNdi8 || 664 RetOpcode == PPC::TCRETURNai8) && 665 "Can only insert epilog into returning blocks"); 666 667 // Get alignment info so we know how to restore the SP. 668 const MachineFrameInfo *MFI = MF.getFrameInfo(); 669 670 // Get the number of bytes allocated from the FrameInfo. 671 int FrameSize = MFI->getStackSize(); 672 673 // Get processor type. 674 bool isPPC64 = Subtarget.isPPC64(); 675 // Get the ABI. 676 bool isDarwinABI = Subtarget.isDarwinABI(); 677 bool isSVR4ABI = Subtarget.isSVR4ABI(); 678 679 // Check if the link register (LR) has been saved. 680 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 681 bool MustSaveLR = FI->mustSaveLR(); 682 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 683 // Do we have a frame pointer and/or base pointer for this function? 684 bool HasFP = hasFP(MF); 685 bool HasBP = RegInfo->hasBasePointer(MF); 686 687 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 688 unsigned BPReg = isPPC64 ? PPC::X30 : PPC::R30; 689 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 690 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0; 691 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 692 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 693 : PPC::MTLR ); 694 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 695 : PPC::LWZ ); 696 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 697 : PPC::LIS ); 698 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 699 : PPC::ORI ); 700 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 701 : PPC::ADDI ); 702 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 703 : PPC::ADD4 ); 704 705 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 706 707 int FPOffset = 0; 708 if (HasFP) { 709 if (isSVR4ABI) { 710 MachineFrameInfo *FFI = MF.getFrameInfo(); 711 int FPIndex = FI->getFramePointerSaveIndex(); 712 assert(FPIndex && "No Frame Pointer Save Slot!"); 713 FPOffset = FFI->getObjectOffset(FPIndex); 714 } else { 715 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 716 } 717 } 718 719 int BPOffset = 0; 720 if (HasBP) { 721 if (isSVR4ABI) { 722 MachineFrameInfo *FFI = MF.getFrameInfo(); 723 int BPIndex = FI->getBasePointerSaveIndex(); 724 assert(BPIndex && "No Base Pointer Save Slot!"); 725 BPOffset = FFI->getObjectOffset(BPIndex); 726 } else { 727 BPOffset = 728 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI); 729 } 730 } 731 732 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 733 RetOpcode == PPC::TCRETURNdi || 734 RetOpcode == PPC::TCRETURNai || 735 RetOpcode == PPC::TCRETURNri8 || 736 RetOpcode == PPC::TCRETURNdi8 || 737 RetOpcode == PPC::TCRETURNai8; 738 739 if (UsesTCRet) { 740 int MaxTCRetDelta = FI->getTailCallSPDelta(); 741 MachineOperand &StackAdjust = MBBI->getOperand(1); 742 assert(StackAdjust.isImm() && "Expecting immediate value."); 743 // Adjust stack pointer. 744 int StackAdj = StackAdjust.getImm(); 745 int Delta = StackAdj - MaxTCRetDelta; 746 assert((Delta >= 0) && "Delta must be positive"); 747 if (MaxTCRetDelta>0) 748 FrameSize += (StackAdj +Delta); 749 else 750 FrameSize += StackAdj; 751 } 752 753 // Frames of 32KB & larger require special handling because they cannot be 754 // indexed into with a simple LD/LWZ immediate offset operand. 755 bool isLargeFrame = !isInt<16>(FrameSize); 756 757 if (FrameSize) { 758 // In the prologue, the loaded (or persistent) stack pointer value is offset 759 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 760 761 // If this function contained a fastcc call and GuaranteedTailCallOpt is 762 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 763 // call which invalidates the stack pointer value in SP(0). So we use the 764 // value of R31 in this case. 765 if (FI->hasFastCall()) { 766 assert(HasFP && "Expecting a valid frame pointer."); 767 if (!isLargeFrame) { 768 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 769 .addReg(FPReg).addImm(FrameSize); 770 } else { 771 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 772 .addImm(FrameSize >> 16); 773 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 774 .addReg(ScratchReg, RegState::Kill) 775 .addImm(FrameSize & 0xFFFF); 776 BuildMI(MBB, MBBI, dl, AddInst) 777 .addReg(SPReg) 778 .addReg(FPReg) 779 .addReg(ScratchReg); 780 } 781 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 782 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 783 .addReg(SPReg) 784 .addImm(FrameSize); 785 } else { 786 BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 787 .addImm(0) 788 .addReg(SPReg); 789 } 790 791 } 792 793 if (MustSaveLR) 794 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 795 .addImm(LROffset) 796 .addReg(SPReg); 797 798 assert((isPPC64 || MustSaveCRs.empty()) && 799 "Epilogue CR restoring supported only in 64-bit mode"); 800 801 if (!MustSaveCRs.empty()) // will only occur for PPC64 802 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 803 .addImm(8) 804 .addReg(SPReg); 805 806 if (HasFP) 807 BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 808 .addImm(FPOffset) 809 .addReg(SPReg); 810 811 if (HasBP) 812 BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 813 .addImm(BPOffset) 814 .addReg(SPReg); 815 816 if (!MustSaveCRs.empty()) // will only occur for PPC64 817 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 818 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 819 .addReg(TempReg, getKillRegState(i == e-1)); 820 821 if (MustSaveLR) 822 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 823 824 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 825 // call optimization 826 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 827 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 828 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 829 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 830 831 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 832 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 833 .addReg(SPReg).addImm(CallerAllocatedAmt); 834 } else { 835 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 836 .addImm(CallerAllocatedAmt >> 16); 837 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 838 .addReg(ScratchReg, RegState::Kill) 839 .addImm(CallerAllocatedAmt & 0xFFFF); 840 BuildMI(MBB, MBBI, dl, AddInst) 841 .addReg(SPReg) 842 .addReg(FPReg) 843 .addReg(ScratchReg); 844 } 845 } else if (RetOpcode == PPC::TCRETURNdi) { 846 MBBI = MBB.getLastNonDebugInstr(); 847 MachineOperand &JumpTarget = MBBI->getOperand(0); 848 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 849 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 850 } else if (RetOpcode == PPC::TCRETURNri) { 851 MBBI = MBB.getLastNonDebugInstr(); 852 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 853 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 854 } else if (RetOpcode == PPC::TCRETURNai) { 855 MBBI = MBB.getLastNonDebugInstr(); 856 MachineOperand &JumpTarget = MBBI->getOperand(0); 857 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 858 } else if (RetOpcode == PPC::TCRETURNdi8) { 859 MBBI = MBB.getLastNonDebugInstr(); 860 MachineOperand &JumpTarget = MBBI->getOperand(0); 861 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 862 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 863 } else if (RetOpcode == PPC::TCRETURNri8) { 864 MBBI = MBB.getLastNonDebugInstr(); 865 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 866 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 867 } else if (RetOpcode == PPC::TCRETURNai8) { 868 MBBI = MBB.getLastNonDebugInstr(); 869 MachineOperand &JumpTarget = MBBI->getOperand(0); 870 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 871 } 872} 873 874/// MustSaveLR - Return true if this function requires that we save the LR 875/// register onto the stack in the prolog and restore it in the epilog of the 876/// function. 877static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 878 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 879 880 // We need a save/restore of LR if there is any def of LR (which is 881 // defined by calls, including the PIC setup sequence), or if there is 882 // some use of the LR stack slot (e.g. for builtin_return_address). 883 // (LR comes in 32 and 64 bit versions.) 884 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 885 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 886} 887 888void 889PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 890 RegScavenger *) const { 891 const PPCRegisterInfo *RegInfo = 892 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 893 894 // Save and clear the LR state. 895 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 896 unsigned LR = RegInfo->getRARegister(); 897 FI->setMustSaveLR(MustSaveLR(MF, LR)); 898 MachineRegisterInfo &MRI = MF.getRegInfo(); 899 MRI.setPhysRegUnused(LR); 900 901 // Save R31 if necessary 902 int FPSI = FI->getFramePointerSaveIndex(); 903 bool isPPC64 = Subtarget.isPPC64(); 904 bool isDarwinABI = Subtarget.isDarwinABI(); 905 MachineFrameInfo *MFI = MF.getFrameInfo(); 906 907 // If the frame pointer save index hasn't been defined yet. 908 if (!FPSI && needsFP(MF)) { 909 // Find out what the fix offset of the frame pointer save area. 910 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 911 // Allocate the frame index for frame pointer save area. 912 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 913 // Save the result. 914 FI->setFramePointerSaveIndex(FPSI); 915 } 916 917 int BPSI = FI->getBasePointerSaveIndex(); 918 if (!BPSI && RegInfo->hasBasePointer(MF)) { 919 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI); 920 // Allocate the frame index for the base pointer save area. 921 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 922 // Save the result. 923 FI->setBasePointerSaveIndex(BPSI); 924 } 925 926 // Reserve stack space to move the linkage area to in case of a tail call. 927 int TCSPDelta = 0; 928 if (MF.getTarget().Options.GuaranteedTailCallOpt && 929 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 930 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 931 } 932 933 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 934 // function uses CR 2, 3, or 4. 935 if (!isPPC64 && !isDarwinABI && 936 (MRI.isPhysRegUsed(PPC::CR2) || 937 MRI.isPhysRegUsed(PPC::CR3) || 938 MRI.isPhysRegUsed(PPC::CR4))) { 939 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 940 FI->setCRSpillFrameIndex(FrameIdx); 941 } 942} 943 944void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 945 RegScavenger *RS) const { 946 // Early exit if not using the SVR4 ABI. 947 if (!Subtarget.isSVR4ABI()) { 948 addScavengingSpillSlot(MF, RS); 949 return; 950 } 951 952 // Get callee saved register information. 953 MachineFrameInfo *FFI = MF.getFrameInfo(); 954 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 955 956 // Early exit if no callee saved registers are modified! 957 if (CSI.empty() && !needsFP(MF)) { 958 addScavengingSpillSlot(MF, RS); 959 return; 960 } 961 962 unsigned MinGPR = PPC::R31; 963 unsigned MinG8R = PPC::X31; 964 unsigned MinFPR = PPC::F31; 965 unsigned MinVR = PPC::V31; 966 967 bool HasGPSaveArea = false; 968 bool HasG8SaveArea = false; 969 bool HasFPSaveArea = false; 970 bool HasVRSAVESaveArea = false; 971 bool HasVRSaveArea = false; 972 973 SmallVector<CalleeSavedInfo, 18> GPRegs; 974 SmallVector<CalleeSavedInfo, 18> G8Regs; 975 SmallVector<CalleeSavedInfo, 18> FPRegs; 976 SmallVector<CalleeSavedInfo, 18> VRegs; 977 978 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 979 unsigned Reg = CSI[i].getReg(); 980 if (PPC::GPRCRegClass.contains(Reg)) { 981 HasGPSaveArea = true; 982 983 GPRegs.push_back(CSI[i]); 984 985 if (Reg < MinGPR) { 986 MinGPR = Reg; 987 } 988 } else if (PPC::G8RCRegClass.contains(Reg)) { 989 HasG8SaveArea = true; 990 991 G8Regs.push_back(CSI[i]); 992 993 if (Reg < MinG8R) { 994 MinG8R = Reg; 995 } 996 } else if (PPC::F8RCRegClass.contains(Reg)) { 997 HasFPSaveArea = true; 998 999 FPRegs.push_back(CSI[i]); 1000 1001 if (Reg < MinFPR) { 1002 MinFPR = Reg; 1003 } 1004 } else if (PPC::CRBITRCRegClass.contains(Reg) || 1005 PPC::CRRCRegClass.contains(Reg)) { 1006 ; // do nothing, as we already know whether CRs are spilled 1007 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 1008 HasVRSAVESaveArea = true; 1009 } else if (PPC::VRRCRegClass.contains(Reg)) { 1010 HasVRSaveArea = true; 1011 1012 VRegs.push_back(CSI[i]); 1013 1014 if (Reg < MinVR) { 1015 MinVR = Reg; 1016 } 1017 } else { 1018 llvm_unreachable("Unknown RegisterClass!"); 1019 } 1020 } 1021 1022 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1023 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 1024 1025 int64_t LowerBound = 0; 1026 1027 // Take into account stack space reserved for tail calls. 1028 int TCSPDelta = 0; 1029 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1030 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 1031 LowerBound = TCSPDelta; 1032 } 1033 1034 // The Floating-point register save area is right below the back chain word 1035 // of the previous stack frame. 1036 if (HasFPSaveArea) { 1037 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 1038 int FI = FPRegs[i].getFrameIdx(); 1039 1040 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1041 } 1042 1043 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1044 } 1045 1046 // Check whether the frame pointer register is allocated. If so, make sure it 1047 // is spilled to the correct offset. 1048 if (needsFP(MF)) { 1049 HasGPSaveArea = true; 1050 1051 int FI = PFI->getFramePointerSaveIndex(); 1052 assert(FI && "No Frame Pointer Save Slot!"); 1053 1054 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1055 } 1056 1057 const PPCRegisterInfo *RegInfo = 1058 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo()); 1059 if (RegInfo->hasBasePointer(MF)) { 1060 HasGPSaveArea = true; 1061 1062 int FI = PFI->getBasePointerSaveIndex(); 1063 assert(FI && "No Base Pointer Save Slot!"); 1064 1065 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1066 } 1067 1068 // General register save area starts right below the Floating-point 1069 // register save area. 1070 if (HasGPSaveArea || HasG8SaveArea) { 1071 // Move general register save area spill slots down, taking into account 1072 // the size of the Floating-point register save area. 1073 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1074 int FI = GPRegs[i].getFrameIdx(); 1075 1076 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1077 } 1078 1079 // Move general register save area spill slots down, taking into account 1080 // the size of the Floating-point register save area. 1081 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1082 int FI = G8Regs[i].getFrameIdx(); 1083 1084 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1085 } 1086 1087 unsigned MinReg = 1088 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1089 TRI->getEncodingValue(MinG8R)); 1090 1091 if (Subtarget.isPPC64()) { 1092 LowerBound -= (31 - MinReg + 1) * 8; 1093 } else { 1094 LowerBound -= (31 - MinReg + 1) * 4; 1095 } 1096 } 1097 1098 // For 32-bit only, the CR save area is below the general register 1099 // save area. For 64-bit SVR4, the CR save area is addressed relative 1100 // to the stack pointer and hence does not need an adjustment here. 1101 // Only CR2 (the first nonvolatile spilled) has an associated frame 1102 // index so that we have a single uniform save area. 1103 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1104 // Adjust the frame index of the CR spill slot. 1105 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1106 unsigned Reg = CSI[i].getReg(); 1107 1108 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1109 // Leave Darwin logic as-is. 1110 || (!Subtarget.isSVR4ABI() && 1111 (PPC::CRBITRCRegClass.contains(Reg) || 1112 PPC::CRRCRegClass.contains(Reg)))) { 1113 int FI = CSI[i].getFrameIdx(); 1114 1115 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1116 } 1117 } 1118 1119 LowerBound -= 4; // The CR save area is always 4 bytes long. 1120 } 1121 1122 if (HasVRSAVESaveArea) { 1123 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1124 // which have the VRSAVE register class? 1125 // Adjust the frame index of the VRSAVE spill slot. 1126 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1127 unsigned Reg = CSI[i].getReg(); 1128 1129 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1130 int FI = CSI[i].getFrameIdx(); 1131 1132 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1133 } 1134 } 1135 1136 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1137 } 1138 1139 if (HasVRSaveArea) { 1140 // Insert alignment padding, we need 16-byte alignment. 1141 LowerBound = (LowerBound - 15) & ~(15); 1142 1143 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1144 int FI = VRegs[i].getFrameIdx(); 1145 1146 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1147 } 1148 } 1149 1150 addScavengingSpillSlot(MF, RS); 1151} 1152 1153void 1154PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1155 RegScavenger *RS) const { 1156 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1157 // a large stack, which will require scavenging a register to materialize a 1158 // large offset. 1159 1160 // We need to have a scavenger spill slot for spills if the frame size is 1161 // large. In case there is no free register for large-offset addressing, 1162 // this slot is used for the necessary emergency spill. Also, we need the 1163 // slot for dynamic stack allocations. 1164 1165 // The scavenger might be invoked if the frame offset does not fit into 1166 // the 16-bit immediate. We don't know the complete frame size here 1167 // because we've not yet computed callee-saved register spills or the 1168 // needed alignment padding. 1169 unsigned StackSize = determineFrameLayout(MF, false, true); 1170 MachineFrameInfo *MFI = MF.getFrameInfo(); 1171 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1172 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1173 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1174 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1175 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1176 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1177 RC->getAlignment(), 1178 false)); 1179 1180 // Might we have over-aligned allocas? 1181 bool HasAlVars = MFI->hasVarSizedObjects() && 1182 MFI->getMaxAlignment() > getStackAlignment(); 1183 1184 // These kinds of spills might need two registers. 1185 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 1186 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1187 RC->getAlignment(), 1188 false)); 1189 1190 } 1191} 1192 1193bool 1194PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1195 MachineBasicBlock::iterator MI, 1196 const std::vector<CalleeSavedInfo> &CSI, 1197 const TargetRegisterInfo *TRI) const { 1198 1199 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1200 // Return false otherwise to maintain pre-existing behavior. 1201 if (!Subtarget.isSVR4ABI()) 1202 return false; 1203 1204 MachineFunction *MF = MBB.getParent(); 1205 const PPCInstrInfo &TII = 1206 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1207 DebugLoc DL; 1208 bool CRSpilled = false; 1209 MachineInstrBuilder CRMIB; 1210 1211 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1212 unsigned Reg = CSI[i].getReg(); 1213 // Only Darwin actually uses the VRSAVE register, but it can still appear 1214 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1215 // Darwin, ignore it. 1216 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1217 continue; 1218 1219 // CR2 through CR4 are the nonvolatile CR fields. 1220 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1221 1222 // Add the callee-saved register as live-in; it's killed at the spill. 1223 MBB.addLiveIn(Reg); 1224 1225 if (CRSpilled && IsCRField) { 1226 CRMIB.addReg(Reg, RegState::ImplicitKill); 1227 continue; 1228 } 1229 1230 // Insert the spill to the stack frame. 1231 if (IsCRField) { 1232 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1233 if (Subtarget.isPPC64()) { 1234 // The actual spill will happen at the start of the prologue. 1235 FuncInfo->addMustSaveCR(Reg); 1236 } else { 1237 CRSpilled = true; 1238 FuncInfo->setSpillsCR(); 1239 1240 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1241 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1242 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1243 .addReg(Reg, RegState::ImplicitKill); 1244 1245 MBB.insert(MI, CRMIB); 1246 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1247 .addReg(PPC::R12, 1248 getKillRegState(true)), 1249 CSI[i].getFrameIdx())); 1250 } 1251 } else { 1252 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1253 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1254 CSI[i].getFrameIdx(), RC, TRI); 1255 } 1256 } 1257 return true; 1258} 1259 1260static void 1261restoreCRs(bool isPPC64, bool is31, 1262 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1263 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1264 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1265 1266 MachineFunction *MF = MBB.getParent(); 1267 const PPCInstrInfo &TII = 1268 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1269 DebugLoc DL; 1270 unsigned RestoreOp, MoveReg; 1271 1272 if (isPPC64) 1273 // This is handled during epilogue generation. 1274 return; 1275 else { 1276 // 32-bit: FP-relative 1277 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1278 PPC::R12), 1279 CSI[CSIIndex].getFrameIdx())); 1280 RestoreOp = PPC::MTOCRF; 1281 MoveReg = PPC::R12; 1282 } 1283 1284 if (CR2Spilled) 1285 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1286 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1287 1288 if (CR3Spilled) 1289 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1290 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1291 1292 if (CR4Spilled) 1293 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1294 .addReg(MoveReg, getKillRegState(true))); 1295} 1296 1297void PPCFrameLowering:: 1298eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1299 MachineBasicBlock::iterator I) const { 1300 const PPCInstrInfo &TII = 1301 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1302 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1303 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1304 // Add (actually subtract) back the amount the callee popped on return. 1305 if (int CalleeAmt = I->getOperand(1).getImm()) { 1306 bool is64Bit = Subtarget.isPPC64(); 1307 CalleeAmt *= -1; 1308 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1309 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1310 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1311 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1312 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1313 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1314 MachineInstr *MI = I; 1315 DebugLoc dl = MI->getDebugLoc(); 1316 1317 if (isInt<16>(CalleeAmt)) { 1318 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1319 .addReg(StackReg, RegState::Kill) 1320 .addImm(CalleeAmt); 1321 } else { 1322 MachineBasicBlock::iterator MBBI = I; 1323 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1324 .addImm(CalleeAmt >> 16); 1325 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1326 .addReg(TmpReg, RegState::Kill) 1327 .addImm(CalleeAmt & 0xFFFF); 1328 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1329 .addReg(StackReg, RegState::Kill) 1330 .addReg(TmpReg); 1331 } 1332 } 1333 } 1334 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1335 MBB.erase(I); 1336} 1337 1338bool 1339PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1340 MachineBasicBlock::iterator MI, 1341 const std::vector<CalleeSavedInfo> &CSI, 1342 const TargetRegisterInfo *TRI) const { 1343 1344 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1345 // Return false otherwise to maintain pre-existing behavior. 1346 if (!Subtarget.isSVR4ABI()) 1347 return false; 1348 1349 MachineFunction *MF = MBB.getParent(); 1350 const PPCInstrInfo &TII = 1351 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1352 bool CR2Spilled = false; 1353 bool CR3Spilled = false; 1354 bool CR4Spilled = false; 1355 unsigned CSIIndex = 0; 1356 1357 // Initialize insertion-point logic; we will be restoring in reverse 1358 // order of spill. 1359 MachineBasicBlock::iterator I = MI, BeforeI = I; 1360 bool AtStart = I == MBB.begin(); 1361 1362 if (!AtStart) 1363 --BeforeI; 1364 1365 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1366 unsigned Reg = CSI[i].getReg(); 1367 1368 // Only Darwin actually uses the VRSAVE register, but it can still appear 1369 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 1370 // Darwin, ignore it. 1371 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 1372 continue; 1373 1374 if (Reg == PPC::CR2) { 1375 CR2Spilled = true; 1376 // The spill slot is associated only with CR2, which is the 1377 // first nonvolatile spilled. Save it here. 1378 CSIIndex = i; 1379 continue; 1380 } else if (Reg == PPC::CR3) { 1381 CR3Spilled = true; 1382 continue; 1383 } else if (Reg == PPC::CR4) { 1384 CR4Spilled = true; 1385 continue; 1386 } else { 1387 // When we first encounter a non-CR register after seeing at 1388 // least one CR register, restore all spilled CRs together. 1389 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1390 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1391 bool is31 = needsFP(*MF); 1392 restoreCRs(Subtarget.isPPC64(), is31, 1393 CR2Spilled, CR3Spilled, CR4Spilled, 1394 MBB, I, CSI, CSIIndex); 1395 CR2Spilled = CR3Spilled = CR4Spilled = false; 1396 } 1397 1398 // Default behavior for non-CR saves. 1399 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1400 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1401 RC, TRI); 1402 assert(I != MBB.begin() && 1403 "loadRegFromStackSlot didn't insert any code!"); 1404 } 1405 1406 // Insert in reverse order. 1407 if (AtStart) 1408 I = MBB.begin(); 1409 else { 1410 I = BeforeI; 1411 ++I; 1412 } 1413 } 1414 1415 // If we haven't yet spilled the CRs, do so now. 1416 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1417 bool is31 = needsFP(*MF); 1418 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1419 MBB, I, CSI, CSIIndex); 1420 } 1421 1422 return true; 1423} 1424 1425