PPCFastISel.cpp revision 263508
1//===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the PowerPC-specific support for the FastISel class. Some 11// of the target-specific code is generated by tablegen in the file 12// PPCGenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "ppcfastisel" 17#include "PPC.h" 18#include "PPCISelLowering.h" 19#include "PPCSubtarget.h" 20#include "PPCTargetMachine.h" 21#include "MCTargetDesc/PPCPredicates.h" 22#include "llvm/ADT/Optional.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/MachineConstantPool.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/IR/CallingConv.h" 31#include "llvm/IR/GlobalAlias.h" 32#include "llvm/IR/GlobalVariable.h" 33#include "llvm/IR/IntrinsicInst.h" 34#include "llvm/IR/Operator.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/GetElementPtrTypeIterator.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetMachine.h" 39 40//===----------------------------------------------------------------------===// 41// 42// TBD: 43// FastLowerArguments: Handle simple cases. 44// PPCMaterializeGV: Handle TLS. 45// SelectCall: Handle function pointers. 46// SelectCall: Handle multi-register return values. 47// SelectCall: Optimize away nops for local calls. 48// processCallArgs: Handle bit-converted arguments. 49// finishCall: Handle multi-register return values. 50// PPCComputeAddress: Handle parameter references as FrameIndex's. 51// PPCEmitCmp: Handle immediate as operand 1. 52// SelectCall: Handle small byval arguments. 53// SelectIntrinsicCall: Implement. 54// SelectSelect: Implement. 55// Consider factoring isTypeLegal into the base class. 56// Implement switches and jump tables. 57// 58//===----------------------------------------------------------------------===// 59using namespace llvm; 60 61namespace { 62 63typedef struct Address { 64 enum { 65 RegBase, 66 FrameIndexBase 67 } BaseType; 68 69 union { 70 unsigned Reg; 71 int FI; 72 } Base; 73 74 long Offset; 75 76 // Innocuous defaults for our address. 77 Address() 78 : BaseType(RegBase), Offset(0) { 79 Base.Reg = 0; 80 } 81} Address; 82 83class PPCFastISel : public FastISel { 84 85 const TargetMachine &TM; 86 const TargetInstrInfo &TII; 87 const TargetLowering &TLI; 88 const PPCSubtarget &PPCSubTarget; 89 LLVMContext *Context; 90 91 public: 92 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo, 93 const TargetLibraryInfo *LibInfo) 94 : FastISel(FuncInfo, LibInfo), 95 TM(FuncInfo.MF->getTarget()), 96 TII(*TM.getInstrInfo()), 97 TLI(*TM.getTargetLowering()), 98 PPCSubTarget( 99 *((static_cast<const PPCTargetMachine *>(&TM))->getSubtargetImpl()) 100 ), 101 Context(&FuncInfo.Fn->getContext()) { } 102 103 // Backend specific FastISel code. 104 private: 105 virtual bool TargetSelectInstruction(const Instruction *I); 106 virtual unsigned TargetMaterializeConstant(const Constant *C); 107 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); 108 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 109 const LoadInst *LI); 110 virtual bool FastLowerArguments(); 111 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm); 112 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 113 const TargetRegisterClass *RC, 114 unsigned Op0, bool Op0IsKill, 115 uint64_t Imm); 116 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode, 117 const TargetRegisterClass *RC, 118 unsigned Op0, bool Op0IsKill); 119 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 120 const TargetRegisterClass *RC, 121 unsigned Op0, bool Op0IsKill, 122 unsigned Op1, bool Op1IsKill); 123 124 // Instruction selection routines. 125 private: 126 bool SelectLoad(const Instruction *I); 127 bool SelectStore(const Instruction *I); 128 bool SelectBranch(const Instruction *I); 129 bool SelectIndirectBr(const Instruction *I); 130 bool SelectCmp(const Instruction *I); 131 bool SelectFPExt(const Instruction *I); 132 bool SelectFPTrunc(const Instruction *I); 133 bool SelectIToFP(const Instruction *I, bool IsSigned); 134 bool SelectFPToI(const Instruction *I, bool IsSigned); 135 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode); 136 bool SelectCall(const Instruction *I); 137 bool SelectRet(const Instruction *I); 138 bool SelectTrunc(const Instruction *I); 139 bool SelectIntExt(const Instruction *I); 140 141 // Utility routines. 142 private: 143 bool isTypeLegal(Type *Ty, MVT &VT); 144 bool isLoadTypeLegal(Type *Ty, MVT &VT); 145 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, 146 bool isZExt, unsigned DestReg); 147 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 148 const TargetRegisterClass *RC, bool IsZExt = true, 149 unsigned FP64LoadOpc = PPC::LFD); 150 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr); 151 bool PPCComputeAddress(const Value *Obj, Address &Addr); 152 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, 153 unsigned &IndexReg); 154 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 155 unsigned DestReg, bool IsZExt); 156 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT); 157 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT); 158 unsigned PPCMaterializeInt(const Constant *C, MVT VT); 159 unsigned PPCMaterialize32BitInt(int64_t Imm, 160 const TargetRegisterClass *RC); 161 unsigned PPCMaterialize64BitInt(int64_t Imm, 162 const TargetRegisterClass *RC); 163 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT, 164 unsigned SrcReg, bool IsSigned); 165 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned); 166 167 // Call handling routines. 168 private: 169 bool processCallArgs(SmallVectorImpl<Value*> &Args, 170 SmallVectorImpl<unsigned> &ArgRegs, 171 SmallVectorImpl<MVT> &ArgVTs, 172 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 173 SmallVectorImpl<unsigned> &RegArgs, 174 CallingConv::ID CC, 175 unsigned &NumBytes, 176 bool IsVarArg); 177 void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 178 const Instruction *I, CallingConv::ID CC, 179 unsigned &NumBytes, bool IsVarArg); 180 CCAssignFn *usePPC32CCs(unsigned Flag); 181 182 private: 183 #include "PPCGenFastISel.inc" 184 185}; 186 187} // end anonymous namespace 188 189#include "PPCGenCallingConv.inc" 190 191// Function whose sole purpose is to kill compiler warnings 192// stemming from unused functions included from PPCGenCallingConv.inc. 193CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) { 194 if (Flag == 1) 195 return CC_PPC32_SVR4; 196 else if (Flag == 2) 197 return CC_PPC32_SVR4_ByVal; 198 else if (Flag == 3) 199 return CC_PPC32_SVR4_VarArg; 200 else 201 return RetCC_PPC; 202} 203 204static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { 205 switch (Pred) { 206 // These are not representable with any single compare. 207 case CmpInst::FCMP_FALSE: 208 case CmpInst::FCMP_UEQ: 209 case CmpInst::FCMP_UGT: 210 case CmpInst::FCMP_UGE: 211 case CmpInst::FCMP_ULT: 212 case CmpInst::FCMP_ULE: 213 case CmpInst::FCMP_UNE: 214 case CmpInst::FCMP_TRUE: 215 default: 216 return Optional<PPC::Predicate>(); 217 218 case CmpInst::FCMP_OEQ: 219 case CmpInst::ICMP_EQ: 220 return PPC::PRED_EQ; 221 222 case CmpInst::FCMP_OGT: 223 case CmpInst::ICMP_UGT: 224 case CmpInst::ICMP_SGT: 225 return PPC::PRED_GT; 226 227 case CmpInst::FCMP_OGE: 228 case CmpInst::ICMP_UGE: 229 case CmpInst::ICMP_SGE: 230 return PPC::PRED_GE; 231 232 case CmpInst::FCMP_OLT: 233 case CmpInst::ICMP_ULT: 234 case CmpInst::ICMP_SLT: 235 return PPC::PRED_LT; 236 237 case CmpInst::FCMP_OLE: 238 case CmpInst::ICMP_ULE: 239 case CmpInst::ICMP_SLE: 240 return PPC::PRED_LE; 241 242 case CmpInst::FCMP_ONE: 243 case CmpInst::ICMP_NE: 244 return PPC::PRED_NE; 245 246 case CmpInst::FCMP_ORD: 247 return PPC::PRED_NU; 248 249 case CmpInst::FCMP_UNO: 250 return PPC::PRED_UN; 251 } 252} 253 254// Determine whether the type Ty is simple enough to be handled by 255// fast-isel, and return its equivalent machine type in VT. 256// FIXME: Copied directly from ARM -- factor into base class? 257bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { 258 EVT Evt = TLI.getValueType(Ty, true); 259 260 // Only handle simple types. 261 if (Evt == MVT::Other || !Evt.isSimple()) return false; 262 VT = Evt.getSimpleVT(); 263 264 // Handle all legal types, i.e. a register that will directly hold this 265 // value. 266 return TLI.isTypeLegal(VT); 267} 268 269// Determine whether the type Ty is simple enough to be handled by 270// fast-isel as a load target, and return its equivalent machine type in VT. 271bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { 272 if (isTypeLegal(Ty, VT)) return true; 273 274 // If this is a type than can be sign or zero-extended to a basic operation 275 // go ahead and accept it now. 276 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) { 277 return true; 278 } 279 280 return false; 281} 282 283// Given a value Obj, create an Address object Addr that represents its 284// address. Return false if we can't handle it. 285bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) { 286 const User *U = NULL; 287 unsigned Opcode = Instruction::UserOp1; 288 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 289 // Don't walk into other basic blocks unless the object is an alloca from 290 // another block, otherwise it may not have a virtual register assigned. 291 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || 292 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 293 Opcode = I->getOpcode(); 294 U = I; 295 } 296 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 297 Opcode = C->getOpcode(); 298 U = C; 299 } 300 301 switch (Opcode) { 302 default: 303 break; 304 case Instruction::BitCast: 305 // Look through bitcasts. 306 return PPCComputeAddress(U->getOperand(0), Addr); 307 case Instruction::IntToPtr: 308 // Look past no-op inttoptrs. 309 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 310 return PPCComputeAddress(U->getOperand(0), Addr); 311 break; 312 case Instruction::PtrToInt: 313 // Look past no-op ptrtoints. 314 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 315 return PPCComputeAddress(U->getOperand(0), Addr); 316 break; 317 case Instruction::GetElementPtr: { 318 Address SavedAddr = Addr; 319 long TmpOffset = Addr.Offset; 320 321 // Iterate through the GEP folding the constants into offsets where 322 // we can. 323 gep_type_iterator GTI = gep_type_begin(U); 324 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end(); 325 II != IE; ++II, ++GTI) { 326 const Value *Op = *II; 327 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 328 const StructLayout *SL = TD.getStructLayout(STy); 329 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 330 TmpOffset += SL->getElementOffset(Idx); 331 } else { 332 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 333 for (;;) { 334 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 335 // Constant-offset addressing. 336 TmpOffset += CI->getSExtValue() * S; 337 break; 338 } 339 if (canFoldAddIntoGEP(U, Op)) { 340 // A compatible add with a constant operand. Fold the constant. 341 ConstantInt *CI = 342 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 343 TmpOffset += CI->getSExtValue() * S; 344 // Iterate on the other operand. 345 Op = cast<AddOperator>(Op)->getOperand(0); 346 continue; 347 } 348 // Unsupported 349 goto unsupported_gep; 350 } 351 } 352 } 353 354 // Try to grab the base operand now. 355 Addr.Offset = TmpOffset; 356 if (PPCComputeAddress(U->getOperand(0), Addr)) return true; 357 358 // We failed, restore everything and try the other options. 359 Addr = SavedAddr; 360 361 unsupported_gep: 362 break; 363 } 364 case Instruction::Alloca: { 365 const AllocaInst *AI = cast<AllocaInst>(Obj); 366 DenseMap<const AllocaInst*, int>::iterator SI = 367 FuncInfo.StaticAllocaMap.find(AI); 368 if (SI != FuncInfo.StaticAllocaMap.end()) { 369 Addr.BaseType = Address::FrameIndexBase; 370 Addr.Base.FI = SI->second; 371 return true; 372 } 373 break; 374 } 375 } 376 377 // FIXME: References to parameters fall through to the behavior 378 // below. They should be able to reference a frame index since 379 // they are stored to the stack, so we can get "ld rx, offset(r1)" 380 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will 381 // just contain the parameter. Try to handle this with a FI. 382 383 // Try to get this in a register if nothing else has worked. 384 if (Addr.Base.Reg == 0) 385 Addr.Base.Reg = getRegForValue(Obj); 386 387 // Prevent assignment of base register to X0, which is inappropriate 388 // for loads and stores alike. 389 if (Addr.Base.Reg != 0) 390 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); 391 392 return Addr.Base.Reg != 0; 393} 394 395// Fix up some addresses that can't be used directly. For example, if 396// an offset won't fit in an instruction field, we may need to move it 397// into an index register. 398void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, 399 unsigned &IndexReg) { 400 401 // Check whether the offset fits in the instruction field. 402 if (!isInt<16>(Addr.Offset)) 403 UseOffset = false; 404 405 // If this is a stack pointer and the offset needs to be simplified then 406 // put the alloca address into a register, set the base type back to 407 // register and continue. This should almost never happen. 408 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) { 409 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8), 411 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); 412 Addr.Base.Reg = ResultReg; 413 Addr.BaseType = Address::RegBase; 414 } 415 416 if (!UseOffset) { 417 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context) 418 : Type::getInt64Ty(*Context)); 419 const ConstantInt *Offset = 420 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset)); 421 IndexReg = PPCMaterializeInt(Offset, MVT::i64); 422 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); 423 } 424} 425 426// Emit a load instruction if possible, returning true if we succeeded, 427// otherwise false. See commentary below for how the register class of 428// the load is determined. 429bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 430 const TargetRegisterClass *RC, 431 bool IsZExt, unsigned FP64LoadOpc) { 432 unsigned Opc; 433 bool UseOffset = true; 434 435 // If ResultReg is given, it determines the register class of the load. 436 // Otherwise, RC is the register class to use. If the result of the 437 // load isn't anticipated in this block, both may be zero, in which 438 // case we must make a conservative guess. In particular, don't assign 439 // R0 or X0 to the result register, as the result may be used in a load, 440 // store, add-immediate, or isel that won't permit this. (Though 441 // perhaps the spill and reload of live-exit values would handle this?) 442 const TargetRegisterClass *UseRC = 443 (ResultReg ? MRI.getRegClass(ResultReg) : 444 (RC ? RC : 445 (VT == MVT::f64 ? &PPC::F8RCRegClass : 446 (VT == MVT::f32 ? &PPC::F4RCRegClass : 447 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : 448 &PPC::GPRC_and_GPRC_NOR0RegClass))))); 449 450 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); 451 452 switch (VT.SimpleTy) { 453 default: // e.g., vector types not handled 454 return false; 455 case MVT::i8: 456 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; 457 break; 458 case MVT::i16: 459 Opc = (IsZExt ? 460 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) : 461 (Is32BitInt ? PPC::LHA : PPC::LHA8)); 462 break; 463 case MVT::i32: 464 Opc = (IsZExt ? 465 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) : 466 (Is32BitInt ? PPC::LWA_32 : PPC::LWA)); 467 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) 468 UseOffset = false; 469 break; 470 case MVT::i64: 471 Opc = PPC::LD; 472 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && 473 "64-bit load with 32-bit target??"); 474 UseOffset = ((Addr.Offset & 3) == 0); 475 break; 476 case MVT::f32: 477 Opc = PPC::LFS; 478 break; 479 case MVT::f64: 480 Opc = FP64LoadOpc; 481 break; 482 } 483 484 // If necessary, materialize the offset into a register and use 485 // the indexed form. Also handle stack pointers with special needs. 486 unsigned IndexReg = 0; 487 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); 488 if (ResultReg == 0) 489 ResultReg = createResultReg(UseRC); 490 491 // Note: If we still have a frame index here, we know the offset is 492 // in range, as otherwise PPCSimplifyAddress would have converted it 493 // into a RegBase. 494 if (Addr.BaseType == Address::FrameIndexBase) { 495 496 MachineMemOperand *MMO = 497 FuncInfo.MF->getMachineMemOperand( 498 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset), 499 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI), 500 MFI.getObjectAlignment(Addr.Base.FI)); 501 502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 503 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO); 504 505 // Base reg with offset in range. 506 } else if (UseOffset) { 507 508 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 509 .addImm(Addr.Offset).addReg(Addr.Base.Reg); 510 511 // Indexed form. 512 } else { 513 // Get the RR opcode corresponding to the RI one. FIXME: It would be 514 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it 515 // is hard to get at. 516 switch (Opc) { 517 default: llvm_unreachable("Unexpected opcode!"); 518 case PPC::LBZ: Opc = PPC::LBZX; break; 519 case PPC::LBZ8: Opc = PPC::LBZX8; break; 520 case PPC::LHZ: Opc = PPC::LHZX; break; 521 case PPC::LHZ8: Opc = PPC::LHZX8; break; 522 case PPC::LHA: Opc = PPC::LHAX; break; 523 case PPC::LHA8: Opc = PPC::LHAX8; break; 524 case PPC::LWZ: Opc = PPC::LWZX; break; 525 case PPC::LWZ8: Opc = PPC::LWZX8; break; 526 case PPC::LWA: Opc = PPC::LWAX; break; 527 case PPC::LWA_32: Opc = PPC::LWAX_32; break; 528 case PPC::LD: Opc = PPC::LDX; break; 529 case PPC::LFS: Opc = PPC::LFSX; break; 530 case PPC::LFD: Opc = PPC::LFDX; break; 531 } 532 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 533 .addReg(Addr.Base.Reg).addReg(IndexReg); 534 } 535 536 return true; 537} 538 539// Attempt to fast-select a load instruction. 540bool PPCFastISel::SelectLoad(const Instruction *I) { 541 // FIXME: No atomic loads are supported. 542 if (cast<LoadInst>(I)->isAtomic()) 543 return false; 544 545 // Verify we have a legal type before going any further. 546 MVT VT; 547 if (!isLoadTypeLegal(I->getType(), VT)) 548 return false; 549 550 // See if we can handle this address. 551 Address Addr; 552 if (!PPCComputeAddress(I->getOperand(0), Addr)) 553 return false; 554 555 // Look at the currently assigned register for this instruction 556 // to determine the required register class. This is necessary 557 // to constrain RA from using R0/X0 when this is not legal. 558 unsigned AssignedReg = FuncInfo.ValueMap[I]; 559 const TargetRegisterClass *RC = 560 AssignedReg ? MRI.getRegClass(AssignedReg) : 0; 561 562 unsigned ResultReg = 0; 563 if (!PPCEmitLoad(VT, ResultReg, Addr, RC)) 564 return false; 565 UpdateValueMap(I, ResultReg); 566 return true; 567} 568 569// Emit a store instruction to store SrcReg at Addr. 570bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { 571 assert(SrcReg && "Nothing to store!"); 572 unsigned Opc; 573 bool UseOffset = true; 574 575 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); 576 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); 577 578 switch (VT.SimpleTy) { 579 default: // e.g., vector types not handled 580 return false; 581 case MVT::i8: 582 Opc = Is32BitInt ? PPC::STB : PPC::STB8; 583 break; 584 case MVT::i16: 585 Opc = Is32BitInt ? PPC::STH : PPC::STH8; 586 break; 587 case MVT::i32: 588 assert(Is32BitInt && "Not GPRC for i32??"); 589 Opc = PPC::STW; 590 break; 591 case MVT::i64: 592 Opc = PPC::STD; 593 UseOffset = ((Addr.Offset & 3) == 0); 594 break; 595 case MVT::f32: 596 Opc = PPC::STFS; 597 break; 598 case MVT::f64: 599 Opc = PPC::STFD; 600 break; 601 } 602 603 // If necessary, materialize the offset into a register and use 604 // the indexed form. Also handle stack pointers with special needs. 605 unsigned IndexReg = 0; 606 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); 607 608 // Note: If we still have a frame index here, we know the offset is 609 // in range, as otherwise PPCSimplifyAddress would have converted it 610 // into a RegBase. 611 if (Addr.BaseType == Address::FrameIndexBase) { 612 MachineMemOperand *MMO = 613 FuncInfo.MF->getMachineMemOperand( 614 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset), 615 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI), 616 MFI.getObjectAlignment(Addr.Base.FI)); 617 618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)).addReg(SrcReg) 619 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO); 620 621 // Base reg with offset in range. 622 } else if (UseOffset) 623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)) 624 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg); 625 626 // Indexed form. 627 else { 628 // Get the RR opcode corresponding to the RI one. FIXME: It would be 629 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it 630 // is hard to get at. 631 switch (Opc) { 632 default: llvm_unreachable("Unexpected opcode!"); 633 case PPC::STB: Opc = PPC::STBX; break; 634 case PPC::STH : Opc = PPC::STHX; break; 635 case PPC::STW : Opc = PPC::STWX; break; 636 case PPC::STB8: Opc = PPC::STBX8; break; 637 case PPC::STH8: Opc = PPC::STHX8; break; 638 case PPC::STW8: Opc = PPC::STWX8; break; 639 case PPC::STD: Opc = PPC::STDX; break; 640 case PPC::STFS: Opc = PPC::STFSX; break; 641 case PPC::STFD: Opc = PPC::STFDX; break; 642 } 643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)) 644 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg); 645 } 646 647 return true; 648} 649 650// Attempt to fast-select a store instruction. 651bool PPCFastISel::SelectStore(const Instruction *I) { 652 Value *Op0 = I->getOperand(0); 653 unsigned SrcReg = 0; 654 655 // FIXME: No atomics loads are supported. 656 if (cast<StoreInst>(I)->isAtomic()) 657 return false; 658 659 // Verify we have a legal type before going any further. 660 MVT VT; 661 if (!isLoadTypeLegal(Op0->getType(), VT)) 662 return false; 663 664 // Get the value to be stored into a register. 665 SrcReg = getRegForValue(Op0); 666 if (SrcReg == 0) 667 return false; 668 669 // See if we can handle this address. 670 Address Addr; 671 if (!PPCComputeAddress(I->getOperand(1), Addr)) 672 return false; 673 674 if (!PPCEmitStore(VT, SrcReg, Addr)) 675 return false; 676 677 return true; 678} 679 680// Attempt to fast-select a branch instruction. 681bool PPCFastISel::SelectBranch(const Instruction *I) { 682 const BranchInst *BI = cast<BranchInst>(I); 683 MachineBasicBlock *BrBB = FuncInfo.MBB; 684 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 685 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 686 687 // For now, just try the simplest case where it's fed by a compare. 688 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 689 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate()); 690 if (!OptPPCPred) 691 return false; 692 693 PPC::Predicate PPCPred = OptPPCPred.getValue(); 694 695 // Take advantage of fall-through opportunities. 696 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 697 std::swap(TBB, FBB); 698 PPCPred = PPC::InvertPredicate(PPCPred); 699 } 700 701 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); 702 703 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(), 704 CondReg)) 705 return false; 706 707 BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC)) 708 .addImm(PPCPred).addReg(CondReg).addMBB(TBB); 709 FastEmitBranch(FBB, DL); 710 FuncInfo.MBB->addSuccessor(TBB); 711 return true; 712 713 } else if (const ConstantInt *CI = 714 dyn_cast<ConstantInt>(BI->getCondition())) { 715 uint64_t Imm = CI->getZExtValue(); 716 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; 717 FastEmitBranch(Target, DL); 718 return true; 719 } 720 721 // FIXME: ARM looks for a case where the block containing the compare 722 // has been split from the block containing the branch. If this happens, 723 // there is a vreg available containing the result of the compare. I'm 724 // not sure we can do much, as we've lost the predicate information with 725 // the compare instruction -- we have a 4-bit CR but don't know which bit 726 // to test here. 727 return false; 728} 729 730// Attempt to emit a compare of the two source values. Signed and unsigned 731// comparisons are supported. Return false if we can't handle it. 732bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2, 733 bool IsZExt, unsigned DestReg) { 734 Type *Ty = SrcValue1->getType(); 735 EVT SrcEVT = TLI.getValueType(Ty, true); 736 if (!SrcEVT.isSimple()) 737 return false; 738 MVT SrcVT = SrcEVT.getSimpleVT(); 739 740 // See if operand 2 is an immediate encodeable in the compare. 741 // FIXME: Operands are not in canonical order at -O0, so an immediate 742 // operand in position 1 is a lost opportunity for now. We are 743 // similar to ARM in this regard. 744 long Imm = 0; 745 bool UseImm = false; 746 747 // Only 16-bit integer constants can be represented in compares for 748 // PowerPC. Others will be materialized into a register. 749 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) { 750 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || 751 SrcVT == MVT::i8 || SrcVT == MVT::i1) { 752 const APInt &CIVal = ConstInt->getValue(); 753 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue(); 754 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) 755 UseImm = true; 756 } 757 } 758 759 unsigned CmpOpc; 760 bool NeedsExt = false; 761 switch (SrcVT.SimpleTy) { 762 default: return false; 763 case MVT::f32: 764 CmpOpc = PPC::FCMPUS; 765 break; 766 case MVT::f64: 767 CmpOpc = PPC::FCMPUD; 768 break; 769 case MVT::i1: 770 case MVT::i8: 771 case MVT::i16: 772 NeedsExt = true; 773 // Intentional fall-through. 774 case MVT::i32: 775 if (!UseImm) 776 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; 777 else 778 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; 779 break; 780 case MVT::i64: 781 if (!UseImm) 782 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; 783 else 784 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; 785 break; 786 } 787 788 unsigned SrcReg1 = getRegForValue(SrcValue1); 789 if (SrcReg1 == 0) 790 return false; 791 792 unsigned SrcReg2 = 0; 793 if (!UseImm) { 794 SrcReg2 = getRegForValue(SrcValue2); 795 if (SrcReg2 == 0) 796 return false; 797 } 798 799 if (NeedsExt) { 800 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); 801 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) 802 return false; 803 SrcReg1 = ExtReg; 804 805 if (!UseImm) { 806 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); 807 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 808 return false; 809 SrcReg2 = ExtReg; 810 } 811 } 812 813 if (!UseImm) 814 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg) 815 .addReg(SrcReg1).addReg(SrcReg2); 816 else 817 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg) 818 .addReg(SrcReg1).addImm(Imm); 819 820 return true; 821} 822 823// Attempt to fast-select a floating-point extend instruction. 824bool PPCFastISel::SelectFPExt(const Instruction *I) { 825 Value *Src = I->getOperand(0); 826 EVT SrcVT = TLI.getValueType(Src->getType(), true); 827 EVT DestVT = TLI.getValueType(I->getType(), true); 828 829 if (SrcVT != MVT::f32 || DestVT != MVT::f64) 830 return false; 831 832 unsigned SrcReg = getRegForValue(Src); 833 if (!SrcReg) 834 return false; 835 836 // No code is generated for a FP extend. 837 UpdateValueMap(I, SrcReg); 838 return true; 839} 840 841// Attempt to fast-select a floating-point truncate instruction. 842bool PPCFastISel::SelectFPTrunc(const Instruction *I) { 843 Value *Src = I->getOperand(0); 844 EVT SrcVT = TLI.getValueType(Src->getType(), true); 845 EVT DestVT = TLI.getValueType(I->getType(), true); 846 847 if (SrcVT != MVT::f64 || DestVT != MVT::f32) 848 return false; 849 850 unsigned SrcReg = getRegForValue(Src); 851 if (!SrcReg) 852 return false; 853 854 // Round the result to single precision. 855 unsigned DestReg = createResultReg(&PPC::F4RCRegClass); 856 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP), DestReg) 857 .addReg(SrcReg); 858 859 UpdateValueMap(I, DestReg); 860 return true; 861} 862 863// Move an i32 or i64 value in a GPR to an f64 value in an FPR. 864// FIXME: When direct register moves are implemented (see PowerISA 2.08), 865// those should be used instead of moving via a stack slot when the 866// subtarget permits. 867// FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte 868// stack slot and 4-byte store/load sequence. Or just sext the 4-byte 869// case to 8 bytes which produces tighter code but wastes stack space. 870unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg, 871 bool IsSigned) { 872 873 // If necessary, extend 32-bit int to 64-bit. 874 if (SrcVT == MVT::i32) { 875 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); 876 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) 877 return 0; 878 SrcReg = TmpReg; 879 } 880 881 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary. 882 Address Addr; 883 Addr.BaseType = Address::FrameIndexBase; 884 Addr.Base.FI = MFI.CreateStackObject(8, 8, false); 885 886 // Store the value from the GPR. 887 if (!PPCEmitStore(MVT::i64, SrcReg, Addr)) 888 return 0; 889 890 // Load the integer value into an FPR. The kind of load used depends 891 // on a number of conditions. 892 unsigned LoadOpc = PPC::LFD; 893 894 if (SrcVT == MVT::i32) { 895 Addr.Offset = 4; 896 if (!IsSigned) 897 LoadOpc = PPC::LFIWZX; 898 else if (PPCSubTarget.hasLFIWAX()) 899 LoadOpc = PPC::LFIWAX; 900 } 901 902 const TargetRegisterClass *RC = &PPC::F8RCRegClass; 903 unsigned ResultReg = 0; 904 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc)) 905 return 0; 906 907 return ResultReg; 908} 909 910// Attempt to fast-select an integer-to-floating-point conversion. 911bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) { 912 MVT DstVT; 913 Type *DstTy = I->getType(); 914 if (!isTypeLegal(DstTy, DstVT)) 915 return false; 916 917 if (DstVT != MVT::f32 && DstVT != MVT::f64) 918 return false; 919 920 Value *Src = I->getOperand(0); 921 EVT SrcEVT = TLI.getValueType(Src->getType(), true); 922 if (!SrcEVT.isSimple()) 923 return false; 924 925 MVT SrcVT = SrcEVT.getSimpleVT(); 926 927 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && 928 SrcVT != MVT::i32 && SrcVT != MVT::i64) 929 return false; 930 931 unsigned SrcReg = getRegForValue(Src); 932 if (SrcReg == 0) 933 return false; 934 935 // We can only lower an unsigned convert if we have the newer 936 // floating-point conversion operations. 937 if (!IsSigned && !PPCSubTarget.hasFPCVT()) 938 return false; 939 940 // FIXME: For now we require the newer floating-point conversion operations 941 // (which are present only on P7 and A2 server models) when converting 942 // to single-precision float. Otherwise we have to generate a lot of 943 // fiddly code to avoid double rounding. If necessary, the fiddly code 944 // can be found in PPCTargetLowering::LowerINT_TO_FP(). 945 if (DstVT == MVT::f32 && !PPCSubTarget.hasFPCVT()) 946 return false; 947 948 // Extend the input if necessary. 949 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) { 950 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); 951 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) 952 return false; 953 SrcVT = MVT::i64; 954 SrcReg = TmpReg; 955 } 956 957 // Move the integer value to an FPR. 958 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned); 959 if (FPReg == 0) 960 return false; 961 962 // Determine the opcode for the conversion. 963 const TargetRegisterClass *RC = &PPC::F8RCRegClass; 964 unsigned DestReg = createResultReg(RC); 965 unsigned Opc; 966 967 if (DstVT == MVT::f32) 968 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS; 969 else 970 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU; 971 972 // Generate the convert. 973 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 974 .addReg(FPReg); 975 976 UpdateValueMap(I, DestReg); 977 return true; 978} 979 980// Move the floating-point value in SrcReg into an integer destination 981// register, and return the register (or zero if we can't handle it). 982// FIXME: When direct register moves are implemented (see PowerISA 2.08), 983// those should be used instead of moving via a stack slot when the 984// subtarget permits. 985unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, 986 unsigned SrcReg, bool IsSigned) { 987 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary. 988 // Note that if have STFIWX available, we could use a 4-byte stack 989 // slot for i32, but this being fast-isel we'll just go with the 990 // easiest code gen possible. 991 Address Addr; 992 Addr.BaseType = Address::FrameIndexBase; 993 Addr.Base.FI = MFI.CreateStackObject(8, 8, false); 994 995 // Store the value from the FPR. 996 if (!PPCEmitStore(MVT::f64, SrcReg, Addr)) 997 return 0; 998 999 // Reload it into a GPR. If we want an i32, modify the address 1000 // to have a 4-byte offset so we load from the right place. 1001 if (VT == MVT::i32) 1002 Addr.Offset = 4; 1003 1004 // Look at the currently assigned register for this instruction 1005 // to determine the required register class. 1006 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1007 const TargetRegisterClass *RC = 1008 AssignedReg ? MRI.getRegClass(AssignedReg) : 0; 1009 1010 unsigned ResultReg = 0; 1011 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned)) 1012 return 0; 1013 1014 return ResultReg; 1015} 1016 1017// Attempt to fast-select a floating-point-to-integer conversion. 1018bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) { 1019 MVT DstVT, SrcVT; 1020 Type *DstTy = I->getType(); 1021 if (!isTypeLegal(DstTy, DstVT)) 1022 return false; 1023 1024 if (DstVT != MVT::i32 && DstVT != MVT::i64) 1025 return false; 1026 1027 Value *Src = I->getOperand(0); 1028 Type *SrcTy = Src->getType(); 1029 if (!isTypeLegal(SrcTy, SrcVT)) 1030 return false; 1031 1032 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) 1033 return false; 1034 1035 unsigned SrcReg = getRegForValue(Src); 1036 if (SrcReg == 0) 1037 return false; 1038 1039 // Convert f32 to f64 if necessary. This is just a meaningless copy 1040 // to get the register class right. COPY_TO_REGCLASS is needed since 1041 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream. 1042 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); 1043 if (InRC == &PPC::F4RCRegClass) { 1044 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); 1045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1046 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg) 1047 .addReg(SrcReg).addImm(PPC::F8RCRegClassID); 1048 SrcReg = TmpReg; 1049 } 1050 1051 // Determine the opcode for the conversion, which takes place 1052 // entirely within FPRs. 1053 unsigned DestReg = createResultReg(&PPC::F8RCRegClass); 1054 unsigned Opc; 1055 1056 if (DstVT == MVT::i32) 1057 if (IsSigned) 1058 Opc = PPC::FCTIWZ; 1059 else 1060 Opc = PPCSubTarget.hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ; 1061 else 1062 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ; 1063 1064 // Generate the convert. 1065 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 1066 .addReg(SrcReg); 1067 1068 // Now move the integer value from a float register to an integer register. 1069 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned); 1070 if (IntReg == 0) 1071 return false; 1072 1073 UpdateValueMap(I, IntReg); 1074 return true; 1075} 1076 1077// Attempt to fast-select a binary integer operation that isn't already 1078// handled automatically. 1079bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { 1080 EVT DestVT = TLI.getValueType(I->getType(), true); 1081 1082 // We can get here in the case when we have a binary operation on a non-legal 1083 // type and the target independent selector doesn't know how to handle it. 1084 if (DestVT != MVT::i16 && DestVT != MVT::i8) 1085 return false; 1086 1087 // Look at the currently assigned register for this instruction 1088 // to determine the required register class. If there is no register, 1089 // make a conservative choice (don't assign R0). 1090 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1091 const TargetRegisterClass *RC = 1092 (AssignedReg ? MRI.getRegClass(AssignedReg) : 1093 &PPC::GPRC_and_GPRC_NOR0RegClass); 1094 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); 1095 1096 unsigned Opc; 1097 switch (ISDOpcode) { 1098 default: return false; 1099 case ISD::ADD: 1100 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8; 1101 break; 1102 case ISD::OR: 1103 Opc = IsGPRC ? PPC::OR : PPC::OR8; 1104 break; 1105 case ISD::SUB: 1106 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8; 1107 break; 1108 } 1109 1110 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); 1111 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); 1112 if (SrcReg1 == 0) return false; 1113 1114 // Handle case of small immediate operand. 1115 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) { 1116 const APInt &CIVal = ConstInt->getValue(); 1117 int Imm = (int)CIVal.getSExtValue(); 1118 bool UseImm = true; 1119 if (isInt<16>(Imm)) { 1120 switch (Opc) { 1121 default: 1122 llvm_unreachable("Missing case!"); 1123 case PPC::ADD4: 1124 Opc = PPC::ADDI; 1125 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1126 break; 1127 case PPC::ADD8: 1128 Opc = PPC::ADDI8; 1129 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1130 break; 1131 case PPC::OR: 1132 Opc = PPC::ORI; 1133 break; 1134 case PPC::OR8: 1135 Opc = PPC::ORI8; 1136 break; 1137 case PPC::SUBF: 1138 if (Imm == -32768) 1139 UseImm = false; 1140 else { 1141 Opc = PPC::ADDI; 1142 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); 1143 Imm = -Imm; 1144 } 1145 break; 1146 case PPC::SUBF8: 1147 if (Imm == -32768) 1148 UseImm = false; 1149 else { 1150 Opc = PPC::ADDI8; 1151 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); 1152 Imm = -Imm; 1153 } 1154 break; 1155 } 1156 1157 if (UseImm) { 1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 1159 .addReg(SrcReg1).addImm(Imm); 1160 UpdateValueMap(I, ResultReg); 1161 return true; 1162 } 1163 } 1164 } 1165 1166 // Reg-reg case. 1167 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); 1168 if (SrcReg2 == 0) return false; 1169 1170 // Reverse operands for subtract-from. 1171 if (ISDOpcode == ISD::SUB) 1172 std::swap(SrcReg1, SrcReg2); 1173 1174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) 1175 .addReg(SrcReg1).addReg(SrcReg2); 1176 UpdateValueMap(I, ResultReg); 1177 return true; 1178} 1179 1180// Handle arguments to a call that we're attempting to fast-select. 1181// Return false if the arguments are too complex for us at the moment. 1182bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args, 1183 SmallVectorImpl<unsigned> &ArgRegs, 1184 SmallVectorImpl<MVT> &ArgVTs, 1185 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1186 SmallVectorImpl<unsigned> &RegArgs, 1187 CallingConv::ID CC, 1188 unsigned &NumBytes, 1189 bool IsVarArg) { 1190 SmallVector<CCValAssign, 16> ArgLocs; 1191 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context); 1192 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS); 1193 1194 // Bail out if we can't handle any of the arguments. 1195 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1196 CCValAssign &VA = ArgLocs[I]; 1197 MVT ArgVT = ArgVTs[VA.getValNo()]; 1198 1199 // Skip vector arguments for now, as well as long double and 1200 // uint128_t, and anything that isn't passed in a register. 1201 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || 1202 !VA.isRegLoc() || VA.needsCustom()) 1203 return false; 1204 1205 // Skip bit-converted arguments for now. 1206 if (VA.getLocInfo() == CCValAssign::BCvt) 1207 return false; 1208 } 1209 1210 // Get a count of how many bytes are to be pushed onto the stack. 1211 NumBytes = CCInfo.getNextStackOffset(); 1212 1213 // Issue CALLSEQ_START. 1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1215 TII.get(TII.getCallFrameSetupOpcode())) 1216 .addImm(NumBytes); 1217 1218 // Prepare to assign register arguments. Every argument uses up a 1219 // GPR protocol register even if it's passed in a floating-point 1220 // register. 1221 unsigned NextGPR = PPC::X3; 1222 unsigned NextFPR = PPC::F1; 1223 1224 // Process arguments. 1225 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { 1226 CCValAssign &VA = ArgLocs[I]; 1227 unsigned Arg = ArgRegs[VA.getValNo()]; 1228 MVT ArgVT = ArgVTs[VA.getValNo()]; 1229 1230 // Handle argument promotion and bitcasts. 1231 switch (VA.getLocInfo()) { 1232 default: 1233 llvm_unreachable("Unknown loc info!"); 1234 case CCValAssign::Full: 1235 break; 1236 case CCValAssign::SExt: { 1237 MVT DestVT = VA.getLocVT(); 1238 const TargetRegisterClass *RC = 1239 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1240 unsigned TmpReg = createResultReg(RC); 1241 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) 1242 llvm_unreachable("Failed to emit a sext!"); 1243 ArgVT = DestVT; 1244 Arg = TmpReg; 1245 break; 1246 } 1247 case CCValAssign::AExt: 1248 case CCValAssign::ZExt: { 1249 MVT DestVT = VA.getLocVT(); 1250 const TargetRegisterClass *RC = 1251 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1252 unsigned TmpReg = createResultReg(RC); 1253 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true)) 1254 llvm_unreachable("Failed to emit a zext!"); 1255 ArgVT = DestVT; 1256 Arg = TmpReg; 1257 break; 1258 } 1259 case CCValAssign::BCvt: { 1260 // FIXME: Not yet handled. 1261 llvm_unreachable("Should have bailed before getting here!"); 1262 break; 1263 } 1264 } 1265 1266 // Copy this argument to the appropriate register. 1267 unsigned ArgReg; 1268 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) { 1269 ArgReg = NextFPR++; 1270 ++NextGPR; 1271 } else 1272 ArgReg = NextGPR++; 1273 1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1275 ArgReg).addReg(Arg); 1276 RegArgs.push_back(ArgReg); 1277 } 1278 1279 return true; 1280} 1281 1282// For a call that we've determined we can fast-select, finish the 1283// call sequence and generate a copy to obtain the return value (if any). 1284void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 1285 const Instruction *I, CallingConv::ID CC, 1286 unsigned &NumBytes, bool IsVarArg) { 1287 // Issue CallSEQ_END. 1288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1289 TII.get(TII.getCallFrameDestroyOpcode())) 1290 .addImm(NumBytes).addImm(0); 1291 1292 // Next, generate a copy to obtain the return value. 1293 // FIXME: No multi-register return values yet, though I don't foresee 1294 // any real difficulties there. 1295 if (RetVT != MVT::isVoid) { 1296 SmallVector<CCValAssign, 16> RVLocs; 1297 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1298 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); 1299 CCValAssign &VA = RVLocs[0]; 1300 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); 1301 assert(VA.isRegLoc() && "Can only return in registers!"); 1302 1303 MVT DestVT = VA.getValVT(); 1304 MVT CopyVT = DestVT; 1305 1306 // Ints smaller than a register still arrive in a full 64-bit 1307 // register, so make sure we recognize this. 1308 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) 1309 CopyVT = MVT::i64; 1310 1311 unsigned SourcePhysReg = VA.getLocReg(); 1312 unsigned ResultReg = 0; 1313 1314 if (RetVT == CopyVT) { 1315 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); 1316 ResultReg = createResultReg(CpyRC); 1317 1318 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1319 TII.get(TargetOpcode::COPY), ResultReg) 1320 .addReg(SourcePhysReg); 1321 1322 // If necessary, round the floating result to single precision. 1323 } else if (CopyVT == MVT::f64) { 1324 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP), 1326 ResultReg).addReg(SourcePhysReg); 1327 1328 // If only the low half of a general register is needed, generate 1329 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be 1330 // used along the fast-isel path (not lowered), and downstream logic 1331 // also doesn't like a direct subreg copy on a physical reg.) 1332 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { 1333 ResultReg = createResultReg(&PPC::GPRCRegClass); 1334 // Convert physical register from G8RC to GPRC. 1335 SourcePhysReg -= PPC::X0 - PPC::R0; 1336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1337 TII.get(TargetOpcode::COPY), ResultReg) 1338 .addReg(SourcePhysReg); 1339 } 1340 1341 assert(ResultReg && "ResultReg unset!"); 1342 UsedRegs.push_back(SourcePhysReg); 1343 UpdateValueMap(I, ResultReg); 1344 } 1345} 1346 1347// Attempt to fast-select a call instruction. 1348bool PPCFastISel::SelectCall(const Instruction *I) { 1349 const CallInst *CI = cast<CallInst>(I); 1350 const Value *Callee = CI->getCalledValue(); 1351 1352 // Can't handle inline asm. 1353 if (isa<InlineAsm>(Callee)) 1354 return false; 1355 1356 // Allow SelectionDAG isel to handle tail calls. 1357 if (CI->isTailCall()) 1358 return false; 1359 1360 // Obtain calling convention. 1361 ImmutableCallSite CS(CI); 1362 CallingConv::ID CC = CS.getCallingConv(); 1363 1364 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1365 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1366 bool IsVarArg = FTy->isVarArg(); 1367 1368 // Not ready for varargs yet. 1369 if (IsVarArg) 1370 return false; 1371 1372 // Handle simple calls for now, with legal return types and 1373 // those that can be extended. 1374 Type *RetTy = I->getType(); 1375 MVT RetVT; 1376 if (RetTy->isVoidTy()) 1377 RetVT = MVT::isVoid; 1378 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && 1379 RetVT != MVT::i8) 1380 return false; 1381 1382 // FIXME: No multi-register return values yet. 1383 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 && 1384 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 && 1385 RetVT != MVT::f64) { 1386 SmallVector<CCValAssign, 16> RVLocs; 1387 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 1388 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS); 1389 if (RVLocs.size() > 1) 1390 return false; 1391 } 1392 1393 // Bail early if more than 8 arguments, as we only currently 1394 // handle arguments passed in registers. 1395 unsigned NumArgs = CS.arg_size(); 1396 if (NumArgs > 8) 1397 return false; 1398 1399 // Set up the argument vectors. 1400 SmallVector<Value*, 8> Args; 1401 SmallVector<unsigned, 8> ArgRegs; 1402 SmallVector<MVT, 8> ArgVTs; 1403 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1404 1405 Args.reserve(NumArgs); 1406 ArgRegs.reserve(NumArgs); 1407 ArgVTs.reserve(NumArgs); 1408 ArgFlags.reserve(NumArgs); 1409 1410 for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end(); 1411 II != IE; ++II) { 1412 // FIXME: ARM does something for intrinsic calls here, check into that. 1413 1414 unsigned AttrIdx = II - CS.arg_begin() + 1; 1415 1416 // Only handle easy calls for now. It would be reasonably easy 1417 // to handle <= 8-byte structures passed ByVal in registers, but we 1418 // have to ensure they are right-justified in the register. 1419 if (CS.paramHasAttr(AttrIdx, Attribute::InReg) || 1420 CS.paramHasAttr(AttrIdx, Attribute::StructRet) || 1421 CS.paramHasAttr(AttrIdx, Attribute::Nest) || 1422 CS.paramHasAttr(AttrIdx, Attribute::ByVal)) 1423 return false; 1424 1425 ISD::ArgFlagsTy Flags; 1426 if (CS.paramHasAttr(AttrIdx, Attribute::SExt)) 1427 Flags.setSExt(); 1428 if (CS.paramHasAttr(AttrIdx, Attribute::ZExt)) 1429 Flags.setZExt(); 1430 1431 Type *ArgTy = (*II)->getType(); 1432 MVT ArgVT; 1433 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8) 1434 return false; 1435 1436 if (ArgVT.isVector()) 1437 return false; 1438 1439 unsigned Arg = getRegForValue(*II); 1440 if (Arg == 0) 1441 return false; 1442 1443 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1444 Flags.setOrigAlign(OriginalAlignment); 1445 1446 Args.push_back(*II); 1447 ArgRegs.push_back(Arg); 1448 ArgVTs.push_back(ArgVT); 1449 ArgFlags.push_back(Flags); 1450 } 1451 1452 // Process the arguments. 1453 SmallVector<unsigned, 8> RegArgs; 1454 unsigned NumBytes; 1455 1456 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 1457 RegArgs, CC, NumBytes, IsVarArg)) 1458 return false; 1459 1460 // FIXME: No handling for function pointers yet. This requires 1461 // implementing the function descriptor (OPD) setup. 1462 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 1463 if (!GV) 1464 return false; 1465 1466 // Build direct call with NOP for TOC restore. 1467 // FIXME: We can and should optimize away the NOP for local calls. 1468 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1469 TII.get(PPC::BL8_NOP)); 1470 // Add callee. 1471 MIB.addGlobalAddress(GV); 1472 1473 // Add implicit physical register uses to the call. 1474 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II) 1475 MIB.addReg(RegArgs[II], RegState::Implicit); 1476 1477 // Add a register mask with the call-preserved registers. Proper 1478 // defs for return values will be added by setPhysRegsDeadExcept(). 1479 MIB.addRegMask(TRI.getCallPreservedMask(CC)); 1480 1481 // Finish off the call including any return values. 1482 SmallVector<unsigned, 4> UsedRegs; 1483 finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg); 1484 1485 // Set all unused physregs defs as dead. 1486 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 1487 1488 return true; 1489} 1490 1491// Attempt to fast-select a return instruction. 1492bool PPCFastISel::SelectRet(const Instruction *I) { 1493 1494 if (!FuncInfo.CanLowerReturn) 1495 return false; 1496 1497 const ReturnInst *Ret = cast<ReturnInst>(I); 1498 const Function &F = *I->getParent()->getParent(); 1499 1500 // Build a list of return value registers. 1501 SmallVector<unsigned, 4> RetRegs; 1502 CallingConv::ID CC = F.getCallingConv(); 1503 1504 if (Ret->getNumOperands() > 0) { 1505 SmallVector<ISD::OutputArg, 4> Outs; 1506 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 1507 1508 // Analyze operands of the call, assigning locations to each operand. 1509 SmallVector<CCValAssign, 16> ValLocs; 1510 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context); 1511 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS); 1512 const Value *RV = Ret->getOperand(0); 1513 1514 // FIXME: Only one output register for now. 1515 if (ValLocs.size() > 1) 1516 return false; 1517 1518 // Special case for returning a constant integer of any size. 1519 // Materialize the constant as an i64 and copy it to the return 1520 // register. This avoids an unnecessary extend or truncate. 1521 if (isa<ConstantInt>(*RV)) { 1522 const Constant *C = cast<Constant>(RV); 1523 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64); 1524 unsigned RetReg = ValLocs[0].getLocReg(); 1525 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1526 RetReg).addReg(SrcReg); 1527 RetRegs.push_back(RetReg); 1528 1529 } else { 1530 unsigned Reg = getRegForValue(RV); 1531 1532 if (Reg == 0) 1533 return false; 1534 1535 // Copy the result values into the output registers. 1536 for (unsigned i = 0; i < ValLocs.size(); ++i) { 1537 1538 CCValAssign &VA = ValLocs[i]; 1539 assert(VA.isRegLoc() && "Can only return in registers!"); 1540 RetRegs.push_back(VA.getLocReg()); 1541 unsigned SrcReg = Reg + VA.getValNo(); 1542 1543 EVT RVEVT = TLI.getValueType(RV->getType()); 1544 if (!RVEVT.isSimple()) 1545 return false; 1546 MVT RVVT = RVEVT.getSimpleVT(); 1547 MVT DestVT = VA.getLocVT(); 1548 1549 if (RVVT != DestVT && RVVT != MVT::i8 && 1550 RVVT != MVT::i16 && RVVT != MVT::i32) 1551 return false; 1552 1553 if (RVVT != DestVT) { 1554 switch (VA.getLocInfo()) { 1555 default: 1556 llvm_unreachable("Unknown loc info!"); 1557 case CCValAssign::Full: 1558 llvm_unreachable("Full value assign but types don't match?"); 1559 case CCValAssign::AExt: 1560 case CCValAssign::ZExt: { 1561 const TargetRegisterClass *RC = 1562 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1563 unsigned TmpReg = createResultReg(RC); 1564 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true)) 1565 return false; 1566 SrcReg = TmpReg; 1567 break; 1568 } 1569 case CCValAssign::SExt: { 1570 const TargetRegisterClass *RC = 1571 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 1572 unsigned TmpReg = createResultReg(RC); 1573 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false)) 1574 return false; 1575 SrcReg = TmpReg; 1576 break; 1577 } 1578 } 1579 } 1580 1581 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1582 TII.get(TargetOpcode::COPY), RetRegs[i]) 1583 .addReg(SrcReg); 1584 } 1585 } 1586 } 1587 1588 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1589 TII.get(PPC::BLR)); 1590 1591 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) 1592 MIB.addReg(RetRegs[i], RegState::Implicit); 1593 1594 return true; 1595} 1596 1597// Attempt to emit an integer extend of SrcReg into DestReg. Both 1598// signed and zero extensions are supported. Return false if we 1599// can't handle it. 1600bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 1601 unsigned DestReg, bool IsZExt) { 1602 if (DestVT != MVT::i32 && DestVT != MVT::i64) 1603 return false; 1604 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32) 1605 return false; 1606 1607 // Signed extensions use EXTSB, EXTSH, EXTSW. 1608 if (!IsZExt) { 1609 unsigned Opc; 1610 if (SrcVT == MVT::i8) 1611 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64; 1612 else if (SrcVT == MVT::i16) 1613 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64; 1614 else { 1615 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??"); 1616 Opc = PPC::EXTSW_32_64; 1617 } 1618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 1619 .addReg(SrcReg); 1620 1621 // Unsigned 32-bit extensions use RLWINM. 1622 } else if (DestVT == MVT::i32) { 1623 unsigned MB; 1624 if (SrcVT == MVT::i8) 1625 MB = 24; 1626 else { 1627 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??"); 1628 MB = 16; 1629 } 1630 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLWINM), 1631 DestReg) 1632 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31); 1633 1634 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source). 1635 } else { 1636 unsigned MB; 1637 if (SrcVT == MVT::i8) 1638 MB = 56; 1639 else if (SrcVT == MVT::i16) 1640 MB = 48; 1641 else 1642 MB = 32; 1643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1644 TII.get(PPC::RLDICL_32_64), DestReg) 1645 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB); 1646 } 1647 1648 return true; 1649} 1650 1651// Attempt to fast-select an indirect branch instruction. 1652bool PPCFastISel::SelectIndirectBr(const Instruction *I) { 1653 unsigned AddrReg = getRegForValue(I->getOperand(0)); 1654 if (AddrReg == 0) 1655 return false; 1656 1657 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8)) 1658 .addReg(AddrReg); 1659 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8)); 1660 1661 const IndirectBrInst *IB = cast<IndirectBrInst>(I); 1662 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i) 1663 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]); 1664 1665 return true; 1666} 1667 1668// Attempt to fast-select an integer truncate instruction. 1669bool PPCFastISel::SelectTrunc(const Instruction *I) { 1670 Value *Src = I->getOperand(0); 1671 EVT SrcVT = TLI.getValueType(Src->getType(), true); 1672 EVT DestVT = TLI.getValueType(I->getType(), true); 1673 1674 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16) 1675 return false; 1676 1677 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) 1678 return false; 1679 1680 unsigned SrcReg = getRegForValue(Src); 1681 if (!SrcReg) 1682 return false; 1683 1684 // The only interesting case is when we need to switch register classes. 1685 if (SrcVT == MVT::i64) { 1686 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); 1687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1688 ResultReg).addReg(SrcReg, 0, PPC::sub_32); 1689 SrcReg = ResultReg; 1690 } 1691 1692 UpdateValueMap(I, SrcReg); 1693 return true; 1694} 1695 1696// Attempt to fast-select an integer extend instruction. 1697bool PPCFastISel::SelectIntExt(const Instruction *I) { 1698 Type *DestTy = I->getType(); 1699 Value *Src = I->getOperand(0); 1700 Type *SrcTy = Src->getType(); 1701 1702 bool IsZExt = isa<ZExtInst>(I); 1703 unsigned SrcReg = getRegForValue(Src); 1704 if (!SrcReg) return false; 1705 1706 EVT SrcEVT, DestEVT; 1707 SrcEVT = TLI.getValueType(SrcTy, true); 1708 DestEVT = TLI.getValueType(DestTy, true); 1709 if (!SrcEVT.isSimple()) 1710 return false; 1711 if (!DestEVT.isSimple()) 1712 return false; 1713 1714 MVT SrcVT = SrcEVT.getSimpleVT(); 1715 MVT DestVT = DestEVT.getSimpleVT(); 1716 1717 // If we know the register class needed for the result of this 1718 // instruction, use it. Otherwise pick the register class of the 1719 // correct size that does not contain X0/R0, since we don't know 1720 // whether downstream uses permit that assignment. 1721 unsigned AssignedReg = FuncInfo.ValueMap[I]; 1722 const TargetRegisterClass *RC = 1723 (AssignedReg ? MRI.getRegClass(AssignedReg) : 1724 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass : 1725 &PPC::GPRC_and_GPRC_NOR0RegClass)); 1726 unsigned ResultReg = createResultReg(RC); 1727 1728 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) 1729 return false; 1730 1731 UpdateValueMap(I, ResultReg); 1732 return true; 1733} 1734 1735// Attempt to fast-select an instruction that wasn't handled by 1736// the table-generated machinery. 1737bool PPCFastISel::TargetSelectInstruction(const Instruction *I) { 1738 1739 switch (I->getOpcode()) { 1740 case Instruction::Load: 1741 return SelectLoad(I); 1742 case Instruction::Store: 1743 return SelectStore(I); 1744 case Instruction::Br: 1745 return SelectBranch(I); 1746 case Instruction::IndirectBr: 1747 return SelectIndirectBr(I); 1748 case Instruction::FPExt: 1749 return SelectFPExt(I); 1750 case Instruction::FPTrunc: 1751 return SelectFPTrunc(I); 1752 case Instruction::SIToFP: 1753 return SelectIToFP(I, /*IsSigned*/ true); 1754 case Instruction::UIToFP: 1755 return SelectIToFP(I, /*IsSigned*/ false); 1756 case Instruction::FPToSI: 1757 return SelectFPToI(I, /*IsSigned*/ true); 1758 case Instruction::FPToUI: 1759 return SelectFPToI(I, /*IsSigned*/ false); 1760 case Instruction::Add: 1761 return SelectBinaryIntOp(I, ISD::ADD); 1762 case Instruction::Or: 1763 return SelectBinaryIntOp(I, ISD::OR); 1764 case Instruction::Sub: 1765 return SelectBinaryIntOp(I, ISD::SUB); 1766 case Instruction::Call: 1767 if (dyn_cast<IntrinsicInst>(I)) 1768 return false; 1769 return SelectCall(I); 1770 case Instruction::Ret: 1771 return SelectRet(I); 1772 case Instruction::Trunc: 1773 return SelectTrunc(I); 1774 case Instruction::ZExt: 1775 case Instruction::SExt: 1776 return SelectIntExt(I); 1777 // Here add other flavors of Instruction::XXX that automated 1778 // cases don't catch. For example, switches are terminators 1779 // that aren't yet handled. 1780 default: 1781 break; 1782 } 1783 return false; 1784} 1785 1786// Materialize a floating-point constant into a register, and return 1787// the register number (or zero if we failed to handle it). 1788unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { 1789 // No plans to handle long double here. 1790 if (VT != MVT::f32 && VT != MVT::f64) 1791 return 0; 1792 1793 // All FP constants are loaded from the constant pool. 1794 unsigned Align = TD.getPrefTypeAlignment(CFP->getType()); 1795 assert(Align > 0 && "Unexpectedly missing alignment information!"); 1796 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); 1797 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 1798 CodeModel::Model CModel = TM.getCodeModel(); 1799 1800 MachineMemOperand *MMO = 1801 FuncInfo.MF->getMachineMemOperand( 1802 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 1803 (VT == MVT::f32) ? 4 : 8, Align); 1804 1805 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; 1806 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 1807 1808 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)). 1809 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) { 1810 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT), 1811 TmpReg) 1812 .addConstantPoolIndex(Idx).addReg(PPC::X2); 1813 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 1814 .addImm(0).addReg(TmpReg).addMemOperand(MMO); 1815 } else { 1816 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)). 1817 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA), 1818 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx); 1819 // But for large code model, we must generate a LDtocL followed 1820 // by the LF[SD]. 1821 if (CModel == CodeModel::Large) { 1822 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 1823 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL), 1824 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg); 1825 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 1826 .addImm(0).addReg(TmpReg2); 1827 } else 1828 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 1829 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO) 1830 .addReg(TmpReg) 1831 .addMemOperand(MMO); 1832 } 1833 1834 return DestReg; 1835} 1836 1837// Materialize the address of a global value into a register, and return 1838// the register number (or zero if we failed to handle it). 1839unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { 1840 assert(VT == MVT::i64 && "Non-address!"); 1841 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; 1842 unsigned DestReg = createResultReg(RC); 1843 1844 // Global values may be plain old object addresses, TLS object 1845 // addresses, constant pool entries, or jump tables. How we generate 1846 // code for these may depend on small, medium, or large code model. 1847 CodeModel::Model CModel = TM.getCodeModel(); 1848 1849 // FIXME: Jump tables are not yet required because fast-isel doesn't 1850 // handle switches; if that changes, we need them as well. For now, 1851 // what follows assumes everything's a generic (or TLS) global address. 1852 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 1853 if (!GVar) { 1854 // If GV is an alias, use the aliasee for determining thread-locality. 1855 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 1856 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)); 1857 } 1858 1859 // FIXME: We don't yet handle the complexity of TLS. 1860 bool IsTLS = GVar && GVar->isThreadLocal(); 1861 if (IsTLS) 1862 return 0; 1863 1864 // For small code model, generate a simple TOC load. 1865 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) 1866 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtoc), DestReg) 1867 .addGlobalAddress(GV).addReg(PPC::X2); 1868 else { 1869 // If the address is an externally defined symbol, a symbol with 1870 // common or externally available linkage, a function address, or a 1871 // jump table address (not yet needed), or if we are generating code 1872 // for large code model, we generate: 1873 // LDtocL(GV, ADDIStocHA(%X2, GV)) 1874 // Otherwise we generate: 1875 // ADDItocL(ADDIStocHA(%X2, GV), GV) 1876 // Either way, start with the ADDIStocHA: 1877 unsigned HighPartReg = createResultReg(RC); 1878 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA), 1879 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV); 1880 1881 // !GVar implies a function address. An external variable is one 1882 // without an initializer. 1883 // If/when switches are implemented, jump tables should be handled 1884 // on the "if" path here. 1885 if (CModel == CodeModel::Large || !GVar || !GVar->hasInitializer() || 1886 GVar->hasCommonLinkage() || GVar->hasAvailableExternallyLinkage()) 1887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL), 1888 DestReg).addGlobalAddress(GV).addReg(HighPartReg); 1889 else 1890 // Otherwise generate the ADDItocL. 1891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDItocL), 1892 DestReg).addReg(HighPartReg).addGlobalAddress(GV); 1893 } 1894 1895 return DestReg; 1896} 1897 1898// Materialize a 32-bit integer constant into a register, and return 1899// the register number (or zero if we failed to handle it). 1900unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm, 1901 const TargetRegisterClass *RC) { 1902 unsigned Lo = Imm & 0xFFFF; 1903 unsigned Hi = (Imm >> 16) & 0xFFFF; 1904 1905 unsigned ResultReg = createResultReg(RC); 1906 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); 1907 1908 if (isInt<16>(Imm)) 1909 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1910 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg) 1911 .addImm(Imm); 1912 else if (Lo) { 1913 // Both Lo and Hi have nonzero bits. 1914 unsigned TmpReg = createResultReg(RC); 1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1916 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg) 1917 .addImm(Hi); 1918 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1919 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg) 1920 .addReg(TmpReg).addImm(Lo); 1921 } else 1922 // Just Hi bits. 1923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1924 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg) 1925 .addImm(Hi); 1926 1927 return ResultReg; 1928} 1929 1930// Materialize a 64-bit integer constant into a register, and return 1931// the register number (or zero if we failed to handle it). 1932unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm, 1933 const TargetRegisterClass *RC) { 1934 unsigned Remainder = 0; 1935 unsigned Shift = 0; 1936 1937 // If the value doesn't fit in 32 bits, see if we can shift it 1938 // so that it fits in 32 bits. 1939 if (!isInt<32>(Imm)) { 1940 Shift = countTrailingZeros<uint64_t>(Imm); 1941 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 1942 1943 if (isInt<32>(ImmSh)) 1944 Imm = ImmSh; 1945 else { 1946 Remainder = Imm; 1947 Shift = 32; 1948 Imm >>= 32; 1949 } 1950 } 1951 1952 // Handle the high-order 32 bits (if shifted) or the whole 32 bits 1953 // (if not shifted). 1954 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC); 1955 if (!Shift) 1956 return TmpReg1; 1957 1958 // If upper 32 bits were not zero, we've built them and need to shift 1959 // them into place. 1960 unsigned TmpReg2; 1961 if (Imm) { 1962 TmpReg2 = createResultReg(RC); 1963 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR), 1964 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift); 1965 } else 1966 TmpReg2 = TmpReg1; 1967 1968 unsigned TmpReg3, Hi, Lo; 1969 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 1970 TmpReg3 = createResultReg(RC); 1971 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8), 1972 TmpReg3).addReg(TmpReg2).addImm(Hi); 1973 } else 1974 TmpReg3 = TmpReg2; 1975 1976 if ((Lo = Remainder & 0xFFFF)) { 1977 unsigned ResultReg = createResultReg(RC); 1978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8), 1979 ResultReg).addReg(TmpReg3).addImm(Lo); 1980 return ResultReg; 1981 } 1982 1983 return TmpReg3; 1984} 1985 1986 1987// Materialize an integer constant into a register, and return 1988// the register number (or zero if we failed to handle it). 1989unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) { 1990 1991 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && 1992 VT != MVT::i8 && VT != MVT::i1) 1993 return 0; 1994 1995 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : 1996 &PPC::GPRCRegClass); 1997 1998 // If the constant is in range, use a load-immediate. 1999 const ConstantInt *CI = cast<ConstantInt>(C); 2000 if (isInt<16>(CI->getSExtValue())) { 2001 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; 2002 unsigned ImmReg = createResultReg(RC); 2003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg) 2004 .addImm(CI->getSExtValue()); 2005 return ImmReg; 2006 } 2007 2008 // Construct the constant piecewise. 2009 int64_t Imm = CI->getZExtValue(); 2010 2011 if (VT == MVT::i64) 2012 return PPCMaterialize64BitInt(Imm, RC); 2013 else if (VT == MVT::i32) 2014 return PPCMaterialize32BitInt(Imm, RC); 2015 2016 return 0; 2017} 2018 2019// Materialize a constant into a register, and return the register 2020// number (or zero if we failed to handle it). 2021unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) { 2022 EVT CEVT = TLI.getValueType(C->getType(), true); 2023 2024 // Only handle simple types. 2025 if (!CEVT.isSimple()) return 0; 2026 MVT VT = CEVT.getSimpleVT(); 2027 2028 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 2029 return PPCMaterializeFP(CFP, VT); 2030 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 2031 return PPCMaterializeGV(GV, VT); 2032 else if (isa<ConstantInt>(C)) 2033 return PPCMaterializeInt(C, VT); 2034 2035 return 0; 2036} 2037 2038// Materialize the address created by an alloca into a register, and 2039// return the register number (or zero if we failed to handle it). 2040unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { 2041 // Don't handle dynamic allocas. 2042 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 2043 2044 MVT VT; 2045 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; 2046 2047 DenseMap<const AllocaInst*, int>::iterator SI = 2048 FuncInfo.StaticAllocaMap.find(AI); 2049 2050 if (SI != FuncInfo.StaticAllocaMap.end()) { 2051 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); 2052 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8), 2053 ResultReg).addFrameIndex(SI->second).addImm(0); 2054 return ResultReg; 2055 } 2056 2057 return 0; 2058} 2059 2060// Fold loads into extends when possible. 2061// FIXME: We can have multiple redundant extend/trunc instructions 2062// following a load. The folding only picks up one. Extend this 2063// to check subsequent instructions for the same pattern and remove 2064// them. Thus ResultReg should be the def reg for the last redundant 2065// instruction in a chain, and all intervening instructions can be 2066// removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll 2067// to add ELF64-NOT: rldicl to the appropriate tests when this works. 2068bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 2069 const LoadInst *LI) { 2070 // Verify we have a legal type before going any further. 2071 MVT VT; 2072 if (!isLoadTypeLegal(LI->getType(), VT)) 2073 return false; 2074 2075 // Combine load followed by zero- or sign-extend. 2076 bool IsZExt = false; 2077 switch(MI->getOpcode()) { 2078 default: 2079 return false; 2080 2081 case PPC::RLDICL: 2082 case PPC::RLDICL_32_64: { 2083 IsZExt = true; 2084 unsigned MB = MI->getOperand(3).getImm(); 2085 if ((VT == MVT::i8 && MB <= 56) || 2086 (VT == MVT::i16 && MB <= 48) || 2087 (VT == MVT::i32 && MB <= 32)) 2088 break; 2089 return false; 2090 } 2091 2092 case PPC::RLWINM: 2093 case PPC::RLWINM8: { 2094 IsZExt = true; 2095 unsigned MB = MI->getOperand(3).getImm(); 2096 if ((VT == MVT::i8 && MB <= 24) || 2097 (VT == MVT::i16 && MB <= 16)) 2098 break; 2099 return false; 2100 } 2101 2102 case PPC::EXTSB: 2103 case PPC::EXTSB8: 2104 case PPC::EXTSB8_32_64: 2105 /* There is no sign-extending load-byte instruction. */ 2106 return false; 2107 2108 case PPC::EXTSH: 2109 case PPC::EXTSH8: 2110 case PPC::EXTSH8_32_64: { 2111 if (VT != MVT::i16 && VT != MVT::i8) 2112 return false; 2113 break; 2114 } 2115 2116 case PPC::EXTSW: 2117 case PPC::EXTSW_32_64: { 2118 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8) 2119 return false; 2120 break; 2121 } 2122 } 2123 2124 // See if we can handle this address. 2125 Address Addr; 2126 if (!PPCComputeAddress(LI->getOperand(0), Addr)) 2127 return false; 2128 2129 unsigned ResultReg = MI->getOperand(0).getReg(); 2130 2131 if (!PPCEmitLoad(VT, ResultReg, Addr, 0, IsZExt)) 2132 return false; 2133 2134 MI->eraseFromParent(); 2135 return true; 2136} 2137 2138// Attempt to lower call arguments in a faster way than done by 2139// the selection DAG code. 2140bool PPCFastISel::FastLowerArguments() { 2141 // Defer to normal argument lowering for now. It's reasonably 2142 // efficient. Consider doing something like ARM to handle the 2143 // case where all args fit in registers, no varargs, no float 2144 // or vector args. 2145 return false; 2146} 2147 2148// Handle materializing integer constants into a register. This is not 2149// automatically generated for PowerPC, so must be explicitly created here. 2150unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) { 2151 2152 if (Opc != ISD::Constant) 2153 return 0; 2154 2155 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && 2156 VT != MVT::i8 && VT != MVT::i1) 2157 return 0; 2158 2159 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : 2160 &PPC::GPRCRegClass); 2161 if (VT == MVT::i64) 2162 return PPCMaterialize64BitInt(Imm, RC); 2163 else 2164 return PPCMaterialize32BitInt(Imm, RC); 2165} 2166 2167// Override for ADDI and ADDI8 to set the correct register class 2168// on RHS operand 0. The automatic infrastructure naively assumes 2169// GPRC for i32 and G8RC for i64; the concept of "no R0" is lost 2170// for these cases. At the moment, none of the other automatically 2171// generated RI instructions require special treatment. However, once 2172// SelectSelect is implemented, "isel" requires similar handling. 2173// 2174// Also be conservative about the output register class. Avoid 2175// assigning R0 or X0 to the output register for GPRC and G8RC 2176// register classes, as any such result could be used in ADDI, etc., 2177// where those regs have another meaning. 2178unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 2179 const TargetRegisterClass *RC, 2180 unsigned Op0, bool Op0IsKill, 2181 uint64_t Imm) { 2182 if (MachineInstOpcode == PPC::ADDI) 2183 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); 2184 else if (MachineInstOpcode == PPC::ADDI8) 2185 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); 2186 2187 const TargetRegisterClass *UseRC = 2188 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2189 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2190 2191 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC, 2192 Op0, Op0IsKill, Imm); 2193} 2194 2195// Override for instructions with one register operand to avoid use of 2196// R0/X0. The automatic infrastructure isn't aware of the context so 2197// we must be conservative. 2198unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 2199 const TargetRegisterClass* RC, 2200 unsigned Op0, bool Op0IsKill) { 2201 const TargetRegisterClass *UseRC = 2202 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2203 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2204 2205 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); 2206} 2207 2208// Override for instructions with two register operands to avoid use 2209// of R0/X0. The automatic infrastructure isn't aware of the context 2210// so we must be conservative. 2211unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 2212 const TargetRegisterClass* RC, 2213 unsigned Op0, bool Op0IsKill, 2214 unsigned Op1, bool Op1IsKill) { 2215 const TargetRegisterClass *UseRC = 2216 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : 2217 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); 2218 2219 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill, 2220 Op1, Op1IsKill); 2221} 2222 2223namespace llvm { 2224 // Create the fast instruction selector for PowerPC64 ELF. 2225 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo, 2226 const TargetLibraryInfo *LibInfo) { 2227 const TargetMachine &TM = FuncInfo.MF->getTarget(); 2228 2229 // Only available on 64-bit ELF for now. 2230 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 2231 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI()) 2232 return new PPCFastISel(FuncInfo, LibInfo); 2233 2234 return 0; 2235 } 2236} 2237