PPC.td revision 263508 
1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// PowerPC Subtarget features.
20//
21 
22//===----------------------------------------------------------------------===//
23// CPU Directives                                                             //
24//===----------------------------------------------------------------------===//
25
26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39                                       "PPC::DIR_E500mc", "">;
40def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective", 
41                                       "PPC::DIR_E5500", "">;
42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49
50def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
51                                        "Enable 64-bit instructions">;
52def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53                              "Enable 64-bit registers usage for ppc32 [beta]">;
54def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
55                                        "Enable Altivec instructions">;
56def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57                                        "Enable the MFOCRF instruction">;
58def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59                                        "Enable the fsqrt instruction">;
60def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
61                                        "Enable the fcpsgn instruction">;
62def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
63                                        "Enable the fre instruction">;
64def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
65                                        "Enable the fres instruction">;
66def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
67                                        "Enable the frsqrte instruction">;
68def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
69                                        "Enable the frsqrtes instruction">;
70def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
71                              "Assume higher precision reciprocal estimates">;
72def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
73                                        "Enable the stfiwx instruction">;
74def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
75                                        "Enable the lfiwax instruction">;
76def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
77                                        "Enable the fri[mnpz] instructions">;
78def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
79  "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
80def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
81                                        "Enable the isel instruction">;
82def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
83                                        "Enable the popcnt[dw] instructions">;
84def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
85                                        "Enable the ldbrx instruction">;
86def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
87                                        "Enable Book E instructions">;
88def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
89                                        "Enable QPX instructions">;
90def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
91                                        "Enable VSX instructions">;
92
93def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
94                                        "Treat mftb as deprecated">;
95def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
96  "Treat vector data stream cache control instructions as deprecated">;
97
98// Note: Future features to add when support is extended to more
99// recent ISA levels:
100//
101// CMPB         p6, p6x, p7        cmpb
102// DFP          p6, p6x, p7        decimal floating-point instructions
103// POPCNTB      p5 through p7      popcntb and related instructions
104// VSX          p7                 vector-scalar instruction set
105
106//===----------------------------------------------------------------------===//
107// Classes used for relation maps.
108//===----------------------------------------------------------------------===//
109// RecFormRel - Filter class used to relate non-record-form instructions with
110// their record-form variants.
111class RecFormRel;
112
113//===----------------------------------------------------------------------===//
114// Relation Map Definitions.
115//===----------------------------------------------------------------------===//
116
117def getRecordFormOpcode : InstrMapping {
118  let FilterClass = "RecFormRel";
119  // Instructions with the same BaseName and Interpretation64Bit values
120  // form a row.
121  let RowFields = ["BaseName", "Interpretation64Bit"];
122  // Instructions with the same RC value form a column.
123  let ColFields = ["RC"];
124  // The key column are the non-record-form instructions.
125  let KeyCol = ["0"];
126  // Value columns RC=1
127  let ValueCols = [["1"]];
128}
129
130def getNonRecordFormOpcode : InstrMapping {
131  let FilterClass = "RecFormRel";
132  // Instructions with the same BaseName and Interpretation64Bit values
133  // form a row.
134  let RowFields = ["BaseName", "Interpretation64Bit"];
135  // Instructions with the same RC value form a column.
136  let ColFields = ["RC"];
137  // The key column are the record-form instructions.
138  let KeyCol = ["1"];
139  // Value columns are RC=0
140  let ValueCols = [["0"]];
141}
142
143//===----------------------------------------------------------------------===//
144// Register File Description
145//===----------------------------------------------------------------------===//
146
147include "PPCRegisterInfo.td"
148include "PPCSchedule.td"
149include "PPCInstrInfo.td"
150
151//===----------------------------------------------------------------------===//
152// PowerPC processors supported.
153//
154
155def : Processor<"generic", G3Itineraries, [Directive32]>;
156def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
157                                           FeatureFRES, FeatureFRSQRTE,
158                                           FeatureBookE, DeprecatedMFTB]>;
159def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
160                                           FeatureFRES, FeatureFRSQRTE,
161                                           FeatureBookE, DeprecatedMFTB]>;
162def : Processor<"601", G3Itineraries, [Directive601]>;
163def : Processor<"602", G3Itineraries, [Directive602]>;
164def : Processor<"603", G3Itineraries, [Directive603,
165                                       FeatureFRES, FeatureFRSQRTE]>;
166def : Processor<"603e", G3Itineraries, [Directive603,
167                                        FeatureFRES, FeatureFRSQRTE]>;
168def : Processor<"603ev", G3Itineraries, [Directive603,
169                                         FeatureFRES, FeatureFRSQRTE]>;
170def : Processor<"604", G3Itineraries, [Directive604,
171                                       FeatureFRES, FeatureFRSQRTE]>;
172def : Processor<"604e", G3Itineraries, [Directive604,
173                                        FeatureFRES, FeatureFRSQRTE]>;
174def : Processor<"620", G3Itineraries, [Directive620,
175                                       FeatureFRES, FeatureFRSQRTE]>;
176def : Processor<"750", G4Itineraries, [Directive750,
177                                       FeatureFRES, FeatureFRSQRTE]>;
178def : Processor<"g3", G3Itineraries, [Directive750,
179                                      FeatureFRES, FeatureFRSQRTE]>;
180def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
181                                        FeatureFRES, FeatureFRSQRTE]>;
182def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
183                                      FeatureFRES, FeatureFRSQRTE]>;
184def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
185                                            FeatureFRES, FeatureFRSQRTE]>;
186def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
187                                           FeatureFRES, FeatureFRSQRTE]>;
188def : ProcessorModel<"970", G5Model,
189                  [Directive970, FeatureAltivec,
190                   FeatureMFOCRF, FeatureFSqrt,
191                   FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
192                   Feature64Bit /*, Feature64BitRegs */]>;
193def : ProcessorModel<"g5", G5Model,
194                  [Directive970, FeatureAltivec,
195                   FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
196                   FeatureFRES, FeatureFRSQRTE,
197                   Feature64Bit /*, Feature64BitRegs */,
198                   DeprecatedMFTB, DeprecatedDST]>;
199def : ProcessorModel<"e500mc", PPCE500mcModel,
200                  [DirectiveE500mc, FeatureMFOCRF,
201                   FeatureSTFIWX, FeatureBookE, FeatureISEL,
202                   DeprecatedMFTB]>;
203def : ProcessorModel<"e5500", PPCE5500Model,
204                  [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
205                   FeatureSTFIWX, FeatureBookE, FeatureISEL,
206                   DeprecatedMFTB]>;
207def : ProcessorModel<"a2", PPCA2Model,
208                  [DirectiveA2, FeatureBookE, FeatureMFOCRF,
209                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
210                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
211                   FeatureSTFIWX, FeatureLFIWAX,
212                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
213                   FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
214               /*, Feature64BitRegs */, DeprecatedMFTB]>;
215def : ProcessorModel<"a2q", PPCA2Model,
216                  [DirectiveA2, FeatureBookE, FeatureMFOCRF,
217                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
218                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
219                   FeatureSTFIWX, FeatureLFIWAX,
220                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
221                   FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
222               /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
223def : ProcessorModel<"pwr3", G5Model,
224                  [DirectivePwr3, FeatureAltivec,
225                   FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
226                   FeatureSTFIWX, Feature64Bit]>;
227def : ProcessorModel<"pwr4", G5Model,
228                  [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
229                   FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
230                   FeatureSTFIWX, Feature64Bit]>;
231def : ProcessorModel<"pwr5", G5Model,
232                  [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
233                   FeatureFSqrt, FeatureFRE, FeatureFRES,
234                   FeatureFRSQRTE, FeatureFRSQRTES,
235                   FeatureSTFIWX, Feature64Bit,
236                   DeprecatedMFTB, DeprecatedDST]>;
237def : ProcessorModel<"pwr5x", G5Model,
238                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
239                   FeatureFSqrt, FeatureFRE, FeatureFRES,
240                   FeatureFRSQRTE, FeatureFRSQRTES,
241                   FeatureSTFIWX, FeatureFPRND, Feature64Bit,
242                   DeprecatedMFTB, DeprecatedDST]>;
243def : ProcessorModel<"pwr6", G5Model,
244                  [DirectivePwr6, FeatureAltivec,
245                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
246                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
247                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
248                   FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
249                   DeprecatedMFTB, DeprecatedDST]>;
250def : ProcessorModel<"pwr6x", G5Model,
251                  [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
252                   FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
253                   FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
254                   FeatureSTFIWX, FeatureLFIWAX,
255                   FeatureFPRND, Feature64Bit,
256                   DeprecatedMFTB, DeprecatedDST]>;
257def : ProcessorModel<"pwr7", G5Model,
258                  [DirectivePwr7, FeatureAltivec,
259                   FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
260                   FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
261                   FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
262                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
263                   FeaturePOPCNTD, FeatureLDBRX,
264                   Feature64Bit /*, Feature64BitRegs */,
265                   DeprecatedMFTB, DeprecatedDST]>;
266def : Processor<"ppc", G3Itineraries, [Directive32]>;
267def : ProcessorModel<"ppc64", G5Model,
268                  [Directive64, FeatureAltivec,
269                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
270                   FeatureFRSQRTE, FeatureSTFIWX,
271                   Feature64Bit /*, Feature64BitRegs */]>;
272def : ProcessorModel<"ppc64le", G5Model,
273                  [Directive64, FeatureAltivec,
274                   FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
275                   FeatureFRSQRTE, FeatureSTFIWX,
276                   Feature64Bit /*, Feature64BitRegs */]>;
277
278//===----------------------------------------------------------------------===//
279// Calling Conventions
280//===----------------------------------------------------------------------===//
281
282include "PPCCallingConv.td"
283
284def PPCInstrInfo : InstrInfo {
285  let isLittleEndianEncoding = 1;
286}
287
288def PPCAsmWriter : AsmWriter {
289  string AsmWriterClassName  = "InstPrinter";
290  bit isMCAsmWriter = 1;
291}
292
293def PPCAsmParser : AsmParser {
294  let ShouldEmitMatchRegisterName = 0;
295}
296
297def PPCAsmParserVariant : AsmParserVariant {
298  int Variant = 0;
299
300  // We do not use hard coded registers in asm strings.  However, some
301  // InstAlias definitions use immediate literals.  Set RegisterPrefix
302  // so that those are not misinterpreted as registers.
303  string RegisterPrefix = "%";
304}
305
306def PPC : Target {
307  // Information about the instructions.
308  let InstructionSet = PPCInstrInfo;
309  
310  let AssemblyWriters = [PPCAsmWriter];
311  let AssemblyParsers = [PPCAsmParser];
312  let AssemblyParserVariants = [PPCAsmParserVariant];
313}
314