1239310Sdim//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the University of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim// 10239310Sdim// This file contains the entry points for global functions defined in 11239310Sdim// the LLVM NVPTX back-end. 12239310Sdim// 13239310Sdim//===----------------------------------------------------------------------===// 14239310Sdim 15239310Sdim#ifndef LLVM_TARGET_NVPTX_H 16239310Sdim#define LLVM_TARGET_NVPTX_H 17239310Sdim 18249423Sdim#include "MCTargetDesc/NVPTXBaseInfo.h" 19251662Sdim#include "llvm/ADT/StringMap.h" 20249423Sdim#include "llvm/IR/Module.h" 21249423Sdim#include "llvm/IR/Value.h" 22239310Sdim#include "llvm/Support/ErrorHandling.h" 23239310Sdim#include "llvm/Target/TargetMachine.h" 24239310Sdim#include <cassert> 25239310Sdim#include <iosfwd> 26239310Sdim 27239310Sdimnamespace llvm { 28239310Sdimclass NVPTXTargetMachine; 29239310Sdimclass FunctionPass; 30263508Sdimclass MachineFunctionPass; 31239310Sdimclass formatted_raw_ostream; 32239310Sdim 33239310Sdimnamespace NVPTXCC { 34239310Sdimenum CondCodes { 35239310Sdim EQ, 36239310Sdim NE, 37239310Sdim LT, 38239310Sdim LE, 39239310Sdim GT, 40239310Sdim GE 41239310Sdim}; 42239310Sdim} 43239310Sdim 44239310Sdiminline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) { 45239310Sdim switch (CC) { 46249423Sdim case NVPTXCC::NE: 47249423Sdim return "ne"; 48249423Sdim case NVPTXCC::EQ: 49249423Sdim return "eq"; 50249423Sdim case NVPTXCC::LT: 51249423Sdim return "lt"; 52249423Sdim case NVPTXCC::LE: 53249423Sdim return "le"; 54249423Sdim case NVPTXCC::GT: 55249423Sdim return "gt"; 56249423Sdim case NVPTXCC::GE: 57249423Sdim return "ge"; 58239310Sdim } 59239310Sdim llvm_unreachable("Unknown condition code"); 60239310Sdim} 61239310Sdim 62249423SdimFunctionPass * 63249423SdimcreateNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel); 64251662SdimModulePass *createGenericToNVVMPass(); 65251662SdimModulePass *createNVVMReflectPass(); 66251662SdimModulePass *createNVVMReflectPass(const StringMap<int>& Mapping); 67263508SdimMachineFunctionPass *createNVPTXPrologEpilogPass(); 68239310Sdim 69239310Sdimbool isImageOrSamplerVal(const Value *, const Module *); 70239310Sdim 71239310Sdimextern Target TheNVPTXTarget32; 72239310Sdimextern Target TheNVPTXTarget64; 73239310Sdim 74249423Sdimnamespace NVPTX { 75239310Sdimenum DrvInterface { 76239310Sdim NVCL, 77263508Sdim CUDA 78239310Sdim}; 79239310Sdim 80239310Sdim// A field inside TSFlags needs a shift and a mask. The usage is 81239310Sdim// always as follows : 82239310Sdim// ((TSFlags & fieldMask) >> fieldShift) 83239310Sdim// The enum keeps the mask, the shift, and all valid values of the 84239310Sdim// field in one place. 85239310Sdimenum VecInstType { 86239310Sdim VecInstTypeShift = 0, 87239310Sdim VecInstTypeMask = 0xF, 88239310Sdim 89239310Sdim VecNOP = 0, 90239310Sdim VecLoad = 1, 91239310Sdim VecStore = 2, 92239310Sdim VecBuild = 3, 93239310Sdim VecShuffle = 4, 94239310Sdim VecExtract = 5, 95239310Sdim VecInsert = 6, 96239310Sdim VecDest = 7, 97239310Sdim VecOther = 15 98239310Sdim}; 99239310Sdim 100239310Sdimenum SimpleMove { 101239310Sdim SimpleMoveMask = 0x10, 102239310Sdim SimpleMoveShift = 4 103239310Sdim}; 104239310Sdimenum LoadStore { 105239310Sdim isLoadMask = 0x20, 106239310Sdim isLoadShift = 5, 107239310Sdim isStoreMask = 0x40, 108239310Sdim isStoreShift = 6 109239310Sdim}; 110239310Sdim 111239310Sdimnamespace PTXLdStInstCode { 112249423Sdimenum AddressSpace { 113239310Sdim GENERIC = 0, 114239310Sdim GLOBAL = 1, 115239310Sdim CONSTANT = 2, 116239310Sdim SHARED = 3, 117239310Sdim PARAM = 4, 118239310Sdim LOCAL = 5 119239310Sdim}; 120239310Sdimenum FromType { 121239310Sdim Unsigned = 0, 122239310Sdim Signed, 123239310Sdim Float 124239310Sdim}; 125239310Sdimenum VecType { 126239310Sdim Scalar = 1, 127239310Sdim V2 = 2, 128239310Sdim V4 = 4 129239310Sdim}; 130239310Sdim} 131263508Sdim 132263508Sdim/// PTXCvtMode - Conversion code enumeration 133263508Sdimnamespace PTXCvtMode { 134263508Sdimenum CvtMode { 135263508Sdim NONE = 0, 136263508Sdim RNI, 137263508Sdim RZI, 138263508Sdim RMI, 139263508Sdim RPI, 140263508Sdim RN, 141263508Sdim RZ, 142263508Sdim RM, 143263508Sdim RP, 144263508Sdim 145263508Sdim BASE_MASK = 0x0F, 146263508Sdim FTZ_FLAG = 0x10, 147263508Sdim SAT_FLAG = 0x20 148263508Sdim}; 149239310Sdim} 150263508Sdim 151263508Sdim/// PTXCmpMode - Comparison mode enumeration 152263508Sdimnamespace PTXCmpMode { 153263508Sdimenum CmpMode { 154263508Sdim EQ = 0, 155263508Sdim NE, 156263508Sdim LT, 157263508Sdim LE, 158263508Sdim GT, 159263508Sdim GE, 160263508Sdim LO, 161263508Sdim LS, 162263508Sdim HI, 163263508Sdim HS, 164263508Sdim EQU, 165263508Sdim NEU, 166263508Sdim LTU, 167263508Sdim LEU, 168263508Sdim GTU, 169263508Sdim GEU, 170263508Sdim NUM, 171263508Sdim // NAN is a MACRO 172263508Sdim NotANumber, 173263508Sdim 174263508Sdim BASE_MASK = 0xFF, 175263508Sdim FTZ_FLAG = 0x100 176263508Sdim}; 177263508Sdim} 178263508Sdim} 179239310Sdim} // end namespace llvm; 180239310Sdim 181239310Sdim// Defines symbolic names for NVPTX registers. This defines a mapping from 182239310Sdim// register name to register number. 183239310Sdim#define GET_REGINFO_ENUM 184239310Sdim#include "NVPTXGenRegisterInfo.inc" 185239310Sdim 186239310Sdim// Defines symbolic names for the NVPTX instructions. 187239310Sdim#define GET_INSTRINFO_ENUM 188239310Sdim#include "NVPTXGenInstrInfo.inc" 189239310Sdim 190239310Sdim#endif 191