1234353Sdim//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Describe MIPS instructions format 12193323Sed// 13193323Sed// CPU INSTRUCTION FORMATS 14193323Sed// 15193323Sed// opcode - operation code. 16193323Sed// rs - src reg. 17193323Sed// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18193323Sed// rd - dst reg, only used on 3 regs instr. 19193323Sed// shamt - only used on shift instructions, contains the shift amount. 20193323Sed// funct - combined with opcode field give us an operation code. 21193323Sed// 22193323Sed//===----------------------------------------------------------------------===// 23193323Sed 24228379Sdim// Format specifies the encoding used by the instruction. This is part of the 25228379Sdim// ad-hoc solution used to emit machine instruction encodings by our machine 26228379Sdim// code emitter. 27228379Sdimclass Format<bits<4> val> { 28228379Sdim bits<4> Value = val; 29228379Sdim} 30228379Sdim 31228379Sdimdef Pseudo : Format<0>; 32228379Sdimdef FrmR : Format<1>; 33228379Sdimdef FrmI : Format<2>; 34228379Sdimdef FrmJ : Format<3>; 35228379Sdimdef FrmFR : Format<4>; 36228379Sdimdef FrmFI : Format<5>; 37228379Sdimdef FrmOther : Format<6>; // Instruction w/ a custom format 38228379Sdim 39251662Sdimclass MMRel; 40251662Sdim 41251662Sdimdef Std2MicroMips : InstrMapping { 42251662Sdim let FilterClass = "MMRel"; 43251662Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 44251662Sdim let RowFields = ["BaseOpcode"]; 45251662Sdim // Instructions with the same predicate sense form a column. 46251662Sdim let ColFields = ["Arch"]; 47251662Sdim // The key column is the unpredicated instructions. 48251662Sdim let KeyCol = ["se"]; 49251662Sdim // Value columns are PredSense=true and PredSense=false 50251662Sdim let ValueCols = [["se"], ["micromips"]]; 51251662Sdim} 52251662Sdim 53251662Sdimclass StdArch { 54251662Sdim string Arch = "se"; 55251662Sdim} 56251662Sdim 57193323Sed// Generic Mips Format 58221345Sdimclass MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59228379Sdim InstrItinClass itin, Format f>: Instruction 60193323Sed{ 61193323Sed field bits<32> Inst; 62228379Sdim Format Form = f; 63193323Sed 64193323Sed let Namespace = "Mips"; 65193323Sed 66234982Sdim let Size = 4; 67234982Sdim 68228379Sdim bits<6> Opcode = 0; 69193323Sed 70228379Sdim // Top 6 bits are the 'opcode' field 71228379Sdim let Inst{31-26} = Opcode; 72221345Sdim 73228379Sdim let OutOperandList = outs; 74228379Sdim let InOperandList = ins; 75193323Sed 76193323Sed let AsmString = asmstr; 77193323Sed let Pattern = pattern; 78193323Sed let Itinerary = itin; 79228379Sdim 80228379Sdim // 81228379Sdim // Attributes specific to Mips instructions... 82228379Sdim // 83228379Sdim bits<4> FormBits = Form.Value; 84228379Sdim 85228379Sdim // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86228379Sdim let TSFlags{3-0} = FormBits; 87234982Sdim 88234982Sdim let DecoderNamespace = "Mips"; 89234982Sdim 90234982Sdim field bits<32> SoftFail = 0; 91193323Sed} 92193323Sed 93239462Sdim// Mips32/64 Instruction Format 94239462Sdimclass InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95251662Sdim InstrItinClass itin, Format f, string opstr = ""> : 96239462Sdim MipsInst<outs, ins, asmstr, pattern, itin, f> { 97249423Sdim let Predicates = [HasStdEnc]; 98251662Sdim string BaseOpcode = opstr; 99251662Sdim string Arch; 100239462Sdim} 101239462Sdim 102193323Sed// Mips Pseudo Instructions Format 103249423Sdimclass MipsPseudo<dag outs, dag ins, list<dag> pattern, 104249423Sdim InstrItinClass itin = IIPseudo> : 105249423Sdim MipsInst<outs, ins, "", pattern, itin, Pseudo> { 106228379Sdim let isCodeGenOnly = 1; 107226633Sdim let isPseudo = 1; 108226633Sdim} 109193323Sed 110239462Sdim// Mips32/64 Pseudo Instruction Format 111249423Sdimclass PseudoSE<dag outs, dag ins, list<dag> pattern, 112249423Sdim InstrItinClass itin = IIPseudo>: 113249423Sdim MipsPseudo<outs, ins, pattern, itin> { 114249423Sdim let Predicates = [HasStdEnc]; 115239462Sdim} 116239462Sdim 117243830Sdim// Pseudo-instructions for alternate assembly syntax (never used by codegen). 118243830Sdim// These are aliases that require C++ handling to convert to the target 119243830Sdim// instruction, while InstAliases can be handled directly by tblgen. 120243830Sdimclass MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 121243830Sdim MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 122243830Sdim let isPseudo = 1; 123243830Sdim let Pattern = []; 124243830Sdim} 125193323Sed//===----------------------------------------------------------------------===// 126193323Sed// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 127193323Sed//===----------------------------------------------------------------------===// 128193323Sed 129193323Sedclass FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 130193323Sed list<dag> pattern, InstrItinClass itin>: 131239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmR> 132193323Sed{ 133193323Sed bits<5> rd; 134193323Sed bits<5> rs; 135193323Sed bits<5> rt; 136193323Sed bits<5> shamt; 137193323Sed bits<6> funct; 138193323Sed 139228379Sdim let Opcode = op; 140193323Sed let funct = _funct; 141193323Sed 142193323Sed let Inst{25-21} = rs; 143221345Sdim let Inst{20-16} = rt; 144193323Sed let Inst{15-11} = rd; 145193323Sed let Inst{10-6} = shamt; 146193323Sed let Inst{5-0} = funct; 147193323Sed} 148193323Sed 149193323Sed//===----------------------------------------------------------------------===// 150193323Sed// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 151193323Sed//===----------------------------------------------------------------------===// 152193323Sed 153193323Sedclass FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 154239462Sdim InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 155193323Sed{ 156193323Sed bits<5> rt; 157193323Sed bits<5> rs; 158193323Sed bits<16> imm16; 159193323Sed 160228379Sdim let Opcode = op; 161193323Sed 162193323Sed let Inst{25-21} = rs; 163221345Sdim let Inst{20-16} = rt; 164193323Sed let Inst{15-0} = imm16; 165193323Sed} 166193323Sed 167234353Sdimclass BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 168226633Sdim list<dag> pattern, InstrItinClass itin>: 169239462Sdim InstSE<outs, ins, asmstr, pattern, itin, FrmI> 170226633Sdim{ 171226633Sdim bits<5> rs; 172226633Sdim bits<5> rt; 173226633Sdim bits<16> imm16; 174226633Sdim 175228379Sdim let Opcode = op; 176226633Sdim 177226633Sdim let Inst{25-21} = rs; 178226633Sdim let Inst{20-16} = rt; 179226633Sdim let Inst{15-0} = imm16; 180226633Sdim} 181226633Sdim 182193323Sed//===----------------------------------------------------------------------===// 183193323Sed// Format J instruction class in Mips : <|opcode|address|> 184193323Sed//===----------------------------------------------------------------------===// 185193323Sed 186263508Sdimclass FJ<bits<6> op> : StdArch 187193323Sed{ 188249423Sdim bits<26> target; 189193323Sed 190249423Sdim bits<32> Inst; 191221345Sdim 192249423Sdim let Inst{31-26} = op; 193249423Sdim let Inst{25-0} = target; 194193323Sed} 195193323Sed 196249423Sdim//===----------------------------------------------------------------------===// 197243830Sdim// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 198193323Sed//===----------------------------------------------------------------------===// 199249423Sdimclass MFC3OP_FM<bits<6> op, bits<5> mfmt> 200243830Sdim{ 201243830Sdim bits<5> rt; 202243830Sdim bits<5> rd; 203243830Sdim bits<3> sel; 204243830Sdim 205249423Sdim bits<32> Inst; 206243830Sdim 207249423Sdim let Inst{31-26} = op; 208243830Sdim let Inst{25-21} = mfmt; 209243830Sdim let Inst{20-16} = rt; 210243830Sdim let Inst{15-11} = rd; 211243830Sdim let Inst{10-3} = 0; 212243830Sdim let Inst{2-0} = sel; 213243830Sdim} 214243830Sdim 215251662Sdimclass ADD_FM<bits<6> op, bits<6> funct> : StdArch { 216249423Sdim bits<5> rd; 217249423Sdim bits<5> rs; 218249423Sdim bits<5> rt; 219249423Sdim 220249423Sdim bits<32> Inst; 221249423Sdim 222249423Sdim let Inst{31-26} = op; 223249423Sdim let Inst{25-21} = rs; 224249423Sdim let Inst{20-16} = rt; 225249423Sdim let Inst{15-11} = rd; 226249423Sdim let Inst{10-6} = 0; 227249423Sdim let Inst{5-0} = funct; 228249423Sdim} 229249423Sdim 230251662Sdimclass ADDI_FM<bits<6> op> : StdArch { 231249423Sdim bits<5> rs; 232249423Sdim bits<5> rt; 233249423Sdim bits<16> imm16; 234249423Sdim 235249423Sdim bits<32> Inst; 236249423Sdim 237249423Sdim let Inst{31-26} = op; 238249423Sdim let Inst{25-21} = rs; 239249423Sdim let Inst{20-16} = rt; 240249423Sdim let Inst{15-0} = imm16; 241249423Sdim} 242249423Sdim 243251662Sdimclass SRA_FM<bits<6> funct, bit rotate> : StdArch { 244249423Sdim bits<5> rd; 245249423Sdim bits<5> rt; 246249423Sdim bits<5> shamt; 247249423Sdim 248249423Sdim bits<32> Inst; 249249423Sdim 250249423Sdim let Inst{31-26} = 0; 251249423Sdim let Inst{25-22} = 0; 252249423Sdim let Inst{21} = rotate; 253249423Sdim let Inst{20-16} = rt; 254249423Sdim let Inst{15-11} = rd; 255249423Sdim let Inst{10-6} = shamt; 256249423Sdim let Inst{5-0} = funct; 257249423Sdim} 258249423Sdim 259251662Sdimclass SRLV_FM<bits<6> funct, bit rotate> : StdArch { 260249423Sdim bits<5> rd; 261249423Sdim bits<5> rt; 262249423Sdim bits<5> rs; 263249423Sdim 264249423Sdim bits<32> Inst; 265249423Sdim 266249423Sdim let Inst{31-26} = 0; 267249423Sdim let Inst{25-21} = rs; 268249423Sdim let Inst{20-16} = rt; 269249423Sdim let Inst{15-11} = rd; 270249423Sdim let Inst{10-7} = 0; 271249423Sdim let Inst{6} = rotate; 272249423Sdim let Inst{5-0} = funct; 273249423Sdim} 274249423Sdim 275263508Sdimclass BEQ_FM<bits<6> op> : StdArch { 276249423Sdim bits<5> rs; 277249423Sdim bits<5> rt; 278249423Sdim bits<16> offset; 279249423Sdim 280249423Sdim bits<32> Inst; 281249423Sdim 282249423Sdim let Inst{31-26} = op; 283249423Sdim let Inst{25-21} = rs; 284249423Sdim let Inst{20-16} = rt; 285249423Sdim let Inst{15-0} = offset; 286249423Sdim} 287249423Sdim 288263508Sdimclass BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 289249423Sdim bits<5> rs; 290249423Sdim bits<16> offset; 291249423Sdim 292249423Sdim bits<32> Inst; 293249423Sdim 294249423Sdim let Inst{31-26} = op; 295249423Sdim let Inst{25-21} = rs; 296249423Sdim let Inst{20-16} = funct; 297249423Sdim let Inst{15-0} = offset; 298249423Sdim} 299249423Sdim 300251662Sdimclass SLTI_FM<bits<6> op> : StdArch { 301249423Sdim bits<5> rt; 302249423Sdim bits<5> rs; 303249423Sdim bits<16> imm16; 304249423Sdim 305249423Sdim bits<32> Inst; 306249423Sdim 307249423Sdim let Inst{31-26} = op; 308249423Sdim let Inst{25-21} = rs; 309249423Sdim let Inst{20-16} = rt; 310249423Sdim let Inst{15-0} = imm16; 311249423Sdim} 312249423Sdim 313263508Sdimclass MFLO_FM<bits<6> funct> : StdArch { 314249423Sdim bits<5> rd; 315249423Sdim 316249423Sdim bits<32> Inst; 317249423Sdim 318249423Sdim let Inst{31-26} = 0; 319249423Sdim let Inst{25-16} = 0; 320249423Sdim let Inst{15-11} = rd; 321249423Sdim let Inst{10-6} = 0; 322249423Sdim let Inst{5-0} = funct; 323249423Sdim} 324249423Sdim 325263508Sdimclass MTLO_FM<bits<6> funct> : StdArch { 326249423Sdim bits<5> rs; 327249423Sdim 328249423Sdim bits<32> Inst; 329249423Sdim 330249423Sdim let Inst{31-26} = 0; 331249423Sdim let Inst{25-21} = rs; 332249423Sdim let Inst{20-6} = 0; 333249423Sdim let Inst{5-0} = funct; 334249423Sdim} 335249423Sdim 336263508Sdimclass SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 337249423Sdim bits<5> rd; 338249423Sdim bits<5> rt; 339249423Sdim 340249423Sdim bits<32> Inst; 341249423Sdim 342249423Sdim let Inst{31-26} = 0x1f; 343249423Sdim let Inst{25-21} = 0; 344249423Sdim let Inst{20-16} = rt; 345249423Sdim let Inst{15-11} = rd; 346249423Sdim let Inst{10-6} = funct; 347249423Sdim let Inst{5-0} = funct2; 348249423Sdim} 349249423Sdim 350263508Sdimclass CLO_FM<bits<6> funct> : StdArch { 351249423Sdim bits<5> rd; 352249423Sdim bits<5> rs; 353249423Sdim bits<5> rt; 354249423Sdim 355249423Sdim bits<32> Inst; 356249423Sdim 357249423Sdim let Inst{31-26} = 0x1c; 358249423Sdim let Inst{25-21} = rs; 359249423Sdim let Inst{20-16} = rt; 360249423Sdim let Inst{15-11} = rd; 361249423Sdim let Inst{10-6} = 0; 362249423Sdim let Inst{5-0} = funct; 363249423Sdim let rt = rd; 364249423Sdim} 365249423Sdim 366263508Sdimclass LUI_FM : StdArch { 367249423Sdim bits<5> rt; 368249423Sdim bits<16> imm16; 369249423Sdim 370249423Sdim bits<32> Inst; 371249423Sdim 372249423Sdim let Inst{31-26} = 0xf; 373249423Sdim let Inst{25-21} = 0; 374249423Sdim let Inst{20-16} = rt; 375249423Sdim let Inst{15-0} = imm16; 376249423Sdim} 377249423Sdim 378263508Sdimclass JALR_FM : StdArch { 379249423Sdim bits<5> rd; 380249423Sdim bits<5> rs; 381249423Sdim 382249423Sdim bits<32> Inst; 383249423Sdim 384249423Sdim let Inst{31-26} = 0; 385249423Sdim let Inst{25-21} = rs; 386249423Sdim let Inst{20-16} = 0; 387249423Sdim let Inst{15-11} = rd; 388249423Sdim let Inst{10-6} = 0; 389249423Sdim let Inst{5-0} = 9; 390249423Sdim} 391249423Sdim 392263508Sdimclass BGEZAL_FM<bits<5> funct> : StdArch { 393249423Sdim bits<5> rs; 394249423Sdim bits<16> offset; 395249423Sdim 396249423Sdim bits<32> Inst; 397249423Sdim 398249423Sdim let Inst{31-26} = 1; 399249423Sdim let Inst{25-21} = rs; 400249423Sdim let Inst{20-16} = funct; 401249423Sdim let Inst{15-0} = offset; 402249423Sdim} 403249423Sdim 404249423Sdimclass SYNC_FM { 405249423Sdim bits<5> stype; 406249423Sdim 407249423Sdim bits<32> Inst; 408249423Sdim 409249423Sdim let Inst{31-26} = 0; 410249423Sdim let Inst{10-6} = stype; 411249423Sdim let Inst{5-0} = 0xf; 412249423Sdim} 413249423Sdim 414251662Sdimclass MULT_FM<bits<6> op, bits<6> funct> : StdArch { 415249423Sdim bits<5> rs; 416249423Sdim bits<5> rt; 417249423Sdim 418249423Sdim bits<32> Inst; 419249423Sdim 420249423Sdim let Inst{31-26} = op; 421249423Sdim let Inst{25-21} = rs; 422249423Sdim let Inst{20-16} = rt; 423249423Sdim let Inst{15-6} = 0; 424249423Sdim let Inst{5-0} = funct; 425249423Sdim} 426249423Sdim 427263508Sdimclass EXT_FM<bits<6> funct> : StdArch { 428249423Sdim bits<5> rt; 429249423Sdim bits<5> rs; 430249423Sdim bits<5> pos; 431249423Sdim bits<5> size; 432249423Sdim 433249423Sdim bits<32> Inst; 434249423Sdim 435249423Sdim let Inst{31-26} = 0x1f; 436249423Sdim let Inst{25-21} = rs; 437249423Sdim let Inst{20-16} = rt; 438249423Sdim let Inst{15-11} = size; 439249423Sdim let Inst{10-6} = pos; 440249423Sdim let Inst{5-0} = funct; 441249423Sdim} 442249423Sdim 443249423Sdimclass RDHWR_FM { 444249423Sdim bits<5> rt; 445249423Sdim bits<5> rd; 446249423Sdim 447249423Sdim bits<32> Inst; 448249423Sdim 449249423Sdim let Inst{31-26} = 0x1f; 450249423Sdim let Inst{25-21} = 0; 451249423Sdim let Inst{20-16} = rt; 452249423Sdim let Inst{15-11} = rd; 453249423Sdim let Inst{10-6} = 0; 454249423Sdim let Inst{5-0} = 0x3b; 455249423Sdim} 456249423Sdim 457263508Sdimclass TEQ_FM<bits<6> funct> : StdArch { 458263508Sdim bits<5> rs; 459263508Sdim bits<5> rt; 460263508Sdim bits<10> code_; 461263508Sdim 462263508Sdim bits<32> Inst; 463263508Sdim 464263508Sdim let Inst{31-26} = 0; 465263508Sdim let Inst{25-21} = rs; 466263508Sdim let Inst{20-16} = rt; 467263508Sdim let Inst{15-6} = code_; 468263508Sdim let Inst{5-0} = funct; 469263508Sdim} 470263508Sdim 471263508Sdimclass TEQI_FM<bits<5> funct> : StdArch { 472263508Sdim bits<5> rs; 473263508Sdim bits<16> imm16; 474263508Sdim 475263508Sdim bits<32> Inst; 476263508Sdim 477263508Sdim let Inst{31-26} = 1; 478263508Sdim let Inst{25-21} = rs; 479263508Sdim let Inst{20-16} = funct; 480263508Sdim let Inst{15-0} = imm16; 481263508Sdim} 482243830Sdim//===----------------------------------------------------------------------===// 483263508Sdim// System calls format <op|code_|funct> 484263508Sdim//===----------------------------------------------------------------------===// 485263508Sdim 486263508Sdimclass SYS_FM<bits<6> funct> 487263508Sdim{ 488263508Sdim bits<20> code_; 489263508Sdim bits<32> Inst; 490263508Sdim let Inst{31-26} = 0x0; 491263508Sdim let Inst{25-6} = code_; 492263508Sdim let Inst{5-0} = funct; 493263508Sdim} 494263508Sdim 495263508Sdim//===----------------------------------------------------------------------===// 496263508Sdim// Break instruction format <op|code_1|funct> 497263508Sdim//===----------------------------------------------------------------------===// 498263508Sdim 499263508Sdimclass BRK_FM<bits<6> funct> 500263508Sdim{ 501263508Sdim bits<10> code_1; 502263508Sdim bits<10> code_2; 503263508Sdim bits<32> Inst; 504263508Sdim let Inst{31-26} = 0x0; 505263508Sdim let Inst{25-16} = code_1; 506263508Sdim let Inst{15-6} = code_2; 507263508Sdim let Inst{5-0} = funct; 508263508Sdim} 509263508Sdim 510263508Sdim//===----------------------------------------------------------------------===// 511263508Sdim// Exception return format <Cop0|1|0|funct> 512263508Sdim//===----------------------------------------------------------------------===// 513263508Sdim 514263508Sdimclass ER_FM<bits<6> funct> 515263508Sdim{ 516263508Sdim bits<32> Inst; 517263508Sdim let Inst{31-26} = 0x10; 518263508Sdim let Inst{25} = 1; 519263508Sdim let Inst{24-6} = 0; 520263508Sdim let Inst{5-0} = funct; 521263508Sdim} 522263508Sdim 523263508Sdim 524263508Sdim//===----------------------------------------------------------------------===// 525263508Sdim// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 526263508Sdim//===----------------------------------------------------------------------===// 527263508Sdim 528263508Sdimclass EI_FM<bits<1> sc> 529263508Sdim{ 530263508Sdim bits<32> Inst; 531263508Sdim bits<5> rt; 532263508Sdim let Inst{31-26} = 0x10; 533263508Sdim let Inst{25-21} = 0xb; 534263508Sdim let Inst{20-16} = rt; 535263508Sdim let Inst{15-11} = 0xc; 536263508Sdim let Inst{10-6} = 0; 537263508Sdim let Inst{5} = sc; 538263508Sdim let Inst{4-0} = 0; 539263508Sdim} 540263508Sdim 541263508Sdim//===----------------------------------------------------------------------===// 542193323Sed// 543193323Sed// FLOATING POINT INSTRUCTION FORMATS 544193323Sed// 545193323Sed// opcode - operation code. 546193323Sed// fs - src reg. 547193323Sed// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 548193323Sed// fd - dst reg, only used on 3 regs instr. 549193323Sed// fmt - double or single precision. 550193323Sed// funct - combined with opcode field give us an operation code. 551193323Sed// 552193323Sed//===----------------------------------------------------------------------===// 553193323Sed 554193323Sed//===----------------------------------------------------------------------===// 555193323Sed// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 556193323Sed//===----------------------------------------------------------------------===// 557193323Sed 558221345Sdimclass FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 559239462Sdim InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 560193323Sed{ 561193323Sed bits<5> ft; 562193323Sed bits<5> base; 563193323Sed bits<16> imm16; 564193323Sed 565228379Sdim let Opcode = op; 566193323Sed 567193323Sed let Inst{25-21} = base; 568221345Sdim let Inst{20-16} = ft; 569193323Sed let Inst{15-0} = imm16; 570193323Sed} 571193323Sed 572249423Sdimclass ADDS_FM<bits<6> funct, bits<5> fmt> { 573249423Sdim bits<5> fd; 574249423Sdim bits<5> fs; 575249423Sdim bits<5> ft; 576193323Sed 577249423Sdim bits<32> Inst; 578193323Sed 579249423Sdim let Inst{31-26} = 0x11; 580193323Sed let Inst{25-21} = fmt; 581221345Sdim let Inst{20-16} = ft; 582193323Sed let Inst{15-11} = fs; 583249423Sdim let Inst{10-6} = fd; 584249423Sdim let Inst{5-0} = funct; 585193323Sed} 586221345Sdim 587249423Sdimclass ABSS_FM<bits<6> funct, bits<5> fmt> { 588249423Sdim bits<5> fd; 589249423Sdim bits<5> fs; 590221345Sdim 591249423Sdim bits<32> Inst; 592221345Sdim 593249423Sdim let Inst{31-26} = 0x11; 594249423Sdim let Inst{25-21} = fmt; 595249423Sdim let Inst{20-16} = 0; 596249423Sdim let Inst{15-11} = fs; 597249423Sdim let Inst{10-6} = fd; 598249423Sdim let Inst{5-0} = funct; 599221345Sdim} 600221345Sdim 601249423Sdimclass MFC1_FM<bits<5> funct> { 602249423Sdim bits<5> rt; 603249423Sdim bits<5> fs; 604221345Sdim 605249423Sdim bits<32> Inst; 606221345Sdim 607249423Sdim let Inst{31-26} = 0x11; 608249423Sdim let Inst{25-21} = funct; 609249423Sdim let Inst{20-16} = rt; 610221345Sdim let Inst{15-11} = fs; 611249423Sdim let Inst{10-0} = 0; 612226633Sdim} 613226633Sdim 614251662Sdimclass LW_FM<bits<6> op> : StdArch { 615249423Sdim bits<5> rt; 616249423Sdim bits<21> addr; 617226633Sdim 618249423Sdim bits<32> Inst; 619249423Sdim 620249423Sdim let Inst{31-26} = op; 621249423Sdim let Inst{25-21} = addr{20-16}; 622249423Sdim let Inst{20-16} = rt; 623249423Sdim let Inst{15-0} = addr{15-0}; 624226633Sdim} 625226633Sdim 626249423Sdimclass MADDS_FM<bits<3> funct, bits<3> fmt> { 627234353Sdim bits<5> fd; 628234353Sdim bits<5> fr; 629234353Sdim bits<5> fs; 630234353Sdim bits<5> ft; 631234353Sdim 632249423Sdim bits<32> Inst; 633249423Sdim 634249423Sdim let Inst{31-26} = 0x13; 635234353Sdim let Inst{25-21} = fr; 636234353Sdim let Inst{20-16} = ft; 637234353Sdim let Inst{15-11} = fs; 638249423Sdim let Inst{10-6} = fd; 639249423Sdim let Inst{5-3} = funct; 640249423Sdim let Inst{2-0} = fmt; 641234353Sdim} 642234353Sdim 643249423Sdimclass LWXC1_FM<bits<6> funct> { 644249423Sdim bits<5> fd; 645249423Sdim bits<5> base; 646249423Sdim bits<5> index; 647234353Sdim 648249423Sdim bits<32> Inst; 649234353Sdim 650249423Sdim let Inst{31-26} = 0x13; 651234353Sdim let Inst{25-21} = base; 652234353Sdim let Inst{20-16} = index; 653249423Sdim let Inst{15-11} = 0; 654249423Sdim let Inst{10-6} = fd; 655249423Sdim let Inst{5-0} = funct; 656249423Sdim} 657249423Sdim 658249423Sdimclass SWXC1_FM<bits<6> funct> { 659249423Sdim bits<5> fs; 660249423Sdim bits<5> base; 661249423Sdim bits<5> index; 662249423Sdim 663249423Sdim bits<32> Inst; 664249423Sdim 665249423Sdim let Inst{31-26} = 0x13; 666249423Sdim let Inst{25-21} = base; 667249423Sdim let Inst{20-16} = index; 668234353Sdim let Inst{15-11} = fs; 669249423Sdim let Inst{10-6} = 0; 670249423Sdim let Inst{5-0} = funct; 671249423Sdim} 672249423Sdim 673249423Sdimclass BC1F_FM<bit nd, bit tf> { 674263508Sdim bits<3> fcc; 675249423Sdim bits<16> offset; 676249423Sdim 677249423Sdim bits<32> Inst; 678249423Sdim 679249423Sdim let Inst{31-26} = 0x11; 680249423Sdim let Inst{25-21} = 0x8; 681263508Sdim let Inst{20-18} = fcc; 682249423Sdim let Inst{17} = nd; 683249423Sdim let Inst{16} = tf; 684249423Sdim let Inst{15-0} = offset; 685249423Sdim} 686249423Sdim 687249423Sdimclass CEQS_FM<bits<5> fmt> { 688249423Sdim bits<5> fs; 689249423Sdim bits<5> ft; 690249423Sdim bits<4> cond; 691249423Sdim 692249423Sdim bits<32> Inst; 693249423Sdim 694249423Sdim let Inst{31-26} = 0x11; 695249423Sdim let Inst{25-21} = fmt; 696249423Sdim let Inst{20-16} = ft; 697249423Sdim let Inst{15-11} = fs; 698249423Sdim let Inst{10-8} = 0; // cc 699249423Sdim let Inst{7-4} = 0x3; 700249423Sdim let Inst{3-0} = cond; 701249423Sdim} 702249423Sdim 703263508Sdimclass C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 704263508Sdim let cond = c; 705263508Sdim} 706263508Sdim 707249423Sdimclass CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 708249423Sdim bits<5> fd; 709249423Sdim bits<5> fs; 710249423Sdim bits<5> rt; 711249423Sdim 712249423Sdim bits<32> Inst; 713249423Sdim 714249423Sdim let Inst{31-26} = 0x11; 715249423Sdim let Inst{25-21} = fmt; 716249423Sdim let Inst{20-16} = rt; 717249423Sdim let Inst{15-11} = fs; 718234353Sdim let Inst{10-6} = fd; 719234353Sdim let Inst{5-0} = funct; 720234353Sdim} 721249423Sdim 722263508Sdimclass CMov_F_I_FM<bit tf> : StdArch { 723249423Sdim bits<5> rd; 724249423Sdim bits<5> rs; 725263508Sdim bits<3> fcc; 726249423Sdim 727249423Sdim bits<32> Inst; 728249423Sdim 729249423Sdim let Inst{31-26} = 0; 730249423Sdim let Inst{25-21} = rs; 731263508Sdim let Inst{20-18} = fcc; 732249423Sdim let Inst{17} = 0; 733249423Sdim let Inst{16} = tf; 734249423Sdim let Inst{15-11} = rd; 735249423Sdim let Inst{10-6} = 0; 736249423Sdim let Inst{5-0} = 1; 737249423Sdim} 738249423Sdim 739249423Sdimclass CMov_F_F_FM<bits<5> fmt, bit tf> { 740249423Sdim bits<5> fd; 741249423Sdim bits<5> fs; 742263508Sdim bits<3> fcc; 743249423Sdim 744249423Sdim bits<32> Inst; 745249423Sdim 746249423Sdim let Inst{31-26} = 0x11; 747249423Sdim let Inst{25-21} = fmt; 748263508Sdim let Inst{20-18} = fcc; 749249423Sdim let Inst{17} = 0; 750249423Sdim let Inst{16} = tf; 751249423Sdim let Inst{15-11} = fs; 752249423Sdim let Inst{10-6} = fd; 753249423Sdim let Inst{5-0} = 0x11; 754249423Sdim} 755