1243789Sdim//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===// 2243789Sdim// 3243789Sdim// The LLVM Compiler Infrastructure 4243789Sdim// 5243789Sdim// This file is distributed under the University of Illinois Open Source 6243789Sdim// License. See LICENSE.TXT for details. 7243789Sdim// 8243789Sdim//===----------------------------------------------------------------------===// 9243789Sdim 10243789Sdimdef HasDSP : Predicate<"Subtarget.hasDSP()">, 11243789Sdim AssemblerPredicate<"FeatureDSP">; 12243789Sdimdef HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">, 13243789Sdim AssemblerPredicate<"FeatureDSPR2">; 14243789Sdim 15243789Sdim// Fields. 16243789Sdimclass Field6<bits<6> val> { 17243789Sdim bits<6> V = val; 18243789Sdim} 19243789Sdim 20243789Sdimdef SPECIAL3_OPCODE : Field6<0b011111>; 21243789Sdimdef REGIMM_OPCODE : Field6<0b000001>; 22243789Sdim 23243789Sdimclass DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> { 24243789Sdim let Predicates = [HasDSP]; 25243789Sdim} 26243789Sdim 27249423Sdimclass PseudoDSP<dag outs, dag ins, list<dag> pattern, 28249423Sdim InstrItinClass itin = IIPseudo>: 29249423Sdim MipsPseudo<outs, ins, pattern, itin> { 30243789Sdim let Predicates = [HasDSP]; 31243789Sdim} 32243789Sdim 33243789Sdim// ADDU.QB sub-class format. 34243789Sdimclass ADDU_QB_FMT<bits<5> op> : DSPInst { 35243789Sdim bits<5> rd; 36243789Sdim bits<5> rs; 37243789Sdim bits<5> rt; 38243789Sdim 39243789Sdim let Opcode = SPECIAL3_OPCODE.V; 40243789Sdim 41243789Sdim let Inst{25-21} = rs; 42243789Sdim let Inst{20-16} = rt; 43243789Sdim let Inst{15-11} = rd; 44243789Sdim let Inst{10-6} = op; 45243789Sdim let Inst{5-0} = 0b010000; 46243789Sdim} 47243789Sdim 48243789Sdimclass RADDU_W_QB_FMT<bits<5> op> : DSPInst { 49243789Sdim bits<5> rd; 50243789Sdim bits<5> rs; 51243789Sdim 52243789Sdim let Opcode = SPECIAL3_OPCODE.V; 53243789Sdim 54243789Sdim let Inst{25-21} = rs; 55243789Sdim let Inst{20-16} = 0; 56243789Sdim let Inst{15-11} = rd; 57243789Sdim let Inst{10-6} = op; 58243789Sdim let Inst{5-0} = 0b010000; 59243789Sdim} 60243789Sdim 61243789Sdim// CMPU.EQ.QB sub-class format. 62243789Sdimclass CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst { 63243789Sdim bits<5> rs; 64243789Sdim bits<5> rt; 65243789Sdim 66243789Sdim let Opcode = SPECIAL3_OPCODE.V; 67243789Sdim 68243789Sdim let Inst{25-21} = rs; 69243789Sdim let Inst{20-16} = rt; 70243789Sdim let Inst{15-11} = 0; 71243789Sdim let Inst{10-6} = op; 72243789Sdim let Inst{5-0} = 0b010001; 73243789Sdim} 74243789Sdim 75243789Sdimclass CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst { 76243789Sdim bits<5> rs; 77243789Sdim bits<5> rt; 78243789Sdim bits<5> rd; 79243789Sdim 80243789Sdim let Opcode = SPECIAL3_OPCODE.V; 81243789Sdim 82243789Sdim let Inst{25-21} = rs; 83243789Sdim let Inst{20-16} = rt; 84243789Sdim let Inst{15-11} = rd; 85243789Sdim let Inst{10-6} = op; 86243789Sdim let Inst{5-0} = 0b010001; 87243789Sdim} 88243789Sdim 89243789Sdimclass PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst { 90243789Sdim bits<5> rs; 91243789Sdim bits<5> rt; 92243789Sdim bits<5> sa; 93243789Sdim 94243789Sdim let Opcode = SPECIAL3_OPCODE.V; 95243789Sdim 96243789Sdim let Inst{25-21} = rs; 97243789Sdim let Inst{20-16} = rt; 98243789Sdim let Inst{15-11} = sa; 99243789Sdim let Inst{10-6} = op; 100243789Sdim let Inst{5-0} = 0b010001; 101243789Sdim} 102243789Sdim 103243789Sdim// ABSQ_S.PH sub-class format. 104243789Sdimclass ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst { 105243789Sdim bits<5> rd; 106243789Sdim bits<5> rt; 107243789Sdim 108243789Sdim let Opcode = SPECIAL3_OPCODE.V; 109243789Sdim 110243789Sdim let Inst{25-21} = 0; 111243789Sdim let Inst{20-16} = rt; 112243789Sdim let Inst{15-11} = rd; 113243789Sdim let Inst{10-6} = op; 114243789Sdim let Inst{5-0} = 0b010010; 115243789Sdim} 116243789Sdim 117243789Sdim 118243789Sdimclass REPL_FMT<bits<5> op> : DSPInst { 119243789Sdim bits<5> rd; 120243789Sdim bits<10> imm; 121243789Sdim 122243789Sdim let Opcode = SPECIAL3_OPCODE.V; 123243789Sdim 124243789Sdim let Inst{25-16} = imm; 125243789Sdim let Inst{15-11} = rd; 126243789Sdim let Inst{10-6} = op; 127243789Sdim let Inst{5-0} = 0b010010; 128243789Sdim} 129243789Sdim 130243789Sdim// SHLL.QB sub-class format. 131243789Sdimclass SHLL_QB_FMT<bits<5> op> : DSPInst { 132243789Sdim bits<5> rd; 133243789Sdim bits<5> rt; 134243789Sdim bits<5> rs_sa; 135243789Sdim 136243789Sdim let Opcode = SPECIAL3_OPCODE.V; 137243789Sdim 138243789Sdim let Inst{25-21} = rs_sa; 139243789Sdim let Inst{20-16} = rt; 140243789Sdim let Inst{15-11} = rd; 141243789Sdim let Inst{10-6} = op; 142243789Sdim let Inst{5-0} = 0b010011; 143243789Sdim} 144243789Sdim 145243789Sdim// LX sub-class format. 146243789Sdimclass LX_FMT<bits<5> op> : DSPInst { 147243789Sdim bits<5> rd; 148243789Sdim bits<5> base; 149243789Sdim bits<5> index; 150243789Sdim 151243789Sdim let Opcode = SPECIAL3_OPCODE.V; 152243789Sdim 153243789Sdim let Inst{25-21} = base; 154243789Sdim let Inst{20-16} = index; 155243789Sdim let Inst{15-11} = rd; 156243789Sdim let Inst{10-6} = op; 157243789Sdim let Inst{5-0} = 0b001010; 158243789Sdim} 159243789Sdim 160243789Sdim// ADDUH.QB sub-class format. 161243789Sdimclass ADDUH_QB_FMT<bits<5> op> : DSPInst { 162243789Sdim bits<5> rd; 163243789Sdim bits<5> rs; 164243789Sdim bits<5> rt; 165243789Sdim 166243789Sdim let Opcode = SPECIAL3_OPCODE.V; 167243789Sdim 168243789Sdim let Inst{25-21} = rs; 169243789Sdim let Inst{20-16} = rt; 170243789Sdim let Inst{15-11} = rd; 171243789Sdim let Inst{10-6} = op; 172243789Sdim let Inst{5-0} = 0b011000; 173243789Sdim} 174243789Sdim 175243789Sdim// APPEND sub-class format. 176243789Sdimclass APPEND_FMT<bits<5> op> : DSPInst { 177243789Sdim bits<5> rt; 178243789Sdim bits<5> rs; 179243789Sdim bits<5> sa; 180243789Sdim 181243789Sdim let Opcode = SPECIAL3_OPCODE.V; 182243789Sdim 183243789Sdim let Inst{25-21} = rs; 184243789Sdim let Inst{20-16} = rt; 185243789Sdim let Inst{15-11} = sa; 186243789Sdim let Inst{10-6} = op; 187243789Sdim let Inst{5-0} = 0b110001; 188243789Sdim} 189243789Sdim 190243789Sdim// DPA.W.PH sub-class format. 191243789Sdimclass DPA_W_PH_FMT<bits<5> op> : DSPInst { 192243789Sdim bits<2> ac; 193243789Sdim bits<5> rs; 194243789Sdim bits<5> rt; 195243789Sdim 196243789Sdim let Opcode = SPECIAL3_OPCODE.V; 197243789Sdim 198243789Sdim let Inst{25-21} = rs; 199243789Sdim let Inst{20-16} = rt; 200243789Sdim let Inst{15-13} = 0; 201243789Sdim let Inst{12-11} = ac; 202243789Sdim let Inst{10-6} = op; 203243789Sdim let Inst{5-0} = 0b110000; 204243789Sdim} 205243789Sdim 206243789Sdim// MULT sub-class format. 207243789Sdimclass MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst { 208243789Sdim bits<2> ac; 209243789Sdim bits<5> rs; 210243789Sdim bits<5> rt; 211243789Sdim 212243789Sdim let Opcode = opcode; 213243789Sdim 214243789Sdim let Inst{25-21} = rs; 215243789Sdim let Inst{20-16} = rt; 216243789Sdim let Inst{15-13} = 0; 217243789Sdim let Inst{12-11} = ac; 218243789Sdim let Inst{10-6} = 0; 219243789Sdim let Inst{5-0} = funct; 220243789Sdim} 221243789Sdim 222251662Sdim// MFHI sub-class format. 223251662Sdimclass MFHI_FMT<bits<6> funct> : DSPInst { 224251662Sdim bits<5> rd; 225251662Sdim bits<2> ac; 226251662Sdim 227251662Sdim let Inst{31-26} = 0; 228251662Sdim let Inst{25-23} = 0; 229251662Sdim let Inst{22-21} = ac; 230251662Sdim let Inst{20-16} = 0; 231251662Sdim let Inst{15-11} = rd; 232251662Sdim let Inst{10-6} = 0; 233251662Sdim let Inst{5-0} = funct; 234251662Sdim} 235251662Sdim 236251662Sdim// MTHI sub-class format. 237251662Sdimclass MTHI_FMT<bits<6> funct> : DSPInst { 238251662Sdim bits<5> rs; 239251662Sdim bits<2> ac; 240251662Sdim 241251662Sdim let Inst{31-26} = 0; 242251662Sdim let Inst{25-21} = rs; 243251662Sdim let Inst{20-13} = 0; 244251662Sdim let Inst{12-11} = ac; 245251662Sdim let Inst{10-6} = 0; 246251662Sdim let Inst{5-0} = funct; 247251662Sdim} 248251662Sdim 249243789Sdim// EXTR.W sub-class format (type 1). 250243789Sdimclass EXTR_W_TY1_FMT<bits<5> op> : DSPInst { 251243789Sdim bits<5> rt; 252243789Sdim bits<2> ac; 253243789Sdim bits<5> shift_rs; 254243789Sdim 255243789Sdim let Opcode = SPECIAL3_OPCODE.V; 256243789Sdim 257243789Sdim let Inst{25-21} = shift_rs; 258243789Sdim let Inst{20-16} = rt; 259243789Sdim let Inst{15-13} = 0; 260243789Sdim let Inst{12-11} = ac; 261243789Sdim let Inst{10-6} = op; 262243789Sdim let Inst{5-0} = 0b111000; 263243789Sdim} 264243789Sdim 265243789Sdim// SHILO sub-class format. 266243789Sdimclass SHILO_R1_FMT<bits<5> op> : DSPInst { 267243789Sdim bits<2> ac; 268243789Sdim bits<6> shift; 269243789Sdim 270243789Sdim let Opcode = SPECIAL3_OPCODE.V; 271243789Sdim 272243789Sdim let Inst{25-20} = shift; 273243789Sdim let Inst{19-13} = 0; 274243789Sdim let Inst{12-11} = ac; 275243789Sdim let Inst{10-6} = op; 276243789Sdim let Inst{5-0} = 0b111000; 277243789Sdim} 278243789Sdim 279243789Sdimclass SHILO_R2_FMT<bits<5> op> : DSPInst { 280243789Sdim bits<2> ac; 281243789Sdim bits<5> rs; 282243789Sdim 283243789Sdim let Opcode = SPECIAL3_OPCODE.V; 284243789Sdim 285243789Sdim let Inst{25-21} = rs; 286243789Sdim let Inst{20-13} = 0; 287243789Sdim let Inst{12-11} = ac; 288243789Sdim let Inst{10-6} = op; 289243789Sdim let Inst{5-0} = 0b111000; 290243789Sdim} 291243789Sdim 292243789Sdimclass RDDSP_FMT<bits<5> op> : DSPInst { 293243789Sdim bits<5> rd; 294243789Sdim bits<10> mask; 295243789Sdim 296243789Sdim let Opcode = SPECIAL3_OPCODE.V; 297243789Sdim 298243789Sdim let Inst{25-16} = mask; 299243789Sdim let Inst{15-11} = rd; 300243789Sdim let Inst{10-6} = op; 301243789Sdim let Inst{5-0} = 0b111000; 302243789Sdim} 303243789Sdim 304243789Sdimclass WRDSP_FMT<bits<5> op> : DSPInst { 305243789Sdim bits<5> rs; 306243789Sdim bits<10> mask; 307243789Sdim 308243789Sdim let Opcode = SPECIAL3_OPCODE.V; 309243789Sdim 310243789Sdim let Inst{25-21} = rs; 311243789Sdim let Inst{20-11} = mask; 312243789Sdim let Inst{10-6} = op; 313243789Sdim let Inst{5-0} = 0b111000; 314243789Sdim} 315243789Sdim 316243789Sdimclass BPOSGE32_FMT<bits<5> op> : DSPInst { 317243789Sdim bits<16> offset; 318243789Sdim 319243789Sdim let Opcode = REGIMM_OPCODE.V; 320243789Sdim 321243789Sdim let Inst{25-21} = 0; 322243789Sdim let Inst{20-16} = op; 323243789Sdim let Inst{15-0} = offset; 324243789Sdim} 325243789Sdim 326243789Sdim// INSV sub-class format. 327243789Sdimclass INSV_FMT<bits<6> op> : DSPInst { 328243789Sdim bits<5> rt; 329243789Sdim bits<5> rs; 330243789Sdim 331243789Sdim let Opcode = SPECIAL3_OPCODE.V; 332243789Sdim 333243789Sdim let Inst{25-21} = rs; 334243789Sdim let Inst{20-16} = rt; 335243789Sdim let Inst{15-6} = 0; 336243789Sdim let Inst{5-0} = op; 337243789Sdim} 338