1234353Sdim//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2221345Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7221345Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// This describes the calling conventions for Mips architecture. 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed 12193323Sed/// CCIfSubtarget - Match if the current subtarget has a feature F. 13221345Sdimclass CCIfSubtarget<string F, CCAction A>: 14193323Sed CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; 15193323Sed 16193323Sed//===----------------------------------------------------------------------===// 17193323Sed// Mips O32 Calling Convention 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed 20221345Sdim// Only the return rules are defined here for O32. The rules for argument 21193323Sed// passing are defined in MipsISelLowering.cpp. 22193323Seddef RetCC_MipsO32 : CallingConv<[ 23224145Sdim // i32 are returned in registers V0, V1, A0, A1 24224145Sdim CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 25193323Sed 26202878Srdivacky // f32 are returned in registers F0, F2 27202878Srdivacky CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 28193323Sed 29263508Sdim // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or 30263508Sdim // in D0 and D1 in FP32bit mode. 31263508Sdim CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>, 32263508Sdim CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>> 33193323Sed]>; 34193323Sed 35193323Sed//===----------------------------------------------------------------------===// 36226633Sdim// Mips N32/64 Calling Convention 37226633Sdim//===----------------------------------------------------------------------===// 38226633Sdim 39226633Sdimdef CC_MipsN : CallingConv<[ 40234353Sdim // Promote i8/i16 arguments to i32. 41234353Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 42226633Sdim 43226633Sdim // Integer arguments are passed in integer registers. 44234353Sdim CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3, 45234353Sdim T0, T1, T2, T3], 46234353Sdim [F12, F13, F14, F15, 47234353Sdim F16, F17, F18, F19]>>, 48234353Sdim 49226633Sdim CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 50226633Sdim T0_64, T1_64, T2_64, T3_64], 51226633Sdim [D12_64, D13_64, D14_64, D15_64, 52226633Sdim D16_64, D17_64, D18_64, D19_64]>>, 53226633Sdim 54226633Sdim // f32 arguments are passed in single precision FP registers. 55226633Sdim CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 56226633Sdim F16, F17, F18, F19], 57226633Sdim [A0_64, A1_64, A2_64, A3_64, 58226633Sdim T0_64, T1_64, T2_64, T3_64]>>, 59226633Sdim 60226633Sdim // f64 arguments are passed in double precision FP registers. 61226633Sdim CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 62226633Sdim D16_64, D17_64, D18_64, D19_64], 63226633Sdim [A0_64, A1_64, A2_64, A3_64, 64226633Sdim T0_64, T1_64, T2_64, T3_64]>>, 65226633Sdim 66226633Sdim // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 67234353Sdim CCIfType<[i32, f32], CCAssignToStack<4, 8>>, 68234353Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 69226633Sdim]>; 70226633Sdim 71234353Sdim// N32/64 variable arguments. 72234353Sdim// All arguments are passed in integer registers. 73234353Sdimdef CC_MipsN_VarArg : CallingConv<[ 74234353Sdim // Promote i8/i16 arguments to i32. 75234353Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 76234353Sdim 77234353Sdim CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 78234353Sdim 79234353Sdim CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 80234353Sdim T0_64, T1_64, T2_64, T3_64]>>, 81234353Sdim 82234353Sdim // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 83234353Sdim CCIfType<[i32, f32], CCAssignToStack<4, 8>>, 84234353Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 85234353Sdim]>; 86234353Sdim 87226633Sdimdef RetCC_MipsN : CallingConv<[ 88226633Sdim // i32 are returned in registers V0, V1 89226633Sdim CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 90226633Sdim 91226633Sdim // i64 are returned in registers V0_64, V1_64 92226633Sdim CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 93226633Sdim 94226633Sdim // f32 are returned in registers F0, F2 95226633Sdim CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 96226633Sdim 97226633Sdim // f64 are returned in registers D0, D2 98226633Sdim CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 99226633Sdim]>; 100226633Sdim 101249423Sdim// In soft-mode, register A0_64, instead of V1_64, is used to return a long 102249423Sdim// double value. 103249423Sdimdef RetCC_F128Soft : CallingConv<[ 104249423Sdim CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>> 105249423Sdim]>; 106249423Sdim 107226633Sdim//===----------------------------------------------------------------------===// 108193323Sed// Mips EABI Calling Convention 109193323Sed//===----------------------------------------------------------------------===// 110193323Sed 111193323Seddef CC_MipsEABI : CallingConv<[ 112193323Sed // Promote i8/i16 arguments to i32. 113193323Sed CCIfType<[i8, i16], CCPromoteToType<i32>>, 114193323Sed 115193323Sed // Integer arguments are passed in integer registers. 116193323Sed CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 117193323Sed 118221345Sdim // Single fp arguments are passed in pairs within 32-bit mode 119221345Sdim CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", 120193323Sed CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, 121193323Sed 122221345Sdim CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()", 123193323Sed CCAssignToReg<[F12, F14, F16, F18]>>>, 124193323Sed 125221345Sdim // The first 4 double fp arguments are passed in single fp registers. 126221345Sdim CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", 127193323Sed CCAssignToReg<[D6, D7, D8, D9]>>>, 128193323Sed 129193323Sed // Integer values get stored in stack slots that are 4 bytes in 130193323Sed // size and 4-byte aligned. 131193323Sed CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 132193323Sed 133193323Sed // Integer values get stored in stack slots that are 8 bytes in 134193323Sed // size and 8-byte aligned. 135193323Sed CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>> 136193323Sed]>; 137193323Sed 138193323Seddef RetCC_MipsEABI : CallingConv<[ 139193323Sed // i32 are returned in registers V0, V1 140193323Sed CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 141193323Sed 142193323Sed // f32 are returned in registers F0, F1 143193323Sed CCIfType<[f32], CCAssignToReg<[F0, F1]>>, 144193323Sed 145193323Sed // f64 are returned in register D0 146193323Sed CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> 147193323Sed]>; 148193323Sed 149193323Sed//===----------------------------------------------------------------------===// 150239462Sdim// Mips FastCC Calling Convention 151239462Sdim//===----------------------------------------------------------------------===// 152239462Sdimdef CC_MipsO32_FastCC : CallingConv<[ 153239462Sdim // f64 arguments are passed in double-precision floating pointer registers. 154263508Sdim CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", 155263508Sdim CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, 156263508Sdim D8, D9]>>>, 157263508Sdim CCIfType<[f64], CCIfSubtarget<"isFP64bit()", 158263508Sdim CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 159263508Sdim D4_64, D5_64, D6_64, D7_64, 160263508Sdim D8_64, D9_64, D10_64, D11_64, 161263508Sdim D12_64, D13_64, D14_64, D15_64, 162263508Sdim D16_64, D17_64, D18_64, 163263508Sdim D19_64]>>>, 164239462Sdim 165239462Sdim // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 166239462Sdim CCIfType<[f64], CCAssignToStack<8, 8>> 167239462Sdim]>; 168239462Sdim 169239462Sdimdef CC_MipsN_FastCC : CallingConv<[ 170239462Sdim // Integer arguments are passed in integer registers. 171239462Sdim CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 172239462Sdim T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 173239462Sdim T8_64, V1_64]>>, 174239462Sdim 175239462Sdim // f64 arguments are passed in double-precision floating pointer registers. 176239462Sdim CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 177239462Sdim D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 178239462Sdim D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 179239462Sdim D18_64, D19_64]>>, 180239462Sdim 181239462Sdim // Stack parameter slots for i64 and f64 are 64-bit doublewords and 182239462Sdim // 8-byte aligned. 183239462Sdim CCIfType<[i64, f64], CCAssignToStack<8, 8>> 184239462Sdim]>; 185239462Sdim 186239462Sdimdef CC_Mips_FastCC : CallingConv<[ 187239462Sdim // Handles byval parameters. 188239462Sdim CCIfByVal<CCPassByVal<4, 4>>, 189239462Sdim 190239462Sdim // Promote i8/i16 arguments to i32. 191239462Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 192239462Sdim 193239462Sdim // Integer arguments are passed in integer registers. All scratch registers, 194239462Sdim // except for AT, V0 and T9, are available to be used as argument registers. 195239462Sdim CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, 196239462Sdim T7, T8, V1]>>, 197239462Sdim 198239462Sdim // f32 arguments are passed in single-precision floating pointer registers. 199239462Sdim CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, 200239462Sdim F11, F12, F13, F14, F15, F16, F17, F18, F19]>>, 201239462Sdim 202239462Sdim // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 203239462Sdim CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 204239462Sdim 205239462Sdim CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 206239462Sdim CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 207239462Sdim CCDelegateTo<CC_MipsN_FastCC> 208239462Sdim]>; 209239462Sdim 210263508Sdim//== 211263508Sdim 212263508Sdimdef CC_Mips16RetHelper : CallingConv<[ 213263508Sdim // Integer arguments are passed in integer registers. 214263508Sdim CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 215263508Sdim]>; 216263508Sdim 217239462Sdim//===----------------------------------------------------------------------===// 218193323Sed// Mips Calling Convention Dispatch 219193323Sed//===----------------------------------------------------------------------===// 220193323Sed 221193323Seddef RetCC_Mips : CallingConv<[ 222193323Sed CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>, 223226633Sdim CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 224226633Sdim CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 225193323Sed CCDelegateTo<RetCC_MipsO32> 226193323Sed]>; 227234353Sdim 228234353Sdim//===----------------------------------------------------------------------===// 229234353Sdim// Callee-saved register lists. 230234353Sdim//===----------------------------------------------------------------------===// 231234353Sdim 232234353Sdimdef CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 233234353Sdim (sequence "S%u", 7, 0))>; 234234353Sdim 235234353Sdimdef CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 236234353Sdim (sequence "S%u", 7, 0))>; 237234353Sdim 238263508Sdimdef CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP, 239263508Sdim (sequence "S%u", 7, 0))>; 240263508Sdim 241234353Sdimdef CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64, 242234353Sdim D23_64, D22_64, D21_64, RA_64, FP_64, GP_64, 243234353Sdim (sequence "S%u_64", 7, 0))>; 244234353Sdim 245234353Sdimdef CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 246234353Sdim GP_64, (sequence "S%u_64", 7, 0))>; 247263508Sdim 248263508Sdimdef CSR_Mips16RetHelper : 249263508Sdim CalleeSavedRegs<(add V0, V1, (sequence "A%u", 3, 0), S0, S1)>; 250