Mips16InstrInfo.td revision 263508
1//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips16 instructions. 11// 12//===----------------------------------------------------------------------===// 13// 14// 15// Mips Address 16// 17def addr16 : 18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>; 19 20// 21// Address operand 22def mem16 : Operand<i32> { 23 let PrintMethod = "printMemOperand"; 24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP); 25 let EncoderMethod = "getMemEncoding"; 26} 27 28def mem16_ea : Operand<i32> { 29 let PrintMethod = "printMemOperandEA"; 30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16); 31 let EncoderMethod = "getMemEncoding"; 32} 33 34// 35// I-type instruction format 36// 37// this is only used by bimm. the actual assembly value is a 12 bit signed 38// number 39// 40class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>: 41 FI16<op, (outs), (ins brtarget:$imm16), 42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>; 43 44// 45// 46// I8 instruction format 47// 48 49class FI816_ins_base<bits<3> _func, string asmstr, 50 string asmstr2, InstrItinClass itin>: 51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 52 [], itin>; 53 54class FI816_ins<bits<3> _func, string asmstr, 55 InstrItinClass itin>: 56 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>; 57 58class FI816_SP_ins<bits<3> _func, string asmstr, 59 InstrItinClass itin>: 60 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>; 61 62// 63// RI instruction format 64// 65 66 67class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2, 68 InstrItinClass itin>: 69 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm), 70 !strconcat(asmstr, asmstr2), [], itin>; 71 72class FRI16_ins<bits<5> op, string asmstr, 73 InstrItinClass itin>: 74 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 75 76class FRI16_TCP_ins<bits<5> _op, string asmstr, 77 InstrItinClass itin>: 78 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size), 79 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>; 80 81class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2, 82 InstrItinClass itin>: 83 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm), 84 !strconcat(asmstr, asmstr2), [], itin>; 85 86class FRI16R_ins<bits<5> op, string asmstr, 87 InstrItinClass itin>: 88 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>; 89 90class F2RI16_ins<bits<5> _op, string asmstr, 91 InstrItinClass itin>: 92 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 93 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { 94 let Constraints = "$rx_ = $rx"; 95} 96 97class FRI16_B_ins<bits<5> _op, string asmstr, 98 InstrItinClass itin>: 99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 100 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>; 101// 102// Compare a register and immediate and place result in CC 103// Implicit use of T8 104// 105// EXT-CCRR Instruction format 106// 107class FEXT_CCRXI16_ins<string asmstr>: 108 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), 109 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> { 110 let isCodeGenOnly=1; 111 let usesCustomInserter = 1; 112} 113 114// JAL and JALX instruction format 115// 116class FJAL16_ins<bits<1> _X, string asmstr, 117 InstrItinClass itin>: 118 FJAL16<_X, (outs), (ins simm20:$imm), 119 !strconcat(asmstr, "\t$imm\n\tnop"),[], 120 itin> { 121 let isCodeGenOnly=1; 122} 123// 124// EXT-I instruction format 125// 126class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> : 127 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 128 !strconcat(asmstr, "\t$imm16"),[], itin>; 129 130// 131// EXT-I8 instruction format 132// 133 134class FEXT_I816_ins_base<bits<3> _func, string asmstr, 135 string asmstr2, InstrItinClass itin>: 136 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2), 137 [], itin>; 138 139class FEXT_I816_ins<bits<3> _func, string asmstr, 140 InstrItinClass itin>: 141 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>; 142 143class FEXT_I816_SP_ins<bits<3> _func, string asmstr, 144 InstrItinClass itin>: 145 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>; 146 147// 148// Assembler formats in alphabetical order. 149// Natural and pseudos are mixed together. 150// 151// Compare two registers and place result in CC 152// Implicit use of T8 153// 154// CC-RR Instruction format 155// 156class FCCRR16_ins<string asmstr> : 157 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), 158 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> { 159 let isCodeGenOnly=1; 160 let usesCustomInserter = 1; 161} 162 163// 164// EXT-RI instruction format 165// 166 167class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2, 168 InstrItinClass itin>: 169 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm), 170 !strconcat(asmstr, asmstr2), [], itin>; 171 172class FEXT_RI16_ins<bits<5> _op, string asmstr, 173 InstrItinClass itin>: 174 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 175 176class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2, 177 InstrItinClass itin>: 178 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm), 179 !strconcat(asmstr, asmstr2), [], itin>; 180 181class FEXT_RI16R_ins<bits<5> _op, string asmstr, 182 InstrItinClass itin>: 183 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>; 184 185class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>: 186 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>; 187 188class FEXT_RI16_B_ins<bits<5> _op, string asmstr, 189 InstrItinClass itin>: 190 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm), 191 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 192 193class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr, 194 InstrItinClass itin>: 195 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size), 196 !strconcat(asmstr, "\t$rx, $imm"), [], itin>; 197 198class FEXT_2RI16_ins<bits<5> _op, string asmstr, 199 InstrItinClass itin>: 200 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), 201 !strconcat(asmstr, "\t$rx, $imm"), [], itin> { 202 let Constraints = "$rx_ = $rx"; 203} 204 205 206// this has an explicit sp argument that we ignore to work around a problem 207// in the compiler 208class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr, 209 InstrItinClass itin>: 210 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm), 211 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 212 213class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr, 214 InstrItinClass itin>: 215 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm), 216 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>; 217 218// 219// EXT-RRI instruction format 220// 221 222class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd, 223 InstrItinClass itin>: 224 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 225 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 226 227class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd, 228 InstrItinClass itin>: 229 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr), 230 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 231 232// 233// 234// EXT-RRI-A instruction format 235// 236 237class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd, 238 InstrItinClass itin>: 239 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr), 240 !strconcat(asmstr, "\t$ry, $addr"), [], itin>; 241 242// 243// EXT-SHIFT instruction format 244// 245class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>: 246 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa), 247 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>; 248 249// 250// EXT-T8I8 251// 252class FEXT_T8I816_ins<string asmstr, string asmstr2>: 253 MipsPseudo16<(outs), 254 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), 255 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", 256 !strconcat(asmstr, "\t$imm"))),[]> { 257 let isCodeGenOnly=1; 258 let usesCustomInserter = 1; 259} 260 261// 262// EXT-T8I8I 263// 264class FEXT_T8I8I16_ins<string asmstr, string asmstr2>: 265 MipsPseudo16<(outs), 266 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), 267 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", 268 !strconcat(asmstr, "\t$targ"))), []> { 269 let isCodeGenOnly=1; 270 let usesCustomInserter = 1; 271} 272// 273 274 275// 276// I8_MOVR32 instruction format (used only by the MOVR32 instructio 277// 278class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>: 279 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32), 280 !strconcat(asmstr, "\t$rz, $r32"), [], itin>; 281 282// 283// I8_MOV32R instruction format (used only by MOV32R instruction) 284// 285 286class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>: 287 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz), 288 !strconcat(asmstr, "\t$r32, $rz"), [], itin>; 289 290// 291// This are pseudo formats for multiply 292// This first one can be changed to non pseudo now. 293// 294// MULT 295// 296class FMULT16_ins<string asmstr, InstrItinClass itin> : 297 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 298 !strconcat(asmstr, "\t$rx, $ry"), []>; 299 300// 301// MULT-LO 302// 303class FMULT16_LO_ins<string asmstr, InstrItinClass itin> : 304 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 305 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> { 306 let isCodeGenOnly=1; 307} 308 309// 310// RR-type instruction format 311// 312 313class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 314 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 315 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 316} 317 318class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> : 319 FRRBreak16<(outs), (ins), asmstr, [], itin> { 320 let Code=0; 321} 322 323class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> : 324 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry), 325 !strconcat(asmstr, "\t$rx, $ry"), [], itin> { 326} 327 328class FRRTR16_ins<string asmstr> : 329 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 330 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ; 331 332// 333// maybe refactor but need a $zero as a dummy first parameter 334// 335class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> : 336 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry), 337 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ; 338 339class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : 340 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry), 341 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ; 342 343 344class FRR16_M_ins<bits<5> f, string asmstr, 345 InstrItinClass itin> : 346 FRR16<f, (outs CPU16Regs:$rx), (ins), 347 !strconcat(asmstr, "\t$rx"), [], itin>; 348 349class FRxRxRy16_ins<bits<5> f, string asmstr, 350 InstrItinClass itin> : 351 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 352 !strconcat(asmstr, "\t$rz, $ry"), 353 [], itin> { 354 let Constraints = "$rx = $rz"; 355} 356 357let rx=0 in 358class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_, 359 string asmstr, InstrItinClass itin>: 360 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"), 361 [], itin> ; 362 363 364class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra, 365 string asmstr, InstrItinClass itin>: 366 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 367 !strconcat(asmstr, "\t $rx"), [], itin> ; 368 369class FRR_SF16_ins 370 <bits<5> _funct, bits<3> _subfunc, 371 string asmstr, InstrItinClass itin>: 372 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_), 373 !strconcat(asmstr, "\t $rx"), 374 [], itin> { 375 let Constraints = "$rx_ = $rx"; 376 } 377// 378// RRR-type instruction format 379// 380 381class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> : 382 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 383 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>; 384 385// 386// These Sel patterns support the generation of conditional move 387// pseudo instructions. 388// 389// The nomenclature uses the components making up the pseudo and may 390// be a bit counter intuitive when compared with the end result we seek. 391// For example using a bqez in the example directly below results in the 392// conditional move being done if the tested register is not zero. 393// I considered in easier to check by keeping the pseudo consistent with 394// it's components but it could have been done differently. 395// 396// The simplest case is when can test and operand directly and do the 397// conditional move based on a simple mips16 conditional 398// branch instruction. 399// for example: 400// if $op == beqz or bnez: 401// 402// $op1 $rt, .+4 403// move $rd, $rs 404// 405// if $op == beqz, then if $rt != 0, then the conditional assignment 406// $rd = $rs is done. 407 408// if $op == bnez, then if $rt == 0, then the conditional assignment 409// $rd = $rs is done. 410// 411// So this pseudo class only has one operand, i.e. op 412// 413class Sel<string op>: 414 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 415 CPU16Regs:$rt), 416 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> { 417 //let isCodeGenOnly=1; 418 let Constraints = "$rd = $rd_"; 419 let usesCustomInserter = 1; 420} 421 422// 423// The next two instruction classes allow for an operand which tests 424// two operands and returns a value in register T8 and 425//then does a conditional branch based on the value of T8 426// 427 428// op2 can be cmpi or slti/sltiu 429// op1 can bteqz or btnez 430// the operands for op2 are a register and a signed constant 431// 432// $op2 $t, $imm ;test register t and branch conditionally 433// $op1 .+4 ;op1 is a conditional branch 434// move $rd, $rs 435// 436// 437class SeliT<string op1, string op2>: 438 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, 439 CPU16Regs:$rl, simm16:$imm), 440 !strconcat(op2, 441 !strconcat("\t$rl, $imm\n\t", 442 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 443 let isCodeGenOnly=1; 444 let Constraints = "$rd = $rd_"; 445 let usesCustomInserter = 1; 446} 447 448// 449// op2 can be cmp or slt/sltu 450// op1 can be bteqz or btnez 451// the operands for op2 are two registers 452// op1 is a conditional branch 453// 454// 455// $op2 $rl, $rr ;test registers rl,rr 456// $op1 .+4 ;op2 is a conditional branch 457// move $rd, $rs 458// 459// 460class SelT<string op1, string op2>: 461 MipsPseudo16<(outs CPU16Regs:$rd_), 462 (ins CPU16Regs:$rd, CPU16Regs:$rs, 463 CPU16Regs:$rl, CPU16Regs:$rr), 464 !strconcat(op2, 465 !strconcat("\t$rl, $rr\n\t", 466 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { 467 let isCodeGenOnly=1; 468 let Constraints = "$rd = $rd_"; 469 let usesCustomInserter = 1; 470} 471 472// 473// 32 bit constant 474// 475def imm32: Operand<i32>; 476 477def Constant32: 478 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; 479 480def LwConstant32: 481 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid), 482 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; 483 484 485// 486// Some general instruction class info 487// 488// 489 490class ArithLogic16Defs<bit isCom=0> { 491 bits<5> shamt = 0; 492 bit isCommutable = isCom; 493 bit isReMaterializable = 1; 494 bit neverHasSideEffects = 1; 495} 496 497class branch16 { 498 bit isBranch = 1; 499 bit isTerminator = 1; 500 bit isBarrier = 1; 501} 502 503class cbranch16 { 504 bit isBranch = 1; 505 bit isTerminator = 1; 506} 507 508class MayLoad { 509 bit mayLoad = 1; 510} 511 512class MayStore { 513 bit mayStore = 1; 514} 515// 516 517 518// Format: ADDIU rx, immediate MIPS16e 519// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) 520// To add a constant to a 32-bit integer. 521// 522def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; 523 524def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, 525 ArithLogic16Defs<0> { 526 let AddedComplexity = 5; 527} 528def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, 529 ArithLogic16Defs<0> { 530 let isCodeGenOnly = 1; 531} 532 533def AddiuRxRyOffMemX16: 534 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>; 535 536// 537 538// Format: ADDIU rx, pc, immediate MIPS16e 539// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended) 540// To add a constant to the program counter. 541// 542def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>; 543 544// 545// Format: ADDIU sp, immediate MIPS16e 546// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended) 547// To add a constant to the stack pointer. 548// 549def AddiuSpImm16 550 : FI816_SP_ins<0b011, "addiu", IIAlu> { 551 let Defs = [SP]; 552 let Uses = [SP]; 553 let AddedComplexity = 5; 554} 555 556def AddiuSpImmX16 557 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { 558 let Defs = [SP]; 559 let Uses = [SP]; 560} 561 562// 563// Format: ADDU rz, rx, ry MIPS16e 564// Purpose: Add Unsigned Word (3-Operand) 565// To add 32-bit integers. 566// 567 568def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>; 569 570// 571// Format: AND rx, ry MIPS16e 572// Purpose: AND 573// To do a bitwise logical AND. 574 575def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>; 576 577 578// 579// Format: BEQZ rx, offset MIPS16e 580// Purpose: Branch on Equal to Zero 581// To test a GPR then do a PC-relative conditional branch. 582// 583def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 584 585 586// 587// Format: BEQZ rx, offset MIPS16e 588// Purpose: Branch on Equal to Zero (Extended) 589// To test a GPR then do a PC-relative conditional branch. 590// 591def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16; 592 593// 594// Format: B offset MIPS16e 595// Purpose: Unconditional Branch (Extended) 596// To do an unconditional PC-relative branch. 597// 598 599def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16; 600 601// Format: B offset MIPS16e 602// Purpose: Unconditional Branch 603// To do an unconditional PC-relative branch. 604// 605def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16; 606 607// 608// Format: BNEZ rx, offset MIPS16e 609// Purpose: Branch on Not Equal to Zero 610// To test a GPR then do a PC-relative conditional branch. 611// 612def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 613 614// 615// Format: BNEZ rx, offset MIPS16e 616// Purpose: Branch on Not Equal to Zero (Extended) 617// To test a GPR then do a PC-relative conditional branch. 618// 619def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; 620 621 622// 623//Format: BREAK immediate 624// Purpose: Breakpoint 625// To cause a Breakpoint exception. 626 627def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>; 628// 629// Format: BTEQZ offset MIPS16e 630// Purpose: Branch on T Equal to Zero (Extended) 631// To test special register T then do a PC-relative conditional branch. 632// 633def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 634 let Uses = [T8]; 635} 636 637def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { 638 let Uses = [T8]; 639} 640 641def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; 642 643def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">, 644 cbranch16; 645 646def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16; 647 648def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16; 649 650def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16; 651 652def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, 653 cbranch16; 654 655// 656// Format: BTNEZ offset MIPS16e 657// Purpose: Branch on T Not Equal to Zero (Extended) 658// To test special register T then do a PC-relative conditional branch. 659// 660 661def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 { 662 let Uses = [T8]; 663} 664 665def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { 666 let Uses = [T8]; 667} 668 669def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; 670 671def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16; 672 673def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16; 674 675def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16; 676 677def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16; 678 679def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, 680 cbranch16; 681 682// 683// Format: CMP rx, ry MIPS16e 684// Purpose: Compare 685// To compare the contents of two GPRs. 686// 687def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> { 688 let Defs = [T8]; 689} 690 691// 692// Format: CMPI rx, immediate MIPS16e 693// Purpose: Compare Immediate 694// To compare a constant with the contents of a GPR. 695// 696def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> { 697 let Defs = [T8]; 698} 699 700// 701// Format: CMPI rx, immediate MIPS16e 702// Purpose: Compare Immediate (Extended) 703// To compare a constant with the contents of a GPR. 704// 705def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> { 706 let Defs = [T8]; 707} 708 709 710// 711// Format: DIV rx, ry MIPS16e 712// Purpose: Divide Word 713// To divide 32-bit signed integers. 714// 715def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> { 716 let Defs = [HI0, LO0]; 717} 718 719// 720// Format: DIVU rx, ry MIPS16e 721// Purpose: Divide Unsigned Word 722// To divide 32-bit unsigned integers. 723// 724def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> { 725 let Defs = [HI0, LO0]; 726} 727// 728// Format: JAL target MIPS16e 729// Purpose: Jump and Link 730// To execute a procedure call within the current 256 MB-aligned 731// region and preserve the current ISA. 732// 733 734def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> { 735 let hasDelaySlot = 0; // not true, but we add the nop for now 736 let isCall=1; 737} 738 739// 740// Format: JR ra MIPS16e 741// Purpose: Jump Register Through Register ra 742// To execute a branch to the instruction address in the return 743// address register. 744// 745 746def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> { 747 let isBranch = 1; 748 let isIndirectBranch = 1; 749 let hasDelaySlot = 1; 750 let isTerminator=1; 751 let isBarrier=1; 752} 753 754def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> { 755 let isBranch = 1; 756 let isIndirectBranch = 1; 757 let isTerminator=1; 758 let isBarrier=1; 759} 760 761def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> { 762 let isBranch = 1; 763 let isIndirectBranch = 1; 764 let isTerminator=1; 765 let isBarrier=1; 766} 767// 768// Format: LB ry, offset(rx) MIPS16e 769// Purpose: Load Byte (Extended) 770// To load a byte from memory as a signed value. 771// 772def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{ 773 let isCodeGenOnly = 1; 774} 775 776// 777// Format: LBU ry, offset(rx) MIPS16e 778// Purpose: Load Byte Unsigned (Extended) 779// To load a byte from memory as a unsigned value. 780// 781def LbuRxRyOffMemX16: 782 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad { 783 let isCodeGenOnly = 1; 784} 785 786// 787// Format: LH ry, offset(rx) MIPS16e 788// Purpose: Load Halfword signed (Extended) 789// To load a halfword from memory as a signed value. 790// 791def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{ 792 let isCodeGenOnly = 1; 793} 794 795// 796// Format: LHU ry, offset(rx) MIPS16e 797// Purpose: Load Halfword unsigned (Extended) 798// To load a halfword from memory as an unsigned value. 799// 800def LhuRxRyOffMemX16: 801 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad { 802 let isCodeGenOnly = 1; 803} 804 805// 806// Format: LI rx, immediate MIPS16e 807// Purpose: Load Immediate 808// To load a constant into a GPR. 809// 810def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>; 811 812// 813// Format: LI rx, immediate MIPS16e 814// Purpose: Load Immediate (Extended) 815// To load a constant into a GPR. 816// 817def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>; 818 819def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> { 820 let isCodeGenOnly = 1; 821} 822 823// 824// Format: LW ry, offset(rx) MIPS16e 825// Purpose: Load Word (Extended) 826// To load a word from memory as a signed value. 827// 828def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{ 829 let isCodeGenOnly = 1; 830} 831 832// Format: LW rx, offset(sp) MIPS16e 833// Purpose: Load Word (SP-Relative, Extended) 834// To load an SP-relative word from memory as a signed value. 835// 836def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{ 837 let Uses = [SP]; 838} 839 840def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; 841 842def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad; 843// 844// Format: MOVE r32, rz MIPS16e 845// Purpose: Move 846// To move the contents of a GPR to a GPR. 847// 848def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>; 849 850// 851// Format: MOVE ry, r32 MIPS16e 852//Purpose: Move 853// To move the contents of a GPR to a GPR. 854// 855def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>; 856 857// 858// Format: MFHI rx MIPS16e 859// Purpose: Move From HI Register 860// To copy the special purpose HI register to a GPR. 861// 862def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> { 863 let Uses = [HI0]; 864 let neverHasSideEffects = 1; 865} 866 867// 868// Format: MFLO rx MIPS16e 869// Purpose: Move From LO Register 870// To copy the special purpose LO register to a GPR. 871// 872def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { 873 let Uses = [LO0]; 874 let neverHasSideEffects = 1; 875} 876 877// 878// Pseudo Instruction for mult 879// 880def MultRxRy16: FMULT16_ins<"mult", IIAlu> { 881 let isCommutable = 1; 882 let neverHasSideEffects = 1; 883 let Defs = [HI0, LO0]; 884} 885 886def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 887 let isCommutable = 1; 888 let neverHasSideEffects = 1; 889 let Defs = [HI0, LO0]; 890} 891 892// 893// Format: MULT rx, ry MIPS16e 894// Purpose: Multiply Word 895// To multiply 32-bit signed integers. 896// 897def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> { 898 let isCommutable = 1; 899 let neverHasSideEffects = 1; 900 let Defs = [HI0, LO0]; 901} 902 903// 904// Format: MULTU rx, ry MIPS16e 905// Purpose: Multiply Unsigned Word 906// To multiply 32-bit unsigned integers. 907// 908def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { 909 let isCommutable = 1; 910 let neverHasSideEffects = 1; 911 let Defs = [HI0, LO0]; 912} 913 914// 915// Format: NEG rx, ry MIPS16e 916// Purpose: Negate 917// To negate an integer value. 918// 919def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>; 920 921// 922// Format: NOT rx, ry MIPS16e 923// Purpose: Not 924// To complement an integer value 925// 926def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>; 927 928// 929// Format: OR rx, ry MIPS16e 930// Purpose: Or 931// To do a bitwise logical OR. 932// 933def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>; 934 935// 936// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize} 937// (All args are optional) MIPS16e 938// Purpose: Restore Registers and Deallocate Stack Frame 939// To deallocate a stack frame before exit from a subroutine, 940// restoring return address and static registers, and adjusting 941// stack 942// 943 944// fixed form for restoring RA and the frame 945// for direct object emitter, encoding needs to be adjusted for the 946// frame size 947// 948let ra=1, s=0,s0=1,s1=1 in 949def RestoreRaF16: 950 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 951 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad { 952 let isCodeGenOnly = 1; 953 let Defs = [S0, S1, S2, RA, SP]; 954 let Uses = [SP]; 955} 956 957// Use Restore to increment SP since SP is not a Mip 16 register, this 958// is an easy way to do that which does not require a register. 959// 960let ra=0, s=0,s0=0,s1=0 in 961def RestoreIncSpF16: 962 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 963 "restore\t$frame_size", [], IILoad >, MayLoad { 964 let isCodeGenOnly = 1; 965 let Defs = [SP]; 966 let Uses = [SP]; 967} 968 969// 970// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional) 971// MIPS16e 972// Purpose: Save Registers and Set Up Stack Frame 973// To set up a stack frame on entry to a subroutine, 974// saving return address and static registers, and adjusting stack 975// 976let ra=1, s=1,s0=1,s1=1 in 977def SaveRaF16: 978 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 979 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore { 980 let isCodeGenOnly = 1; 981 let Uses = [RA, SP, S0, S1, S2]; 982 let Defs = [SP]; 983} 984 985// 986// Use Save to decrement the SP by a constant since SP is not 987// a Mips16 register. 988// 989let ra=0, s=0,s0=0,s1=0 in 990def SaveDecSpF16: 991 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size), 992 "save\t$frame_size", [], IIStore >, MayStore { 993 let isCodeGenOnly = 1; 994 let Uses = [SP]; 995 let Defs = [SP]; 996} 997// 998// Format: SB ry, offset(rx) MIPS16e 999// Purpose: Store Byte (Extended) 1000// To store a byte to memory. 1001// 1002def SbRxRyOffMemX16: 1003 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; 1004 1005// 1006// Format: SEB rx MIPS16e 1007// Purpose: Sign-Extend Byte 1008// Sign-extend least significant byte in register rx. 1009// 1010def SebRx16 1011 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>; 1012 1013// 1014// Format: SEH rx MIPS16e 1015// Purpose: Sign-Extend Halfword 1016// Sign-extend least significant word in register rx. 1017// 1018def SehRx16 1019 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>; 1020 1021// 1022// The Sel(T) instructions are pseudos 1023// T means that they use T8 implicitly. 1024// 1025// 1026// Format: SelBeqZ rd, rs, rt 1027// Purpose: if rt==0, do nothing 1028// else rs = rt 1029// 1030def SelBeqZ: Sel<"beqz">; 1031 1032// 1033// Format: SelTBteqZCmp rd, rs, rl, rr 1034// Purpose: b = Cmp rl, rr. 1035// If b==0 then do nothing. 1036// if b!=0 then rd = rs 1037// 1038def SelTBteqZCmp: SelT<"bteqz", "cmp">; 1039 1040// 1041// Format: SelTBteqZCmpi rd, rs, rl, rr 1042// Purpose: b = Cmpi rl, imm. 1043// If b==0 then do nothing. 1044// if b!=0 then rd = rs 1045// 1046def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">; 1047 1048// 1049// Format: SelTBteqZSlt rd, rs, rl, rr 1050// Purpose: b = Slt rl, rr. 1051// If b==0 then do nothing. 1052// if b!=0 then rd = rs 1053// 1054def SelTBteqZSlt: SelT<"bteqz", "slt">; 1055 1056// 1057// Format: SelTBteqZSlti rd, rs, rl, rr 1058// Purpose: b = Slti rl, imm. 1059// If b==0 then do nothing. 1060// if b!=0 then rd = rs 1061// 1062def SelTBteqZSlti: SeliT<"bteqz", "slti">; 1063 1064// 1065// Format: SelTBteqZSltu rd, rs, rl, rr 1066// Purpose: b = Sltu rl, rr. 1067// If b==0 then do nothing. 1068// if b!=0 then rd = rs 1069// 1070def SelTBteqZSltu: SelT<"bteqz", "sltu">; 1071 1072// 1073// Format: SelTBteqZSltiu rd, rs, rl, rr 1074// Purpose: b = Sltiu rl, imm. 1075// If b==0 then do nothing. 1076// if b!=0 then rd = rs 1077// 1078def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">; 1079 1080// 1081// Format: SelBnez rd, rs, rt 1082// Purpose: if rt!=0, do nothing 1083// else rs = rt 1084// 1085def SelBneZ: Sel<"bnez">; 1086 1087// 1088// Format: SelTBtneZCmp rd, rs, rl, rr 1089// Purpose: b = Cmp rl, rr. 1090// If b!=0 then do nothing. 1091// if b0=0 then rd = rs 1092// 1093def SelTBtneZCmp: SelT<"btnez", "cmp">; 1094 1095// 1096// Format: SelTBtnezCmpi rd, rs, rl, rr 1097// Purpose: b = Cmpi rl, imm. 1098// If b!=0 then do nothing. 1099// if b==0 then rd = rs 1100// 1101def SelTBtneZCmpi: SeliT<"btnez", "cmpi">; 1102 1103// 1104// Format: SelTBtneZSlt rd, rs, rl, rr 1105// Purpose: b = Slt rl, rr. 1106// If b!=0 then do nothing. 1107// if b==0 then rd = rs 1108// 1109def SelTBtneZSlt: SelT<"btnez", "slt">; 1110 1111// 1112// Format: SelTBtneZSlti rd, rs, rl, rr 1113// Purpose: b = Slti rl, imm. 1114// If b!=0 then do nothing. 1115// if b==0 then rd = rs 1116// 1117def SelTBtneZSlti: SeliT<"btnez", "slti">; 1118 1119// 1120// Format: SelTBtneZSltu rd, rs, rl, rr 1121// Purpose: b = Sltu rl, rr. 1122// If b!=0 then do nothing. 1123// if b==0 then rd = rs 1124// 1125def SelTBtneZSltu: SelT<"btnez", "sltu">; 1126 1127// 1128// Format: SelTBtneZSltiu rd, rs, rl, rr 1129// Purpose: b = Slti rl, imm. 1130// If b!=0 then do nothing. 1131// if b==0 then rd = rs 1132// 1133def SelTBtneZSltiu: SeliT<"btnez", "sltiu">; 1134// 1135// 1136// Format: SH ry, offset(rx) MIPS16e 1137// Purpose: Store Halfword (Extended) 1138// To store a halfword to memory. 1139// 1140def ShRxRyOffMemX16: 1141 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore; 1142 1143// 1144// Format: SLL rx, ry, sa MIPS16e 1145// Purpose: Shift Word Left Logical (Extended) 1146// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits. 1147// 1148def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; 1149 1150// 1151// Format: SLLV ry, rx MIPS16e 1152// Purpose: Shift Word Left Logical Variable 1153// To execute a left-shift of a word by a variable number of bits. 1154// 1155def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; 1156 1157// Format: SLTI rx, immediate MIPS16e 1158// Purpose: Set on Less Than Immediate 1159// To record the result of a less-than comparison with a constant. 1160// 1161// 1162def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> { 1163 let Defs = [T8]; 1164} 1165 1166// 1167// Format: SLTI rx, immediate MIPS16e 1168// Purpose: Set on Less Than Immediate (Extended) 1169// To record the result of a less-than comparison with a constant. 1170// 1171// 1172def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> { 1173 let Defs = [T8]; 1174} 1175 1176def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; 1177 1178// Format: SLTIU rx, immediate MIPS16e 1179// Purpose: Set on Less Than Immediate Unsigned 1180// To record the result of a less-than comparison with a constant. 1181// 1182// 1183def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> { 1184 let Defs = [T8]; 1185} 1186 1187// 1188// Format: SLTI rx, immediate MIPS16e 1189// Purpose: Set on Less Than Immediate Unsigned (Extended) 1190// To record the result of a less-than comparison with a constant. 1191// 1192// 1193def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> { 1194 let Defs = [T8]; 1195} 1196// 1197// Format: SLTIU rx, immediate MIPS16e 1198// Purpose: Set on Less Than Immediate Unsigned (Extended) 1199// To record the result of a less-than comparison with a constant. 1200// 1201def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">; 1202 1203// 1204// Format: SLT rx, ry MIPS16e 1205// Purpose: Set on Less Than 1206// To record the result of a less-than comparison. 1207// 1208def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{ 1209 let Defs = [T8]; 1210} 1211 1212def SltCCRxRy16: FCCRR16_ins<"slt">; 1213 1214// Format: SLTU rx, ry MIPS16e 1215// Purpose: Set on Less Than Unsigned 1216// To record the result of an unsigned less-than comparison. 1217// 1218def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{ 1219 let Defs = [T8]; 1220} 1221 1222def SltuRxRyRz16: FRRTR16_ins<"sltu"> { 1223 let isCodeGenOnly=1; 1224 let Defs = [T8]; 1225} 1226 1227 1228def SltuCCRxRy16: FCCRR16_ins<"sltu">; 1229// 1230// Format: SRAV ry, rx MIPS16e 1231// Purpose: Shift Word Right Arithmetic Variable 1232// To execute an arithmetic right-shift of a word by a variable 1233// number of bits. 1234// 1235def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>; 1236 1237 1238// 1239// Format: SRA rx, ry, sa MIPS16e 1240// Purpose: Shift Word Right Arithmetic (Extended) 1241// To execute an arithmetic right-shift of a word by a fixed 1242// number of bits-1 to 8 bits. 1243// 1244def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; 1245 1246 1247// 1248// Format: SRLV ry, rx MIPS16e 1249// Purpose: Shift Word Right Logical Variable 1250// To execute a logical right-shift of a word by a variable 1251// number of bits. 1252// 1253def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>; 1254 1255 1256// 1257// Format: SRL rx, ry, sa MIPS16e 1258// Purpose: Shift Word Right Logical (Extended) 1259// To execute a logical right-shift of a word by a fixed 1260// number of bits-1 to 31 bits. 1261// 1262def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; 1263 1264// 1265// Format: SUBU rz, rx, ry MIPS16e 1266// Purpose: Subtract Unsigned Word 1267// To subtract 32-bit integers 1268// 1269def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>; 1270 1271// 1272// Format: SW ry, offset(rx) MIPS16e 1273// Purpose: Store Word (Extended) 1274// To store a word to memory. 1275// 1276def SwRxRyOffMemX16: 1277 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore; 1278 1279// 1280// Format: SW rx, offset(sp) MIPS16e 1281// Purpose: Store Word rx (SP-Relative) 1282// To store an SP-relative word to memory. 1283// 1284def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins 1285 <0b11010, "sw", IIStore>, MayStore; 1286 1287// 1288// 1289// Format: XOR rx, ry MIPS16e 1290// Purpose: Xor 1291// To do a bitwise logical XOR. 1292// 1293def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>; 1294 1295class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> { 1296 let Predicates = [InMips16Mode]; 1297} 1298 1299// Unary Arith/Logic 1300// 1301class ArithLogicU_pat<PatFrag OpNode, Instruction I> : 1302 Mips16Pat<(OpNode CPU16Regs:$r), 1303 (I CPU16Regs:$r)>; 1304 1305def: ArithLogicU_pat<not, NotRxRy16>; 1306def: ArithLogicU_pat<ineg, NegRxRy16>; 1307 1308class ArithLogic16_pat<SDNode OpNode, Instruction I> : 1309 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r), 1310 (I CPU16Regs:$l, CPU16Regs:$r)>; 1311 1312def: ArithLogic16_pat<add, AdduRxRyRz16>; 1313def: ArithLogic16_pat<and, AndRxRxRy16>; 1314def: ArithLogic16_pat<mul, MultRxRyRz16>; 1315def: ArithLogic16_pat<or, OrRxRxRy16>; 1316def: ArithLogic16_pat<sub, SubuRxRyRz16>; 1317def: ArithLogic16_pat<xor, XorRxRxRy16>; 1318 1319// Arithmetic and logical instructions with 2 register operands. 1320 1321class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : 1322 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), 1323 (I CPU16Regs:$in, imm_type:$imm)>; 1324 1325def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; 1326def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; 1327def: ArithLogicI16_pat<shl, immZExt5, SllX16>; 1328def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; 1329def: ArithLogicI16_pat<sra, immZExt5, SraX16>; 1330 1331class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> : 1332 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra), 1333 (I CPU16Regs:$r, CPU16Regs:$ra)>; 1334 1335def: shift_rotate_reg16_pat<shl, SllvRxRy16>; 1336def: shift_rotate_reg16_pat<sra, SravRxRy16>; 1337def: shift_rotate_reg16_pat<srl, SrlvRxRy16>; 1338 1339class LoadM16_pat<PatFrag OpNode, Instruction I> : 1340 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>; 1341 1342def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>; 1343def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>; 1344def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>; 1345def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>; 1346def: LoadM16_pat<load, LwRxRyOffMemX16>; 1347 1348class StoreM16_pat<PatFrag OpNode, Instruction I> : 1349 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr), 1350 (I CPU16Regs:$r, addr16:$addr)>; 1351 1352def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>; 1353def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>; 1354def: StoreM16_pat<store, SwRxRyOffMemX16>; 1355 1356// Unconditional branch 1357class UncondBranch16_pat<SDNode OpNode, Instruction I>: 1358 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1359 let Predicates = [InMips16Mode]; 1360 } 1361 1362def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1363 (Jal16 tglobaladdr:$dst)>; 1364 1365def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)), 1366 (Jal16 texternalsym:$dst)>; 1367 1368// Indirect branch 1369def: Mips16Pat< 1370 (brind CPU16Regs:$rs), 1371 (JrcRx16 CPU16Regs:$rs)>; 1372 1373// Jump and Link (Call) 1374let isCall=1, hasDelaySlot=0 in 1375def JumpLinkReg16: 1376 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), 1377 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; 1378 1379// Mips16 pseudos 1380let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1, 1381 hasExtraSrcRegAllocReq = 1 in 1382def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>; 1383 1384 1385// setcc patterns 1386 1387class SetCC_R16<PatFrag cond_op, Instruction I>: 1388 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry), 1389 (I CPU16Regs:$rx, CPU16Regs:$ry)>; 1390 1391class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>: 1392 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1393 (I CPU16Regs:$rx, imm_type:$imm16)>; 1394 1395 1396def: Mips16Pat<(i32 addr16:$addr), 1397 (AddiuRxRyOffMemX16 addr16:$addr)>; 1398 1399 1400// Large (>16 bit) immediate loads 1401def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>; 1402 1403// Carry MipsPatterns 1404def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs), 1405 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1406def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs), 1407 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>; 1408def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm), 1409 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>; 1410 1411// 1412// Some branch conditional patterns are not generated by llvm at this time. 1413// Some are for seemingly arbitrary reasons not used: i.e. with signed number 1414// comparison they are used and for unsigned a different pattern is used. 1415// I am pushing upstream from the full mips16 port and it seemed that I needed 1416// these earlier and the mips32 port has these but now I cannot create test 1417// cases that use these patterns. While I sort this all out I will leave these 1418// extra patterns commented out and if I can be sure they are really not used, 1419// I will delete the code. I don't want to check the code in uncommented without 1420// a valid test case. In some cases, the compiler is generating patterns with 1421// setcc instead and earlier I had implemented setcc first so may have masked 1422// the problem. The setcc variants are suboptimal for mips16 so I may wantto 1423// figure out how to enable the brcond patterns or else possibly new 1424// combinations of of brcond and setcc. 1425// 1426// 1427// bcond-seteq 1428// 1429def: Mips16Pat 1430 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1431 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1432 >; 1433 1434 1435def: Mips16Pat 1436 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1437 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1438 >; 1439 1440def: Mips16Pat 1441 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16), 1442 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16) 1443 >; 1444 1445// 1446// bcond-setgt (do we need to have this pair of setlt, setgt??) 1447// 1448def: Mips16Pat 1449 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1450 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1451 >; 1452 1453// 1454// bcond-setge 1455// 1456def: Mips16Pat 1457 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1458 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1459 >; 1460 1461// 1462// never called because compiler transforms a >= k to a > (k-1) 1463def: Mips16Pat 1464 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1465 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1466 >; 1467 1468// 1469// bcond-setlt 1470// 1471def: Mips16Pat 1472 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1473 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1474 >; 1475 1476def: Mips16Pat 1477 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1478 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16) 1479 >; 1480 1481// 1482// bcond-setle 1483// 1484def: Mips16Pat 1485 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1486 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1487 >; 1488 1489// 1490// bcond-setne 1491// 1492def: Mips16Pat 1493 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1494 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1495 >; 1496 1497def: Mips16Pat 1498 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16), 1499 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16) 1500 >; 1501 1502def: Mips16Pat 1503 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16), 1504 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16) 1505 >; 1506 1507// 1508// This needs to be there but I forget which code will generate it 1509// 1510def: Mips16Pat 1511 <(brcond CPU16Regs:$rx, bb:$targ16), 1512 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16) 1513 >; 1514 1515// 1516 1517// 1518// bcond-setugt 1519// 1520//def: Mips16Pat 1521// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1522// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16) 1523// >; 1524 1525// 1526// bcond-setuge 1527// 1528//def: Mips16Pat 1529// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1530// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1531// >; 1532 1533 1534// 1535// bcond-setult 1536// 1537//def: Mips16Pat 1538// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1539// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1540// >; 1541 1542def: UncondBranch16_pat<br, Bimm16>; 1543 1544// Small immediates 1545def: Mips16Pat<(i32 immSExt16:$in), 1546 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>; 1547 1548def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>; 1549 1550// 1551// MipsDivRem 1552// 1553def: Mips16Pat 1554 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry), 1555 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1556 1557// 1558// MipsDivRemU 1559// 1560def: Mips16Pat 1561 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry), 1562 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>; 1563 1564// signed a,b 1565// x = (a>=b)?x:y 1566// 1567// if !(a < b) x = y 1568// 1569def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)), 1570 CPU16Regs:$x, CPU16Regs:$y), 1571 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1572 CPU16Regs:$a, CPU16Regs:$b)>; 1573 1574// signed a,b 1575// x = (a>b)?x:y 1576// 1577// if (b < a) x = y 1578// 1579def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)), 1580 CPU16Regs:$x, CPU16Regs:$y), 1581 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y, 1582 CPU16Regs:$b, CPU16Regs:$a)>; 1583 1584// unsigned a,b 1585// x = (a>=b)?x:y 1586// 1587// if !(a < b) x = y; 1588// 1589def : Mips16Pat< 1590 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)), 1591 CPU16Regs:$x, CPU16Regs:$y), 1592 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1593 CPU16Regs:$a, CPU16Regs:$b)>; 1594 1595// unsigned a,b 1596// x = (a>b)?x:y 1597// 1598// if (b < a) x = y 1599// 1600def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)), 1601 CPU16Regs:$x, CPU16Regs:$y), 1602 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y, 1603 CPU16Regs:$b, CPU16Regs:$a)>; 1604 1605// signed 1606// x = (a >= k)?x:y 1607// due to an llvm optimization, i don't think that this will ever 1608// be used. This is transformed into x = (a > k-1)?x:y 1609// 1610// 1611 1612//def : Mips16Pat< 1613// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)), 1614// CPU16Regs:$T, CPU16Regs:$F), 1615// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F, 1616// CPU16Regs:$lhs, immSExt16:$rhs)>; 1617 1618//def : Mips16Pat< 1619// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)), 1620// CPU16Regs:$T, CPU16Regs:$F), 1621// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F, 1622// CPU16Regs:$lhs, immSExt16:$rhs)>; 1623 1624// signed 1625// x = (a < k)?x:y 1626// 1627// if !(a < k) x = y; 1628// 1629def : Mips16Pat< 1630 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1631 CPU16Regs:$x, CPU16Regs:$y), 1632 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y, 1633 CPU16Regs:$a, immSExt16:$b)>; 1634 1635 1636// 1637// 1638// signed 1639// x = (a <= b)? x : y 1640// 1641// if (b < a) x = y 1642// 1643def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), 1644 CPU16Regs:$x, CPU16Regs:$y), 1645 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y, 1646 CPU16Regs:$b, CPU16Regs:$a)>; 1647 1648// 1649// unnsigned 1650// x = (a <= b)? x : y 1651// 1652// if (b < a) x = y 1653// 1654def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)), 1655 CPU16Regs:$x, CPU16Regs:$y), 1656 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y, 1657 CPU16Regs:$b, CPU16Regs:$a)>; 1658 1659// 1660// signed/unsigned 1661// x = (a == b)? x : y 1662// 1663// if (a != b) x = y 1664// 1665def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)), 1666 CPU16Regs:$x, CPU16Regs:$y), 1667 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y, 1668 CPU16Regs:$b, CPU16Regs:$a)>; 1669 1670// 1671// signed/unsigned 1672// x = (a == 0)? x : y 1673// 1674// if (a != 0) x = y 1675// 1676def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)), 1677 CPU16Regs:$x, CPU16Regs:$y), 1678 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y, 1679 CPU16Regs:$a)>; 1680 1681 1682// 1683// signed/unsigned 1684// x = (a == k)? x : y 1685// 1686// if (a != k) x = y 1687// 1688def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)), 1689 CPU16Regs:$x, CPU16Regs:$y), 1690 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y, 1691 CPU16Regs:$a, immZExt16:$k)>; 1692 1693 1694// 1695// signed/unsigned 1696// x = (a != b)? x : y 1697// 1698// if (a == b) x = y 1699// 1700// 1701def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)), 1702 CPU16Regs:$x, CPU16Regs:$y), 1703 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y, 1704 CPU16Regs:$b, CPU16Regs:$a)>; 1705 1706// 1707// signed/unsigned 1708// x = (a != 0)? x : y 1709// 1710// if (a == 0) x = y 1711// 1712def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)), 1713 CPU16Regs:$x, CPU16Regs:$y), 1714 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1715 CPU16Regs:$a)>; 1716 1717// signed/unsigned 1718// x = (a)? x : y 1719// 1720// if (!a) x = y 1721// 1722def : Mips16Pat<(select CPU16Regs:$a, 1723 CPU16Regs:$x, CPU16Regs:$y), 1724 (SelBneZ CPU16Regs:$x, CPU16Regs:$y, 1725 CPU16Regs:$a)>; 1726 1727 1728// 1729// signed/unsigned 1730// x = (a != k)? x : y 1731// 1732// if (a == k) x = y 1733// 1734def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)), 1735 CPU16Regs:$x, CPU16Regs:$y), 1736 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y, 1737 CPU16Regs:$a, immZExt16:$k)>; 1738 1739// 1740// When writing C code to test setxx these patterns, 1741// some will be transformed into 1742// other things. So we test using C code but using -O3 and -O0 1743// 1744// seteq 1745// 1746def : Mips16Pat 1747 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs), 1748 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>; 1749 1750def : Mips16Pat 1751 <(seteq CPU16Regs:$lhs, 0), 1752 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>; 1753 1754 1755// 1756// setge 1757// 1758 1759def: Mips16Pat 1760 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs), 1761 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1762 (LiRxImmX16 1))>; 1763 1764// 1765// For constants, llvm transforms this to: 1766// x > (k -1) and then reverses the operands to use setlt. So this pattern 1767// is not used now by the compiler. (Presumably checking that k-1 does not 1768// overflow). The compiler never uses this at a the current time, due to 1769// other optimizations. 1770// 1771//def: Mips16Pat 1772// <(setge CPU16Regs:$lhs, immSExt16:$rhs), 1773// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs), 1774// (LiRxImmX16 1))>; 1775 1776// This catches the x >= -32768 case by transforming it to x > -32769 1777// 1778def: Mips16Pat 1779 <(setgt CPU16Regs:$lhs, -32769), 1780 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768), 1781 (LiRxImmX16 1))>; 1782 1783// 1784// setgt 1785// 1786// 1787 1788def: Mips16Pat 1789 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs), 1790 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1791 1792// 1793// setle 1794// 1795def: Mips16Pat 1796 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs), 1797 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>; 1798 1799// 1800// setlt 1801// 1802def: SetCC_R16<setlt, SltCCRxRy16>; 1803 1804def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>; 1805 1806// 1807// setne 1808// 1809def : Mips16Pat 1810 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs), 1811 (SltuCCRxRy16 (LiRxImmX16 0), 1812 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>; 1813 1814 1815// 1816// setuge 1817// 1818def: Mips16Pat 1819 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs), 1820 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1821 (LiRxImmX16 1))>; 1822 1823// this pattern will never be used because the compiler will transform 1824// x >= k to x > (k - 1) and then use SLT 1825// 1826//def: Mips16Pat 1827// <(setuge CPU16Regs:$lhs, immZExt16:$rhs), 1828// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), 1829// (LiRxImmX16 1))>; 1830 1831// 1832// setugt 1833// 1834def: Mips16Pat 1835 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs), 1836 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>; 1837 1838// 1839// setule 1840// 1841def: Mips16Pat 1842 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs), 1843 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>; 1844 1845// 1846// setult 1847// 1848def: SetCC_R16<setult, SltuCCRxRy16>; 1849 1850def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>; 1851 1852def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), 1853 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>; 1854 1855// hi/lo relocs 1856def : Mips16Pat<(MipsHi tblockaddress:$in), 1857 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>; 1858def : Mips16Pat<(MipsHi tglobaladdr:$in), 1859 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>; 1860def : Mips16Pat<(MipsHi tjumptable:$in), 1861 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>; 1862def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), 1863 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; 1864 1865def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>; 1866 1867// wrapper_pic 1868class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1869 Mips16Pat<(MipsWrapper RC:$gp, node:$in), 1870 (ADDiuOp RC:$gp, node:$in)>; 1871 1872 1873def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>; 1874def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>; 1875 1876def : Mips16Pat<(i32 (extloadi8 addr16:$src)), 1877 (LbuRxRyOffMemX16 addr16:$src)>; 1878def : Mips16Pat<(i32 (extloadi16 addr16:$src)), 1879 (LhuRxRyOffMemX16 addr16:$src)>; 1880 1881def: Mips16Pat<(trap), (Break16)>; 1882 1883def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8), 1884 (SebRx16 CPU16Regs:$val)>; 1885 1886def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16), 1887 (SehRx16 CPU16Regs:$val)>; 1888 1889def GotPrologue16: 1890 MipsPseudo16< 1891 (outs CPU16Regs:$rh, CPU16Regs:$rl), 1892 (ins simm16:$immHi, simm16:$immLo), 1893 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ; 1894 1895// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 1896def cpinst_operand : Operand<i32> { 1897 // let PrintMethod = "printCPInstOperand"; 1898} 1899 1900// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1901// the function. The first operand is the ID# for this instruction, the second 1902// is the index into the MachineConstantPool that this is, the third is the 1903// size in bytes of this constant pool entry. 1904// 1905let neverHasSideEffects = 1, isNotDuplicable = 1 in 1906def CONSTPOOL_ENTRY : 1907MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1908 i32imm:$size), "foo", []>; 1909 1910