1239310Sdim//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the University of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim 10239310Sdim//===----------------------------------------------------------------------===// 11239310Sdim// Describe MIPS instructions format 12239310Sdim// 13239310Sdim// CPU INSTRUCTION FORMATS 14239310Sdim// 15239310Sdim// funct or f Function field 16239310Sdim// 17239310Sdim// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or 18239310Sdim// or imm address displacement 19239310Sdim// 20239310Sdim// op 5-bit major operation code 21239310Sdim// 22239310Sdim// rx 3-bit source or destination register 23239310Sdim// 24239310Sdim// ry 3-bit source or destination register 25239310Sdim// 26239310Sdim// rz 3-bit source or destination register 27239310Sdim// 28239310Sdim// sa 3- or 5-bit shift amount 29239310Sdim// 30239310Sdim//===----------------------------------------------------------------------===// 31239310Sdim 32239310Sdim 33239310Sdim// Base class for Mips 16 Format 34239310Sdim// This class does not depend on the instruction size 35239310Sdim// 36239310Sdimclass MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern, 37249423Sdim InstrItinClass itin>: Instruction 38239310Sdim{ 39239310Sdim 40239310Sdim let Namespace = "Mips"; 41239310Sdim 42239310Sdim let OutOperandList = outs; 43239310Sdim let InOperandList = ins; 44239310Sdim 45239310Sdim let AsmString = asmstr; 46239310Sdim let Pattern = pattern; 47239310Sdim let Itinerary = itin; 48239310Sdim 49239310Sdim let Predicates = [InMips16Mode]; 50239310Sdim} 51239310Sdim 52239310Sdim// 53239310Sdim// Generic Mips 16 Format 54239310Sdim// 55239310Sdimclass MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern, 56249423Sdim InstrItinClass itin>: 57249423Sdim MipsInst16_Base<outs, ins, asmstr, pattern, itin> 58239310Sdim{ 59239310Sdim field bits<16> Inst; 60239310Sdim bits<5> Opcode = 0; 61239310Sdim 62239310Sdim // Top 5 bits are the 'opcode' field 63239310Sdim let Inst{15-11} = Opcode; 64263508Sdim 65249423Sdim let Size=2; 66249423Sdim field bits<16> SoftFail = 0; 67239310Sdim} 68239310Sdim 69239310Sdim// 70239310Sdim// For 32 bit extended instruction forms. 71239310Sdim// 72239310Sdimclass MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern, 73249423Sdim InstrItinClass itin>: 74249423Sdim MipsInst16_Base<outs, ins, asmstr, pattern, itin> 75239310Sdim{ 76239310Sdim field bits<32> Inst; 77263508Sdim 78249423Sdim let Size=4; 79249423Sdim field bits<32> SoftFail = 0; 80239310Sdim} 81239310Sdim 82239310Sdimclass MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern, 83249423Sdim InstrItinClass itin>: 84249423Sdim MipsInst16_32<outs, ins, asmstr, pattern, itin> 85239310Sdim{ 86239310Sdim let Inst{31-27} = 0b11110; 87239310Sdim} 88239310Sdim 89239310Sdim 90239310Sdim 91239310Sdim// Mips Pseudo Instructions Format 92239310Sdimclass MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>: 93249423Sdim MipsInst16<outs, ins, asmstr, pattern, IIPseudo> { 94239310Sdim let isCodeGenOnly = 1; 95239310Sdim let isPseudo = 1; 96239310Sdim} 97239310Sdim 98239310Sdim 99239310Sdim//===----------------------------------------------------------------------===// 100239310Sdim// Format I instruction class in Mips : <|opcode|imm11|> 101239310Sdim//===----------------------------------------------------------------------===// 102239310Sdim 103239310Sdimclass FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern, 104239310Sdim InstrItinClass itin>: 105249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 106239310Sdim{ 107239310Sdim bits<11> imm11; 108239310Sdim 109239310Sdim let Opcode = op; 110239310Sdim 111239310Sdim let Inst{10-0} = imm11; 112239310Sdim} 113239310Sdim 114239310Sdim//===----------------------------------------------------------------------===// 115239310Sdim// Format RI instruction class in Mips : <|opcode|rx|imm8|> 116239310Sdim//===----------------------------------------------------------------------===// 117239310Sdim 118239310Sdimclass FRI16<bits<5> op, dag outs, dag ins, string asmstr, 119239310Sdim list<dag> pattern, InstrItinClass itin>: 120249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 121239310Sdim{ 122239310Sdim bits<3> rx; 123239310Sdim bits<8> imm8; 124239310Sdim 125239310Sdim let Opcode = op; 126239310Sdim 127239310Sdim let Inst{10-8} = rx; 128239310Sdim let Inst{7-0} = imm8; 129239310Sdim} 130239310Sdim 131239310Sdim//===----------------------------------------------------------------------===// 132239310Sdim// Format RR instruction class in Mips : <|opcode|rx|ry|funct|> 133239310Sdim//===----------------------------------------------------------------------===// 134239310Sdim 135239310Sdimclass FRR16<bits<5> _funct, dag outs, dag ins, string asmstr, 136239310Sdim list<dag> pattern, InstrItinClass itin>: 137249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 138239310Sdim{ 139239310Sdim bits<3> rx; 140239310Sdim bits<3> ry; 141239310Sdim bits<5> funct; 142239310Sdim 143239310Sdim let Opcode = 0b11101; 144239310Sdim let funct = _funct; 145239310Sdim 146239310Sdim let Inst{10-8} = rx; 147239310Sdim let Inst{7-5} = ry; 148239310Sdim let Inst{4-0} = funct; 149239310Sdim} 150239310Sdim 151263508Sdimclass FRRBreak16<dag outs, dag ins, string asmstr, 152263508Sdim list<dag> pattern, InstrItinClass itin>: 153263508Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 154263508Sdim{ 155263508Sdim bits<6> Code; 156263508Sdim bits<5> funct; 157263508Sdim 158263508Sdim let Opcode = 0b11101; 159263508Sdim let funct = 0b00101; 160263508Sdim 161263508Sdim let Inst{10-5} = Code; 162263508Sdim let Inst{4-0} = funct; 163263508Sdim} 164263508Sdim 165239310Sdim// 166239310Sdim// For conversion functions. 167239310Sdim// 168239310Sdimclass FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins, 169239310Sdim string asmstr, list<dag> pattern, InstrItinClass itin>: 170249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 171239310Sdim{ 172239310Sdim bits<3> rx; 173239310Sdim bits<3> subfunct; 174239310Sdim bits<5> funct; 175239310Sdim 176239310Sdim let Opcode = 0b11101; // RR 177239310Sdim let funct = _funct; 178239310Sdim let subfunct = _subfunct; 179239310Sdim 180239310Sdim let Inst{10-8} = rx; 181239310Sdim let Inst{7-5} = subfunct; 182239310Sdim let Inst{4-0} = funct; 183239310Sdim} 184239310Sdim 185239310Sdim// 186239310Sdim// just used for breakpoint (hardware and software) instructions. 187239310Sdim// 188239310Sdimclass FC16<bits<5> _funct, dag outs, dag ins, string asmstr, 189239310Sdim list<dag> pattern, InstrItinClass itin>: 190249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 191239310Sdim{ 192239310Sdim bits<6> _code; // code is a keyword in tablegen 193239310Sdim bits<5> funct; 194239310Sdim 195239310Sdim let Opcode = 0b11101; // RR 196239310Sdim let funct = _funct; 197239310Sdim 198239310Sdim let Inst{10-5} = _code; 199239310Sdim let Inst{4-0} = funct; 200239310Sdim} 201239310Sdim 202239310Sdim// 203239310Sdim// J(AL)R(C) subformat 204239310Sdim// 205239310Sdimclass FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a, 206239310Sdim dag outs, dag ins, string asmstr, 207239310Sdim list<dag> pattern, InstrItinClass itin>: 208249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 209239310Sdim{ 210239310Sdim bits<3> rx; 211239310Sdim bits<1> nd; 212239310Sdim bits<1> l; 213239310Sdim bits<1> ra; 214239310Sdim 215239310Sdim let nd = _nd; 216239310Sdim let l = _l; 217239310Sdim let ra = r_a; 218239310Sdim 219239310Sdim let Opcode = 0b11101; 220239310Sdim 221239310Sdim let Inst{10-8} = rx; 222239310Sdim let Inst{7} = nd; 223239310Sdim let Inst{6} = l; 224239310Sdim let Inst{5} = ra; 225239310Sdim let Inst{4-0} = 0; 226239310Sdim} 227239310Sdim 228239310Sdim//===----------------------------------------------------------------------===// 229239310Sdim// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|> 230239310Sdim//===----------------------------------------------------------------------===// 231239310Sdim 232239310Sdimclass FRRI16<bits<5> op, dag outs, dag ins, string asmstr, 233239310Sdim list<dag> pattern, InstrItinClass itin>: 234249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 235239310Sdim{ 236239310Sdim bits<3> rx; 237239310Sdim bits<3> ry; 238239310Sdim bits<5> imm5; 239239310Sdim 240239310Sdim let Opcode = op; 241239310Sdim 242239310Sdim 243239310Sdim let Inst{10-8} = rx; 244239310Sdim let Inst{7-5} = ry; 245239310Sdim let Inst{4-0} = imm5; 246239310Sdim} 247239310Sdim 248239310Sdim//===----------------------------------------------------------------------===// 249239310Sdim// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|> 250239310Sdim//===----------------------------------------------------------------------===// 251239310Sdim 252239310Sdimclass FRRR16<bits<2> _f, dag outs, dag ins, string asmstr, 253239310Sdim list<dag> pattern, InstrItinClass itin>: 254249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 255239310Sdim{ 256239310Sdim bits<3> rx; 257239310Sdim bits<3> ry; 258239310Sdim bits<3> rz; 259239310Sdim bits<2> f; 260239310Sdim 261239310Sdim let Opcode = 0b11100; 262239310Sdim let f = _f; 263239310Sdim 264239310Sdim let Inst{10-8} = rx; 265239310Sdim let Inst{7-5} = ry; 266239310Sdim let Inst{4-2} = rz; 267239310Sdim let Inst{1-0} = f; 268239310Sdim} 269239310Sdim 270239310Sdim//===----------------------------------------------------------------------===// 271239310Sdim// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|> 272239310Sdim//===----------------------------------------------------------------------===// 273239310Sdim 274239310Sdimclass FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 275239310Sdim list<dag> pattern, InstrItinClass itin>: 276249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 277239310Sdim{ 278239310Sdim bits<3> rx; 279239310Sdim bits<3> ry; 280239310Sdim bits<1> f; 281239310Sdim bits<4> imm4; 282239310Sdim 283239310Sdim let Opcode = 0b01000; 284239310Sdim let f = _f; 285239310Sdim 286239310Sdim let Inst{10-8} = rx; 287239310Sdim let Inst{7-5} = ry; 288239310Sdim let Inst{4} = f; 289239310Sdim let Inst{3-0} = imm4; 290239310Sdim} 291239310Sdim 292239310Sdim//===----------------------------------------------------------------------===// 293239310Sdim// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|> 294239310Sdim//===----------------------------------------------------------------------===// 295239310Sdim 296239310Sdimclass FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 297239310Sdim list<dag> pattern, InstrItinClass itin>: 298249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 299239310Sdim{ 300239310Sdim bits<3> rx; 301239310Sdim bits<3> ry; 302239310Sdim bits<3> sa; 303239310Sdim bits<2> f; 304239310Sdim 305239310Sdim let Opcode = 0b00110; 306239310Sdim let f = _f; 307239310Sdim 308239310Sdim let Inst{10-8} = rx; 309239310Sdim let Inst{7-5} = ry; 310239310Sdim let Inst{4-2} = sa; 311239310Sdim let Inst{1-0} = f; 312239310Sdim} 313239310Sdim 314239310Sdim//===----------------------------------------------------------------------===// 315239310Sdim// Format i8 instruction class in Mips : <|opcode|funct|imm8> 316239310Sdim//===----------------------------------------------------------------------===// 317239310Sdim 318239310Sdimclass FI816<bits<3> _func, dag outs, dag ins, string asmstr, 319239310Sdim list<dag> pattern, InstrItinClass itin>: 320249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 321239310Sdim{ 322239310Sdim bits<3> func; 323239310Sdim bits<8> imm8; 324239310Sdim 325239310Sdim let Opcode = 0b01100; 326239310Sdim let func = _func; 327239310Sdim 328239310Sdim let Inst{10-8} = func; 329239310Sdim let Inst{7-0} = imm8; 330239310Sdim} 331239310Sdim 332239310Sdim//===----------------------------------------------------------------------===// 333239310Sdim// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32> 334239310Sdim//===----------------------------------------------------------------------===// 335239310Sdim 336239310Sdimclass FI8_MOVR3216<dag outs, dag ins, string asmstr, 337239310Sdim list<dag> pattern, InstrItinClass itin>: 338249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 339239310Sdim{ 340239310Sdim 341239310Sdim bits<4> ry; 342239310Sdim bits<4> r32; 343239310Sdim 344239310Sdim let Opcode = 0b01100; 345239310Sdim 346239310Sdim let Inst{10-8} = 0b111; 347239310Sdim let Inst{7-4} = ry; 348239310Sdim let Inst{3-0} = r32; 349239310Sdim 350239310Sdim} 351239310Sdim 352239310Sdim 353239310Sdim 354239310Sdim//===----------------------------------------------------------------------===// 355239310Sdim// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz> 356239310Sdim//===----------------------------------------------------------------------===// 357239310Sdim 358239310Sdimclass FI8_MOV32R16<dag outs, dag ins, string asmstr, 359239310Sdim list<dag> pattern, InstrItinClass itin>: 360249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 361239310Sdim{ 362239310Sdim 363239310Sdim bits<3> func; 364239310Sdim bits<5> r32; 365239310Sdim bits<3> rz; 366239310Sdim 367239310Sdim 368239310Sdim let Opcode = 0b01100; 369239310Sdim 370239310Sdim let Inst{10-8} = 0b101; 371239310Sdim let Inst{7-5} = r32{2-0}; 372239310Sdim let Inst{4-3} = r32{4-3}; 373239310Sdim let Inst{2-0} = rz; 374239310Sdim 375239310Sdim} 376239310Sdim 377239310Sdim//===----------------------------------------------------------------------===// 378239310Sdim// Format i8_SVRS instruction class in Mips : 379239310Sdim// <|opcode|svrs|s|ra|s0|s1|framesize> 380239310Sdim//===----------------------------------------------------------------------===// 381239310Sdim 382239310Sdimclass FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr, 383239310Sdim list<dag> pattern, InstrItinClass itin>: 384249423Sdim MipsInst16<outs, ins, asmstr, pattern, itin> 385239310Sdim{ 386239310Sdim bits<1> s; 387239310Sdim bits<1> ra = 0; 388239310Sdim bits<1> s0 = 0; 389239310Sdim bits<1> s1 = 0; 390239310Sdim bits<4> framesize = 0; 391239310Sdim 392239310Sdim let s =_s; 393239310Sdim let Opcode = 0b01100; 394239310Sdim 395239310Sdim let Inst{10-8} = 0b100; 396239310Sdim let Inst{7} = s; 397239310Sdim let Inst{6} = ra; 398239310Sdim let Inst{5} = s0; 399239310Sdim let Inst{4} = s1; 400239310Sdim let Inst{3-0} = framesize; 401239310Sdim 402239310Sdim} 403239310Sdim 404239310Sdim//===----------------------------------------------------------------------===// 405239310Sdim// Format JAL instruction class in Mips16 : 406239310Sdim// <|opcode|svrs|s|ra|s0|s1|framesize> 407239310Sdim//===----------------------------------------------------------------------===// 408239310Sdim 409239310Sdimclass FJAL16<bits<1> _X, dag outs, dag ins, string asmstr, 410239310Sdim list<dag> pattern, InstrItinClass itin>: 411249423Sdim MipsInst16_32<outs, ins, asmstr, pattern, itin> 412239310Sdim{ 413239310Sdim bits<1> X; 414239310Sdim bits<26> imm26; 415239310Sdim 416239310Sdim 417239310Sdim let X = _X; 418239310Sdim 419239310Sdim let Inst{31-27} = 0b00011; 420239310Sdim let Inst{26} = X; 421239310Sdim let Inst{25-21} = imm26{20-16}; 422239310Sdim let Inst{20-16} = imm26{25-21}; 423239310Sdim let Inst{15-0} = imm26{15-0}; 424239310Sdim 425239310Sdim} 426239310Sdim 427239310Sdim//===----------------------------------------------------------------------===// 428239310Sdim// Format EXT-I instruction class in Mips16 : 429239310Sdim// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0> 430239310Sdim//===----------------------------------------------------------------------===// 431239310Sdim 432239310Sdimclass FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr, 433239310Sdim list<dag> pattern, InstrItinClass itin>: 434249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 435239310Sdim{ 436239310Sdim bits<16> imm16; 437239310Sdim bits<5> eop; 438239310Sdim 439239310Sdim let eop = _eop; 440239310Sdim 441239310Sdim let Inst{26-21} = imm16{10-5}; 442239310Sdim let Inst{20-16} = imm16{15-11}; 443239310Sdim let Inst{15-11} = eop; 444239310Sdim let Inst{10-5} = 0; 445239310Sdim let Inst{4-0} = imm16{4-0}; 446239310Sdim 447239310Sdim} 448239310Sdim 449239310Sdim//===----------------------------------------------------------------------===// 450239310Sdim// Format ASMACRO instruction class in Mips16 : 451239310Sdim// <EXTEND|select|p4|p3|RRR|p2|p1|p0> 452239310Sdim//===----------------------------------------------------------------------===// 453239310Sdim 454239310Sdimclass FASMACRO16<dag outs, dag ins, string asmstr, 455239310Sdim list<dag> pattern, InstrItinClass itin>: 456249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 457239310Sdim{ 458239310Sdim bits<3> select; 459239310Sdim bits<3> p4; 460239310Sdim bits<5> p3; 461239310Sdim bits<5> RRR = 0b11100; 462239310Sdim bits<3> p2; 463239310Sdim bits<3> p1; 464239310Sdim bits<5> p0; 465239310Sdim 466239310Sdim 467239310Sdim let Inst{26-24} = select; 468239310Sdim let Inst{23-21} = p4; 469239310Sdim let Inst{20-16} = p3; 470239310Sdim let Inst{15-11} = RRR; 471239310Sdim let Inst{10-8} = p2; 472239310Sdim let Inst{7-5} = p1; 473239310Sdim let Inst{4-0} = p0; 474239310Sdim 475239310Sdim} 476239310Sdim 477239310Sdim 478239310Sdim//===----------------------------------------------------------------------===// 479239310Sdim// Format EXT-RI instruction class in Mips16 : 480239310Sdim// <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0> 481239310Sdim//===----------------------------------------------------------------------===// 482239310Sdim 483239310Sdimclass FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr, 484239310Sdim list<dag> pattern, InstrItinClass itin>: 485249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 486239310Sdim{ 487239310Sdim bits<16> imm16; 488239310Sdim bits<5> op; 489239310Sdim bits<3> rx; 490239310Sdim 491239310Sdim let op = _op; 492239310Sdim 493239310Sdim let Inst{26-21} = imm16{10-5}; 494239310Sdim let Inst{20-16} = imm16{15-11}; 495239310Sdim let Inst{15-11} = op; 496239310Sdim let Inst{10-8} = rx; 497239310Sdim let Inst{7-5} = 0; 498239310Sdim let Inst{4-0} = imm16{4-0}; 499239310Sdim 500239310Sdim} 501239310Sdim 502239310Sdim//===----------------------------------------------------------------------===// 503239310Sdim// Format EXT-RRI instruction class in Mips16 : 504239310Sdim// <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0> 505239310Sdim//===----------------------------------------------------------------------===// 506239310Sdim 507239310Sdimclass FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr, 508239310Sdim list<dag> pattern, InstrItinClass itin>: 509249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 510239310Sdim{ 511239310Sdim bits<5> op; 512239310Sdim bits<16> imm16; 513239310Sdim bits<3> rx; 514239310Sdim bits<3> ry; 515239310Sdim 516239310Sdim let op=_op; 517239310Sdim 518239310Sdim let Inst{26-21} = imm16{10-5}; 519239310Sdim let Inst{20-16} = imm16{15-11}; 520239310Sdim let Inst{15-11} = op; 521239310Sdim let Inst{10-8} = rx; 522239310Sdim let Inst{7-5} = ry; 523239310Sdim let Inst{4-0} = imm16{4-0}; 524239310Sdim 525239310Sdim} 526239310Sdim 527239310Sdim//===----------------------------------------------------------------------===// 528239310Sdim// Format EXT-RRI-A instruction class in Mips16 : 529239310Sdim// <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0> 530239310Sdim//===----------------------------------------------------------------------===// 531239310Sdim 532239310Sdimclass FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr, 533239310Sdim list<dag> pattern, InstrItinClass itin>: 534249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 535239310Sdim{ 536239310Sdim bits<15> imm15; 537239310Sdim bits<3> rx; 538239310Sdim bits<3> ry; 539239310Sdim bits<1> f; 540239310Sdim 541239310Sdim let f = _f; 542239310Sdim 543239310Sdim let Inst{26-20} = imm15{10-4}; 544239310Sdim let Inst{19-16} = imm15{14-11}; 545239310Sdim let Inst{15-11} = 0b01000; 546239310Sdim let Inst{10-8} = rx; 547239310Sdim let Inst{7-5} = ry; 548239310Sdim let Inst{4} = f; 549239310Sdim let Inst{3-0} = imm15{3-0}; 550239310Sdim 551239310Sdim} 552239310Sdim 553239310Sdim//===----------------------------------------------------------------------===// 554239310Sdim// Format EXT-SHIFT instruction class in Mips16 : 555239310Sdim// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f> 556239310Sdim//===----------------------------------------------------------------------===// 557239310Sdim 558239310Sdimclass FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr, 559239310Sdim list<dag> pattern, InstrItinClass itin>: 560249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 561239310Sdim{ 562239310Sdim bits<6> sa6; 563239310Sdim bits<3> rx; 564239310Sdim bits<3> ry; 565239310Sdim bits<2> f; 566239310Sdim 567239310Sdim let f = _f; 568239310Sdim 569239310Sdim let Inst{26-22} = sa6{4-0}; 570239310Sdim let Inst{21} = sa6{5}; 571239310Sdim let Inst{20-16} = 0; 572239310Sdim let Inst{15-11} = 0b00110; 573239310Sdim let Inst{10-8} = rx; 574239310Sdim let Inst{7-5} = ry; 575239310Sdim let Inst{4-2} = 0; 576239310Sdim let Inst{1-0} = f; 577239310Sdim 578239310Sdim} 579239310Sdim 580239310Sdim//===----------------------------------------------------------------------===// 581239310Sdim// Format EXT-I8 instruction class in Mips16 : 582239310Sdim// <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0> 583239310Sdim//===----------------------------------------------------------------------===// 584239310Sdim 585239310Sdimclass FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr, 586239310Sdim list<dag> pattern, InstrItinClass itin>: 587249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 588239310Sdim{ 589239310Sdim bits<16> imm16; 590239310Sdim bits<5> I8; 591239310Sdim bits<3> funct; 592239310Sdim 593239310Sdim let funct = _funct; 594239310Sdim let I8 = 0b0110; 595239310Sdim 596239310Sdim let Inst{26-21} = imm16{10-5}; 597239310Sdim let Inst{20-16} = imm16{15-11}; 598239310Sdim let Inst{15-11} = I8; 599239310Sdim let Inst{10-8} = funct; 600239310Sdim let Inst{7-5} = 0; 601239310Sdim let Inst{4-0} = imm16{4-0}; 602239310Sdim 603239310Sdim} 604239310Sdim 605239310Sdim//===----------------------------------------------------------------------===// 606239310Sdim// Format EXT-I8_SVRS instruction class in Mips16 : 607239310Sdim// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0> 608239310Sdim//===----------------------------------------------------------------------===// 609239310Sdim 610239310Sdimclass FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr, 611239310Sdim list<dag> pattern, InstrItinClass itin>: 612249423Sdim MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin> 613239310Sdim{ 614239310Sdim bits<3> xsregs =0; 615239310Sdim bits<8> framesize =0; 616239310Sdim bits<3> aregs =0; 617239310Sdim bits<5> I8 = 0b01100; 618239310Sdim bits<3> SVRS = 0b100; 619239310Sdim bits<1> s; 620239310Sdim bits<1> ra = 0; 621239310Sdim bits<1> s0 = 0; 622239310Sdim bits<1> s1 = 0; 623239310Sdim 624239310Sdim let s= s_; 625239310Sdim 626239310Sdim let Inst{26-24} = xsregs; 627239310Sdim let Inst{23-20} = framesize{7-4}; 628239310Sdim let Inst{19} = 0; 629239310Sdim let Inst{18-16} = aregs; 630239310Sdim let Inst{15-11} = I8; 631239310Sdim let Inst{10-8} = SVRS; 632239310Sdim let Inst{7} = s; 633239310Sdim let Inst{6} = ra; 634239310Sdim let Inst{5} = s0; 635239310Sdim let Inst{4} = s1; 636239310Sdim let Inst{3-0} = framesize{3-0}; 637239310Sdim 638239310Sdim 639239310Sdim} 640239310Sdim 641