Mips.td revision 263508
1179055Sjfv//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2171384Sjfv// 3190873Sjfv// The LLVM Compiler Infrastructure 4171384Sjfv// 5171384Sjfv// This file is distributed under the University of Illinois Open Source 6171384Sjfv// License. See LICENSE.TXT for details. 7171384Sjfv// 8171384Sjfv//===----------------------------------------------------------------------===// 9171384Sjfv// This is the top level entry point for the Mips target. 10171384Sjfv//===----------------------------------------------------------------------===// 11171384Sjfv 12171384Sjfv//===----------------------------------------------------------------------===// 13171384Sjfv// Target-independent interfaces 14171384Sjfv//===----------------------------------------------------------------------===// 15171384Sjfv 16171384Sjfvinclude "llvm/Target/Target.td" 17171384Sjfv 18171384Sjfv//===----------------------------------------------------------------------===// 19171384Sjfv// Register File, Calling Conv, Instruction Descriptions 20171384Sjfv//===----------------------------------------------------------------------===// 21171384Sjfv 22171384Sjfvinclude "MipsRegisterInfo.td" 23171384Sjfvinclude "MipsSchedule.td" 24171384Sjfvinclude "MipsInstrInfo.td" 25171384Sjfvinclude "MipsCallingConv.td" 26171384Sjfv 27171384Sjfvdef MipsInstrInfo : InstrInfo; 28171384Sjfv 29171384Sjfv//===----------------------------------------------------------------------===// 30171384Sjfv// Mips Subtarget features // 31171384Sjfv//===----------------------------------------------------------------------===// 32179055Sjfv 33179055Sjfvdef FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 34171384Sjfv "General Purpose Registers are 64-bit wide.">; 35171384Sjfvdef FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 36171384Sjfv "Support 64-bit FP registers.">; 37171384Sjfvdef FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 38171384Sjfv "true", "Only supports single precision float">; 39190873Sjfvdef FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 40190873Sjfv "Enable o32 ABI">; 41190873Sjfvdef FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 42190873Sjfv "Enable n32 ABI">; 43190873Sjfvdef FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 44171384Sjfv "Enable n64 ABI">; 45200239Sjfvdef FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 46200239Sjfv "Enable eabi ABI">; 47179055Sjfvdef FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 48171384Sjfv "true", "Enable vector FPU instructions.">; 49171384Sjfvdef FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 50171384Sjfv "Enable 'signext in register' instructions.">; 51179055Sjfvdef FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 52171384Sjfv "Enable 'conditional move' instructions.">; 53171384Sjfvdef FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 54185352Sjfv "Enable 'byte/half swap' instructions.">; 55171384Sjfvdef FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 56171384Sjfv "Enable 'count leading bits' instructions.">; 57171384Sjfvdef FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", 58171384Sjfv "Enable 'FP indexed load/store' instructions.">; 59171384Sjfvdef FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 60171384Sjfv "Mips32 ISA Support", 61171384Sjfv [FeatureCondMov, FeatureBitCount]>; 62200239Sjfvdef FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 63171384Sjfv "Mips32r2", "Mips32r2 ISA Support", 64179055Sjfv [FeatureMips32, FeatureSEInReg, FeatureSwap, 65200239Sjfv FeatureFPIdx]>; 66171384Sjfvdef FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 67179055Sjfv "Mips64", "Mips64 ISA Support", 68171384Sjfv [FeatureGP64Bit, FeatureFP64Bit, 69200239Sjfv FeatureMips32, FeatureFPIdx]>; 70171384Sjfvdef FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 71179055Sjfv "Mips64r2", "Mips64r2 ISA Support", 72179055Sjfv [FeatureMips64, FeatureMips32r2]>; 73181003Sjfv 74171384Sjfvdef FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 75171384Sjfv "Mips16 mode">; 76179055Sjfv 77179055Sjfvdef FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 78179055Sjfvdef FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 79179055Sjfv "Mips DSP-R2 ASE", [FeatureDSP]>; 80171384Sjfv 81171384Sjfvdef FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 82190873Sjfv 83171384Sjfvdef FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 84190873Sjfv "microMips mode">; 85190873Sjfv 86185352Sjfv//===----------------------------------------------------------------------===// 87185352Sjfv// Mips processors supported. 88171384Sjfv//===----------------------------------------------------------------------===// 89171384Sjfv 90171384Sjfvclass Proc<string Name, list<SubtargetFeature> Features> 91171384Sjfv : Processor<Name, MipsGenericItineraries, Features>; 92171384Sjfv 93190873Sjfvdef : Proc<"mips32", [FeatureMips32]>; 94190873Sjfvdef : Proc<"mips32r2", [FeatureMips32r2]>; 95190873Sjfvdef : Proc<"mips64", [FeatureMips64]>; 96200239Sjfvdef : Proc<"mips64r2", [FeatureMips64r2]>; 97200239Sjfvdef : Proc<"mips16", [FeatureMips16]>; 98200239Sjfv 99200239Sjfvdef MipsAsmWriter : AsmWriter { 100200239Sjfv string AsmWriterClassName = "InstPrinter"; 101200239Sjfv bit isMCAsmWriter = 1; 102200239Sjfv} 103200239Sjfv 104200239Sjfvdef MipsAsmParser : AsmParser { 105200239Sjfv let ShouldEmitMatchRegisterName = 0; 106200239Sjfv let MnemonicContainsDot = 1; 107200239Sjfv} 108200239Sjfv 109200239Sjfvdef MipsAsmParserVariant : AsmParserVariant { 110200239Sjfv int Variant = 0; 111200239Sjfv 112200239Sjfv // Recognize hard coded registers. 113200239Sjfv string RegisterPrefix = "$"; 114171384Sjfv} 115 116def Mips : Target { 117 let InstructionSet = MipsInstrInfo; 118 let AssemblyParsers = [MipsAsmParser]; 119 let AssemblyWriters = [MipsAsmWriter]; 120 let AssemblyParserVariants = [MipsAsmParserVariant]; 121} 122