1234353Sdim//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// This is the top level entry point for the Mips target. 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed// Target-independent interfaces 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sedinclude "llvm/Target/Target.td" 17193323Sed 18193323Sed//===----------------------------------------------------------------------===// 19193323Sed// Register File, Calling Conv, Instruction Descriptions 20193323Sed//===----------------------------------------------------------------------===// 21193323Sed 22193323Sedinclude "MipsRegisterInfo.td" 23193323Sedinclude "MipsSchedule.td" 24193323Sedinclude "MipsInstrInfo.td" 25193323Sedinclude "MipsCallingConv.td" 26193323Sed 27206274Srdivackydef MipsInstrInfo : InstrInfo; 28193323Sed 29193323Sed//===----------------------------------------------------------------------===// 30193323Sed// Mips Subtarget features // 31193323Sed//===----------------------------------------------------------------------===// 32193323Sed 33193323Seddef FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 34193323Sed "General Purpose Registers are 64-bit wide.">; 35193323Seddef FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 36193323Sed "Support 64-bit FP registers.">; 37193323Seddef FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 38193323Sed "true", "Only supports single precision float">; 39193323Seddef FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 40193323Sed "Enable o32 ABI">; 41226633Sdimdef FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 42226633Sdim "Enable n32 ABI">; 43226633Sdimdef FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 44226633Sdim "Enable n64 ABI">; 45193323Seddef FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 46193323Sed "Enable eabi ABI">; 47218893Sdimdef FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 48193323Sed "true", "Enable vector FPU instructions.">; 49218893Sdimdef FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 50193323Sed "Enable 'signext in register' instructions.">; 51218893Sdimdef FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 52193323Sed "Enable 'conditional move' instructions.">; 53193323Seddef FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 54193323Sed "Enable 'byte/half swap' instructions.">; 55193323Seddef FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 56193323Sed "Enable 'count leading bits' instructions.">; 57249423Sdimdef FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", 58249423Sdim "Enable 'FP indexed load/store' instructions.">; 59218893Sdimdef FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 60221345Sdim "Mips32 ISA Support", 61218893Sdim [FeatureCondMov, FeatureBitCount]>; 62218893Sdimdef FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 63218893Sdim "Mips32r2", "Mips32r2 ISA Support", 64249423Sdim [FeatureMips32, FeatureSEInReg, FeatureSwap, 65249423Sdim FeatureFPIdx]>; 66226633Sdimdef FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 67226633Sdim "Mips64", "Mips64 ISA Support", 68226633Sdim [FeatureGP64Bit, FeatureFP64Bit, 69249423Sdim FeatureMips32, FeatureFPIdx]>; 70226633Sdimdef FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 71226633Sdim "Mips64r2", "Mips64r2 ISA Support", 72226633Sdim [FeatureMips64, FeatureMips32r2]>; 73193323Sed 74239462Sdimdef FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 75239462Sdim "Mips16 mode">; 76239462Sdim 77243830Sdimdef FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 78243830Sdimdef FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 79243830Sdim "Mips DSP-R2 ASE", [FeatureDSP]>; 80243830Sdim 81263508Sdimdef FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 82263508Sdim 83249423Sdimdef FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 84249423Sdim "microMips mode">; 85249423Sdim 86193323Sed//===----------------------------------------------------------------------===// 87193323Sed// Mips processors supported. 88193323Sed//===----------------------------------------------------------------------===// 89193323Sed 90193323Sedclass Proc<string Name, list<SubtargetFeature> Features> 91193323Sed : Processor<Name, MipsGenericItineraries, Features>; 92193323Sed 93234353Sdimdef : Proc<"mips32", [FeatureMips32]>; 94234353Sdimdef : Proc<"mips32r2", [FeatureMips32r2]>; 95234353Sdimdef : Proc<"mips64", [FeatureMips64]>; 96226633Sdimdef : Proc<"mips64r2", [FeatureMips64r2]>; 97239462Sdimdef : Proc<"mips16", [FeatureMips16]>; 98218893Sdim 99224145Sdimdef MipsAsmWriter : AsmWriter { 100224145Sdim string AsmWriterClassName = "InstPrinter"; 101224145Sdim bit isMCAsmWriter = 1; 102224145Sdim} 103224145Sdim 104243830Sdimdef MipsAsmParser : AsmParser { 105243830Sdim let ShouldEmitMatchRegisterName = 0; 106263508Sdim let MnemonicContainsDot = 1; 107243830Sdim} 108243830Sdim 109243830Sdimdef MipsAsmParserVariant : AsmParserVariant { 110243830Sdim int Variant = 0; 111243830Sdim 112243830Sdim // Recognize hard coded registers. 113243830Sdim string RegisterPrefix = "$"; 114243830Sdim} 115243830Sdim 116193323Seddef Mips : Target { 117193323Sed let InstructionSet = MipsInstrInfo; 118243830Sdim let AssemblyParsers = [MipsAsmParser]; 119224145Sdim let AssemblyWriters = [MipsAsmWriter]; 120243830Sdim let AssemblyParserVariants = [MipsAsmParserVariant]; 121193323Sed} 122