1259698SdimCode Generation Notes for MSA 2259698Sdim============================= 3259698Sdim 4259698SdimIntrinsics are lowered to SelectionDAG nodes where possible in order to enable 5259698Sdimoptimisation, reduce the size of the ISel matcher, and reduce repetition in 6259698Sdimthe implementation. In a small number of cases, this can cause different 7259698Sdim(semantically equivalent) instructions to be used in place of the requested 8259698Sdiminstruction, even when no optimisation has taken place. 9259698Sdim 10259698SdimInstructions 11259698Sdim============ 12259698Sdim 13259698SdimThis section describes any quirks of instruction selection for MSA. For 14259698Sdimexample, two instructions might be equally valid for some given IR and one is 15259698Sdimchosen in preference to the other. 16259698Sdim 17259698Sdimbclri.b: 18259698Sdim It is not possible to emit bclri.b since andi.b covers exactly the 19259698Sdim same cases. andi.b should use fractionally less power than bclri.b in 20259698Sdim most hardware implementations so it is used in preference to bclri.b. 21259698Sdim 22259698Sdimvshf.w: 23259698Sdim It is not possible to emit vshf.w when the shuffle description is 24259698Sdim constant since shf.w covers exactly the same cases. shf.w is used 25259698Sdim instead. It is also impossible for the shuffle description to be 26259698Sdim unknown at compile-time due to the definition of shufflevector in 27259698Sdim LLVM IR. 28259698Sdim 29259698Sdimvshf.[bhwd] 30259698Sdim When the shuffle description describes a splat operation, splat.[bhwd] 31259698Sdim instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*, 32259698Sdim and pck* instructions, this is matched from MipsISD::VSHF instead of 33259698Sdim a special-case MipsISD node. 34259698Sdim 35259698Sdimilvl.d, pckev.d: 36259698Sdim It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the 37259698Sdim same shuffle. ilvev.d will be emitted instead. 38259698Sdim 39259698Sdimilvr.d, ilvod.d, pckod.d: 40259698Sdim It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the 41259698Sdim same shuffle. ilvod.d will be emitted instead. 42259698Sdim 43259698Sdimsplat.[bhwd] 44259698Sdim The intrinsic will work as expected. However, unlike other intrinsics 45259698Sdim it lowers directly to MipsISD::VSHF instead of using common IR. 46259698Sdim 47259698Sdimsplati.w: 48259698Sdim It is not possible to emit splati.w since shf.w covers the same cases. 49259698Sdim shf.w will be emitted instead. 50259698Sdim 51259698Sdimcopy_s.w: 52259698Sdim On MIPS32, the copy_u.d intrinsic will emit this instruction instead of 53259698Sdim copy_u.w. This is semantically equivalent since the general-purpose 54259698Sdim register file is 32-bits wide. 55259698Sdim 56259698Sdimbinsri.[bhwd], binsli.[bhwd]: 57259698Sdim These two operations are equivalent to each other with the operands 58259698Sdim swapped and condition inverted. The compiler may use either one as 59259698Sdim appropriate. 60259698Sdim Furthermore, the compiler may use bsel.[bhwd] for some masks that do 61259698Sdim not survive the legalization process (this is a bug and will be fixed). 62259698Sdim 63259698Sdimbmnz.v, bmz.v, bsel.v: 64259698Sdim These three operations differ only in the operand that is tied to the 65259698Sdim result. 66259698Sdim It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is 67259698Sdim the same operation and will be emitted instead. 68259698Sdim In future, the compiler may choose between these three instructions 69259698Sdim according to register allocation. 70259698Sdim 71259698Sdimbmnzi.b, bmzi.b: 72259698Sdim Like their non-immediate counterparts, bmnzi.v and bmzi.v are the same 73259698Sdim operation with the operands swapped. bmnzi.v will (currently) be emitted 74259698Sdim for both cases. 75259698Sdim 76259698Sdimbseli.v: 77259698Sdim Unlike the non-immediate versions, bseli.v is distinguishable from 78259698Sdim bmnzi.b and bmzi.b and can be emitted. 79