MSP430ISelLowering.cpp revision 193323
1193323Sed//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file implements the MSP430TargetLowering class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#define DEBUG_TYPE "msp430-lower" 15193323Sed 16193323Sed#include "MSP430ISelLowering.h" 17193323Sed#include "MSP430.h" 18193323Sed#include "MSP430TargetMachine.h" 19193323Sed#include "MSP430Subtarget.h" 20193323Sed#include "llvm/DerivedTypes.h" 21193323Sed#include "llvm/Function.h" 22193323Sed#include "llvm/Intrinsics.h" 23193323Sed#include "llvm/CallingConv.h" 24193323Sed#include "llvm/GlobalVariable.h" 25193323Sed#include "llvm/GlobalAlias.h" 26193323Sed#include "llvm/CodeGen/CallingConvLower.h" 27193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 28193323Sed#include "llvm/CodeGen/MachineFunction.h" 29193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 30193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 31193323Sed#include "llvm/CodeGen/PseudoSourceValue.h" 32193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 33193323Sed#include "llvm/CodeGen/ValueTypes.h" 34193323Sed#include "llvm/Support/Debug.h" 35193323Sed#include "llvm/ADT/VectorExtras.h" 36193323Sedusing namespace llvm; 37193323Sed 38193323SedMSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : 39193323Sed TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) { 40193323Sed 41193323Sed // Set up the register classes. 42193323Sed addRegisterClass(MVT::i8, MSP430::GR8RegisterClass); 43193323Sed addRegisterClass(MVT::i16, MSP430::GR16RegisterClass); 44193323Sed 45193323Sed // Compute derived properties from the register classes 46193323Sed computeRegisterProperties(); 47193323Sed 48193323Sed // Provide all sorts of operation actions 49193323Sed 50193323Sed // Division is expensive 51193323Sed setIntDivIsCheap(false); 52193323Sed 53193323Sed // Even if we have only 1 bit shift here, we can perform 54193323Sed // shifts of the whole bitwidth 1 bit per step. 55193323Sed setShiftAmountType(MVT::i8); 56193323Sed 57193323Sed setStackPointerRegisterToSaveRestore(MSP430::SPW); 58193323Sed setBooleanContents(ZeroOrOneBooleanContent); 59193323Sed setSchedulingPreference(SchedulingForLatency); 60193323Sed 61193323Sed setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 62193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 63193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 64193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 65193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); 66193323Sed 67193323Sed // We don't have any truncstores 68193323Sed setTruncStoreAction(MVT::i16, MVT::i8, Expand); 69193323Sed 70193323Sed setOperationAction(ISD::SRA, MVT::i8, Custom); 71193323Sed setOperationAction(ISD::SHL, MVT::i8, Custom); 72193323Sed setOperationAction(ISD::SRL, MVT::i8, Custom); 73193323Sed setOperationAction(ISD::SRA, MVT::i16, Custom); 74193323Sed setOperationAction(ISD::SHL, MVT::i16, Custom); 75193323Sed setOperationAction(ISD::SRL, MVT::i16, Custom); 76193323Sed setOperationAction(ISD::ROTL, MVT::i8, Expand); 77193323Sed setOperationAction(ISD::ROTR, MVT::i8, Expand); 78193323Sed setOperationAction(ISD::ROTL, MVT::i16, Expand); 79193323Sed setOperationAction(ISD::ROTR, MVT::i16, Expand); 80193323Sed setOperationAction(ISD::RET, MVT::Other, Custom); 81193323Sed setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 82193323Sed setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); 83193323Sed setOperationAction(ISD::BR_JT, MVT::Other, Expand); 84193323Sed setOperationAction(ISD::BRIND, MVT::Other, Expand); 85193323Sed setOperationAction(ISD::BR_CC, MVT::i8, Custom); 86193323Sed setOperationAction(ISD::BR_CC, MVT::i16, Custom); 87193323Sed setOperationAction(ISD::BRCOND, MVT::Other, Expand); 88193323Sed setOperationAction(ISD::SETCC, MVT::i8, Expand); 89193323Sed setOperationAction(ISD::SETCC, MVT::i16, Expand); 90193323Sed setOperationAction(ISD::SELECT, MVT::i8, Expand); 91193323Sed setOperationAction(ISD::SELECT, MVT::i16, Expand); 92193323Sed setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 93193323Sed setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 94193323Sed setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); 95193323Sed 96193323Sed // FIXME: Implement efficiently multiplication by a constant 97193323Sed setOperationAction(ISD::MUL, MVT::i16, Expand); 98193323Sed setOperationAction(ISD::MULHS, MVT::i16, Expand); 99193323Sed setOperationAction(ISD::MULHU, MVT::i16, Expand); 100193323Sed setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 101193323Sed setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 102193323Sed 103193323Sed setOperationAction(ISD::UDIV, MVT::i16, Expand); 104193323Sed setOperationAction(ISD::UDIVREM, MVT::i16, Expand); 105193323Sed setOperationAction(ISD::UREM, MVT::i16, Expand); 106193323Sed setOperationAction(ISD::SDIV, MVT::i16, Expand); 107193323Sed setOperationAction(ISD::SDIVREM, MVT::i16, Expand); 108193323Sed setOperationAction(ISD::SREM, MVT::i16, Expand); 109193323Sed} 110193323Sed 111193323SedSDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 112193323Sed switch (Op.getOpcode()) { 113193323Sed case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 114193323Sed case ISD::SHL: // FALLTHROUGH 115193323Sed case ISD::SRL: 116193323Sed case ISD::SRA: return LowerShifts(Op, DAG); 117193323Sed case ISD::RET: return LowerRET(Op, DAG); 118193323Sed case ISD::CALL: return LowerCALL(Op, DAG); 119193323Sed case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 120193323Sed case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 121193323Sed case ISD::BR_CC: return LowerBR_CC(Op, DAG); 122193323Sed case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 123193323Sed case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); 124193323Sed default: 125193323Sed assert(0 && "unimplemented operand"); 126193323Sed return SDValue(); 127193323Sed } 128193323Sed} 129193323Sed 130193323Sed//===----------------------------------------------------------------------===// 131193323Sed// Calling Convention Implementation 132193323Sed//===----------------------------------------------------------------------===// 133193323Sed 134193323Sed#include "MSP430GenCallingConv.inc" 135193323Sed 136193323SedSDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, 137193323Sed SelectionDAG &DAG) { 138193323Sed unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 139193323Sed switch (CC) { 140193323Sed default: 141193323Sed assert(0 && "Unsupported calling convention"); 142193323Sed case CallingConv::C: 143193323Sed case CallingConv::Fast: 144193323Sed return LowerCCCArguments(Op, DAG); 145193323Sed } 146193323Sed} 147193323Sed 148193323SedSDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 149193323Sed CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 150193323Sed unsigned CallingConv = TheCall->getCallingConv(); 151193323Sed switch (CallingConv) { 152193323Sed default: 153193323Sed assert(0 && "Unsupported calling convention"); 154193323Sed case CallingConv::Fast: 155193323Sed case CallingConv::C: 156193323Sed return LowerCCCCallTo(Op, DAG, CallingConv); 157193323Sed } 158193323Sed} 159193323Sed 160193323Sed/// LowerCCCArguments - transform physical registers into virtual registers and 161193323Sed/// generate load operations for arguments places on the stack. 162193323Sed// FIXME: struct return stuff 163193323Sed// FIXME: varargs 164193323SedSDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op, 165193323Sed SelectionDAG &DAG) { 166193323Sed MachineFunction &MF = DAG.getMachineFunction(); 167193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 168193323Sed MachineRegisterInfo &RegInfo = MF.getRegInfo(); 169193323Sed SDValue Root = Op.getOperand(0); 170193323Sed bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 171193323Sed unsigned CC = MF.getFunction()->getCallingConv(); 172193323Sed DebugLoc dl = Op.getDebugLoc(); 173193323Sed 174193323Sed // Assign locations to all of the incoming arguments. 175193323Sed SmallVector<CCValAssign, 16> ArgLocs; 176193323Sed CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 177193323Sed CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430); 178193323Sed 179193323Sed assert(!isVarArg && "Varargs not supported yet"); 180193323Sed 181193323Sed SmallVector<SDValue, 16> ArgValues; 182193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 183193323Sed CCValAssign &VA = ArgLocs[i]; 184193323Sed if (VA.isRegLoc()) { 185193323Sed // Arguments passed in registers 186193323Sed MVT RegVT = VA.getLocVT(); 187193323Sed switch (RegVT.getSimpleVT()) { 188193323Sed default: 189193323Sed cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " 190193323Sed << RegVT.getSimpleVT() 191193323Sed << "\n"; 192193323Sed abort(); 193193323Sed case MVT::i16: 194193323Sed unsigned VReg = 195193323Sed RegInfo.createVirtualRegister(MSP430::GR16RegisterClass); 196193323Sed RegInfo.addLiveIn(VA.getLocReg(), VReg); 197193323Sed SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT); 198193323Sed 199193323Sed // If this is an 8-bit value, it is really passed promoted to 16 200193323Sed // bits. Insert an assert[sz]ext to capture this, then truncate to the 201193323Sed // right size. 202193323Sed if (VA.getLocInfo() == CCValAssign::SExt) 203193323Sed ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 204193323Sed DAG.getValueType(VA.getValVT())); 205193323Sed else if (VA.getLocInfo() == CCValAssign::ZExt) 206193323Sed ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 207193323Sed DAG.getValueType(VA.getValVT())); 208193323Sed 209193323Sed if (VA.getLocInfo() != CCValAssign::Full) 210193323Sed ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 211193323Sed 212193323Sed ArgValues.push_back(ArgValue); 213193323Sed } 214193323Sed } else { 215193323Sed // Sanity check 216193323Sed assert(VA.isMemLoc()); 217193323Sed // Load the argument to a virtual register 218193323Sed unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 219193323Sed if (ObjSize > 2) { 220193323Sed cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: " 221193323Sed << VA.getLocVT().getSimpleVT() 222193323Sed << "\n"; 223193323Sed } 224193323Sed // Create the frame index object for this incoming parameter... 225193323Sed int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset()); 226193323Sed 227193323Sed // Create the SelectionDAG nodes corresponding to a load 228193323Sed //from this parameter 229193323Sed SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); 230193323Sed ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, 231193323Sed PseudoSourceValue::getFixedStack(FI), 0)); 232193323Sed } 233193323Sed } 234193323Sed 235193323Sed ArgValues.push_back(Root); 236193323Sed 237193323Sed // Return the new list of results. 238193323Sed return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 239193323Sed &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 240193323Sed} 241193323Sed 242193323SedSDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 243193323Sed // CCValAssign - represent the assignment of the return value to a location 244193323Sed SmallVector<CCValAssign, 16> RVLocs; 245193323Sed unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 246193323Sed bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 247193323Sed DebugLoc dl = Op.getDebugLoc(); 248193323Sed 249193323Sed // CCState - Info about the registers and stack slot. 250193323Sed CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 251193323Sed 252193323Sed // Analize return values of ISD::RET 253193323Sed CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430); 254193323Sed 255193323Sed // If this is the first return lowered for this function, add the regs to the 256193323Sed // liveout set for the function. 257193323Sed if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 258193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) 259193323Sed if (RVLocs[i].isRegLoc()) 260193323Sed DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 261193323Sed } 262193323Sed 263193323Sed // The chain is always operand #0 264193323Sed SDValue Chain = Op.getOperand(0); 265193323Sed SDValue Flag; 266193323Sed 267193323Sed // Copy the result values into the output registers. 268193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 269193323Sed CCValAssign &VA = RVLocs[i]; 270193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 271193323Sed 272193323Sed // ISD::RET => ret chain, (regnum1,val1), ... 273193323Sed // So i*2+1 index only the regnums 274193323Sed Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 275193323Sed Op.getOperand(i*2+1), Flag); 276193323Sed 277193323Sed // Guarantee that all emitted copies are stuck together, 278193323Sed // avoiding something bad. 279193323Sed Flag = Chain.getValue(1); 280193323Sed } 281193323Sed 282193323Sed if (Flag.getNode()) 283193323Sed return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 284193323Sed 285193323Sed // Return Void 286193323Sed return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain); 287193323Sed} 288193323Sed 289193323Sed/// LowerCCCCallTo - functions arguments are copied from virtual regs to 290193323Sed/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 291193323Sed/// TODO: sret. 292193323SedSDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, 293193323Sed unsigned CC) { 294193323Sed CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 295193323Sed SDValue Chain = TheCall->getChain(); 296193323Sed SDValue Callee = TheCall->getCallee(); 297193323Sed bool isVarArg = TheCall->isVarArg(); 298193323Sed DebugLoc dl = Op.getDebugLoc(); 299193323Sed 300193323Sed // Analyze operands of the call, assigning locations to each operand. 301193323Sed SmallVector<CCValAssign, 16> ArgLocs; 302193323Sed CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 303193323Sed 304193323Sed CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430); 305193323Sed 306193323Sed // Get a count of how many bytes are to be pushed on the stack. 307193323Sed unsigned NumBytes = CCInfo.getNextStackOffset(); 308193323Sed 309193323Sed Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 310193323Sed getPointerTy(), true)); 311193323Sed 312193323Sed SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 313193323Sed SmallVector<SDValue, 12> MemOpChains; 314193323Sed SDValue StackPtr; 315193323Sed 316193323Sed // Walk the register/memloc assignments, inserting copies/loads. 317193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 318193323Sed CCValAssign &VA = ArgLocs[i]; 319193323Sed 320193323Sed // Arguments start after the 5 first operands of ISD::CALL 321193323Sed SDValue Arg = TheCall->getArg(i); 322193323Sed 323193323Sed // Promote the value if needed. 324193323Sed switch (VA.getLocInfo()) { 325193323Sed default: assert(0 && "Unknown loc info!"); 326193323Sed case CCValAssign::Full: break; 327193323Sed case CCValAssign::SExt: 328193323Sed Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 329193323Sed break; 330193323Sed case CCValAssign::ZExt: 331193323Sed Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 332193323Sed break; 333193323Sed case CCValAssign::AExt: 334193323Sed Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 335193323Sed break; 336193323Sed } 337193323Sed 338193323Sed // Arguments that can be passed on register must be kept at RegsToPass 339193323Sed // vector 340193323Sed if (VA.isRegLoc()) { 341193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 342193323Sed } else { 343193323Sed assert(VA.isMemLoc()); 344193323Sed 345193323Sed if (StackPtr.getNode() == 0) 346193323Sed StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy()); 347193323Sed 348193323Sed SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 349193323Sed StackPtr, 350193323Sed DAG.getIntPtrConstant(VA.getLocMemOffset())); 351193323Sed 352193323Sed 353193323Sed MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 354193323Sed PseudoSourceValue::getStack(), 355193323Sed VA.getLocMemOffset())); 356193323Sed } 357193323Sed } 358193323Sed 359193323Sed // Transform all store nodes into one single node because all store nodes are 360193323Sed // independent of each other. 361193323Sed if (!MemOpChains.empty()) 362193323Sed Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 363193323Sed &MemOpChains[0], MemOpChains.size()); 364193323Sed 365193323Sed // Build a sequence of copy-to-reg nodes chained together with token chain and 366193323Sed // flag operands which copy the outgoing args into registers. The InFlag in 367193323Sed // necessary since all emited instructions must be stuck together. 368193323Sed SDValue InFlag; 369193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 370193323Sed Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 371193323Sed RegsToPass[i].second, InFlag); 372193323Sed InFlag = Chain.getValue(1); 373193323Sed } 374193323Sed 375193323Sed // If the callee is a GlobalAddress node (quite common, every direct call is) 376193323Sed // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 377193323Sed // Likewise ExternalSymbol -> TargetExternalSymbol. 378193323Sed if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 379193323Sed Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16); 380193323Sed else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 381193323Sed Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); 382193323Sed 383193323Sed // Returns a chain & a flag for retval copy to use. 384193323Sed SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); 385193323Sed SmallVector<SDValue, 8> Ops; 386193323Sed Ops.push_back(Chain); 387193323Sed Ops.push_back(Callee); 388193323Sed 389193323Sed // Add argument registers to the end of the list so that they are 390193323Sed // known live into the call. 391193323Sed for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 392193323Sed Ops.push_back(DAG.getRegister(RegsToPass[i].first, 393193323Sed RegsToPass[i].second.getValueType())); 394193323Sed 395193323Sed if (InFlag.getNode()) 396193323Sed Ops.push_back(InFlag); 397193323Sed 398193323Sed Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 399193323Sed InFlag = Chain.getValue(1); 400193323Sed 401193323Sed // Create the CALLSEQ_END node. 402193323Sed Chain = DAG.getCALLSEQ_END(Chain, 403193323Sed DAG.getConstant(NumBytes, getPointerTy(), true), 404193323Sed DAG.getConstant(0, getPointerTy(), true), 405193323Sed InFlag); 406193323Sed InFlag = Chain.getValue(1); 407193323Sed 408193323Sed // Handle result values, copying them out of physregs into vregs that we 409193323Sed // return. 410193323Sed return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 411193323Sed Op.getResNo()); 412193323Sed} 413193323Sed 414193323Sed/// LowerCallResult - Lower the result values of an ISD::CALL into the 415193323Sed/// appropriate copies out of appropriate physical registers. This assumes that 416193323Sed/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 417193323Sed/// being lowered. Returns a SDNode with the same number of values as the 418193323Sed/// ISD::CALL. 419193323SedSDNode* 420193323SedMSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 421193323Sed CallSDNode *TheCall, 422193323Sed unsigned CallingConv, 423193323Sed SelectionDAG &DAG) { 424193323Sed bool isVarArg = TheCall->isVarArg(); 425193323Sed DebugLoc dl = TheCall->getDebugLoc(); 426193323Sed 427193323Sed // Assign locations to each value returned by this call. 428193323Sed SmallVector<CCValAssign, 16> RVLocs; 429193323Sed CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 430193323Sed 431193323Sed CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430); 432193323Sed SmallVector<SDValue, 8> ResultVals; 433193323Sed 434193323Sed // Copy all of the result registers out of their specified physreg. 435193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 436193323Sed Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 437193323Sed RVLocs[i].getValVT(), InFlag).getValue(1); 438193323Sed InFlag = Chain.getValue(2); 439193323Sed ResultVals.push_back(Chain.getValue(0)); 440193323Sed } 441193323Sed 442193323Sed ResultVals.push_back(Chain); 443193323Sed 444193323Sed // Merge everything together with a MERGE_VALUES node. 445193323Sed return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 446193323Sed &ResultVals[0], ResultVals.size()).getNode(); 447193323Sed} 448193323Sed 449193323SedSDValue MSP430TargetLowering::LowerShifts(SDValue Op, 450193323Sed SelectionDAG &DAG) { 451193323Sed unsigned Opc = Op.getOpcode(); 452193323Sed SDNode* N = Op.getNode(); 453193323Sed MVT VT = Op.getValueType(); 454193323Sed DebugLoc dl = N->getDebugLoc(); 455193323Sed 456193323Sed // We currently only lower shifts of constant argument. 457193323Sed if (!isa<ConstantSDNode>(N->getOperand(1))) 458193323Sed return SDValue(); 459193323Sed 460193323Sed uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 461193323Sed 462193323Sed // Expand the stuff into sequence of shifts. 463193323Sed // FIXME: for some shift amounts this might be done better! 464193323Sed // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N 465193323Sed SDValue Victim = N->getOperand(0); 466193323Sed 467193323Sed if (Opc == ISD::SRL && ShiftAmount) { 468193323Sed // Emit a special goodness here: 469193323Sed // srl A, 1 => clrc; rrc A 470193323Sed Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); 471193323Sed ShiftAmount -= 1; 472193323Sed } 473193323Sed 474193323Sed while (ShiftAmount--) 475193323Sed Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 476193323Sed dl, VT, Victim); 477193323Sed 478193323Sed return Victim; 479193323Sed} 480193323Sed 481193323SedSDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { 482193323Sed const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 483193323Sed int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 484193323Sed 485193323Sed // Create the TargetGlobalAddress node, folding in the constant offset. 486193323Sed SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset); 487193323Sed return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(), 488193323Sed getPointerTy(), Result); 489193323Sed} 490193323Sed 491193323SedSDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, 492193323Sed SelectionDAG &DAG) { 493193323Sed DebugLoc dl = Op.getDebugLoc(); 494193323Sed const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 495193323Sed SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 496193323Sed 497193323Sed return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);; 498193323Sed} 499193323Sed 500193323Sedstatic SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC, 501193323Sed ISD::CondCode CC, 502193323Sed DebugLoc dl, SelectionDAG &DAG) { 503193323Sed // FIXME: Handle bittests someday 504193323Sed assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); 505193323Sed 506193323Sed // FIXME: Handle jump negative someday 507193323Sed TargetCC = MSP430::COND_INVALID; 508193323Sed switch (CC) { 509193323Sed default: assert(0 && "Invalid integer condition!"); 510193323Sed case ISD::SETEQ: 511193323Sed TargetCC = MSP430::COND_E; // aka COND_Z 512193323Sed break; 513193323Sed case ISD::SETNE: 514193323Sed TargetCC = MSP430::COND_NE; // aka COND_NZ 515193323Sed break; 516193323Sed case ISD::SETULE: 517193323Sed std::swap(LHS, RHS); // FALLTHROUGH 518193323Sed case ISD::SETUGE: 519193323Sed TargetCC = MSP430::COND_HS; // aka COND_C 520193323Sed break; 521193323Sed case ISD::SETUGT: 522193323Sed std::swap(LHS, RHS); // FALLTHROUGH 523193323Sed case ISD::SETULT: 524193323Sed TargetCC = MSP430::COND_LO; // aka COND_NC 525193323Sed break; 526193323Sed case ISD::SETLE: 527193323Sed std::swap(LHS, RHS); // FALLTHROUGH 528193323Sed case ISD::SETGE: 529193323Sed TargetCC = MSP430::COND_GE; 530193323Sed break; 531193323Sed case ISD::SETGT: 532193323Sed std::swap(LHS, RHS); // FALLTHROUGH 533193323Sed case ISD::SETLT: 534193323Sed TargetCC = MSP430::COND_L; 535193323Sed break; 536193323Sed } 537193323Sed 538193323Sed return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS); 539193323Sed} 540193323Sed 541193323Sed 542193323SedSDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 543193323Sed SDValue Chain = Op.getOperand(0); 544193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 545193323Sed SDValue LHS = Op.getOperand(2); 546193323Sed SDValue RHS = Op.getOperand(3); 547193323Sed SDValue Dest = Op.getOperand(4); 548193323Sed DebugLoc dl = Op.getDebugLoc(); 549193323Sed 550193323Sed unsigned TargetCC = MSP430::COND_INVALID; 551193323Sed SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 552193323Sed 553193323Sed return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), 554193323Sed Chain, 555193323Sed Dest, DAG.getConstant(TargetCC, MVT::i8), 556193323Sed Flag); 557193323Sed} 558193323Sed 559193323SedSDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 560193323Sed SDValue LHS = Op.getOperand(0); 561193323Sed SDValue RHS = Op.getOperand(1); 562193323Sed SDValue TrueV = Op.getOperand(2); 563193323Sed SDValue FalseV = Op.getOperand(3); 564193323Sed ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 565193323Sed DebugLoc dl = Op.getDebugLoc(); 566193323Sed 567193323Sed unsigned TargetCC = MSP430::COND_INVALID; 568193323Sed SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); 569193323Sed 570193323Sed SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); 571193323Sed SmallVector<SDValue, 4> Ops; 572193323Sed Ops.push_back(TrueV); 573193323Sed Ops.push_back(FalseV); 574193323Sed Ops.push_back(DAG.getConstant(TargetCC, MVT::i8)); 575193323Sed Ops.push_back(Flag); 576193323Sed 577193323Sed return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); 578193323Sed} 579193323Sed 580193323SedSDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, 581193323Sed SelectionDAG &DAG) { 582193323Sed SDValue Val = Op.getOperand(0); 583193323Sed MVT VT = Op.getValueType(); 584193323Sed DebugLoc dl = Op.getDebugLoc(); 585193323Sed 586193323Sed assert(VT == MVT::i16 && "Only support i16 for now!"); 587193323Sed 588193323Sed return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, 589193323Sed DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), 590193323Sed DAG.getValueType(Val.getValueType())); 591193323Sed} 592193323Sed 593193323Sedconst char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { 594193323Sed switch (Opcode) { 595193323Sed default: return NULL; 596193323Sed case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; 597193323Sed case MSP430ISD::RRA: return "MSP430ISD::RRA"; 598193323Sed case MSP430ISD::RLA: return "MSP430ISD::RLA"; 599193323Sed case MSP430ISD::RRC: return "MSP430ISD::RRC"; 600193323Sed case MSP430ISD::CALL: return "MSP430ISD::CALL"; 601193323Sed case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; 602193323Sed case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; 603193323Sed case MSP430ISD::CMP: return "MSP430ISD::CMP"; 604193323Sed case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; 605193323Sed } 606193323Sed} 607193323Sed 608193323Sed//===----------------------------------------------------------------------===// 609193323Sed// Other Lowering Code 610193323Sed//===----------------------------------------------------------------------===// 611193323Sed 612193323SedMachineBasicBlock* 613193323SedMSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 614193323Sed MachineBasicBlock *BB) const { 615193323Sed const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 616193323Sed DebugLoc dl = MI->getDebugLoc(); 617193323Sed assert((MI->getOpcode() == MSP430::Select16 || 618193323Sed MI->getOpcode() == MSP430::Select8) && 619193323Sed "Unexpected instr type to insert"); 620193323Sed 621193323Sed // To "insert" a SELECT instruction, we actually have to insert the diamond 622193323Sed // control-flow pattern. The incoming instruction knows the destination vreg 623193323Sed // to set, the condition code register to branch on, the true/false values to 624193323Sed // select between, and a branch opcode to use. 625193323Sed const BasicBlock *LLVM_BB = BB->getBasicBlock(); 626193323Sed MachineFunction::iterator I = BB; 627193323Sed ++I; 628193323Sed 629193323Sed // thisMBB: 630193323Sed // ... 631193323Sed // TrueVal = ... 632193323Sed // cmpTY ccX, r1, r2 633193323Sed // jCC copy1MBB 634193323Sed // fallthrough --> copy0MBB 635193323Sed MachineBasicBlock *thisMBB = BB; 636193323Sed MachineFunction *F = BB->getParent(); 637193323Sed MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 638193323Sed MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 639193323Sed BuildMI(BB, dl, TII.get(MSP430::JCC)) 640193323Sed .addMBB(copy1MBB) 641193323Sed .addImm(MI->getOperand(3).getImm()); 642193323Sed F->insert(I, copy0MBB); 643193323Sed F->insert(I, copy1MBB); 644193323Sed // Update machine-CFG edges by transferring all successors of the current 645193323Sed // block to the new block which will contain the Phi node for the select. 646193323Sed copy1MBB->transferSuccessors(BB); 647193323Sed // Next, add the true and fallthrough blocks as its successors. 648193323Sed BB->addSuccessor(copy0MBB); 649193323Sed BB->addSuccessor(copy1MBB); 650193323Sed 651193323Sed // copy0MBB: 652193323Sed // %FalseValue = ... 653193323Sed // # fallthrough to copy1MBB 654193323Sed BB = copy0MBB; 655193323Sed 656193323Sed // Update machine-CFG edges 657193323Sed BB->addSuccessor(copy1MBB); 658193323Sed 659193323Sed // copy1MBB: 660193323Sed // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 661193323Sed // ... 662193323Sed BB = copy1MBB; 663193323Sed BuildMI(BB, dl, TII.get(MSP430::PHI), 664193323Sed MI->getOperand(0).getReg()) 665193323Sed .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 666193323Sed .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 667193323Sed 668193323Sed F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 669193323Sed return BB; 670193323Sed} 671