1234285Sdim//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim 10234285Sdim// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine. 11234285Sdim// This file describes that machine information. 12234285Sdim 13234285Sdim// 14234285Sdim// |===========|==================================================| 15234285Sdim// | PIPELINE | Instruction Classes | 16234285Sdim// |===========|==================================================| 17234285Sdim// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | 18234285Sdim// |-----------|--------------------------------------------------| 19234285Sdim// | SLOT1 | LD ST ALU32 | 20234285Sdim// |-----------|--------------------------------------------------| 21234285Sdim// | SLOT2 | XTYPE ALU32 J JR | 22234285Sdim// |-----------|--------------------------------------------------| 23234285Sdim// | SLOT3 | XTYPE ALU32 J CR | 24234285Sdim// |===========|==================================================| 25234285Sdim 26234285Sdim// Functional Units. 27234285Sdimdef SLOT0 : FuncUnit; 28234285Sdimdef SLOT1 : FuncUnit; 29234285Sdimdef SLOT2 : FuncUnit; 30234285Sdimdef SLOT3 : FuncUnit; 31249423Sdim// Endloop is a pseudo instruction that is encoded with 2 bits in a packet 32249423Sdim// rather than taking an execution slot. This special unit is needed 33249423Sdim// to schedule an ENDLOOP with 4 other instructions. 34249423Sdimdef SLOT_ENDLOOP: FuncUnit; 35234285Sdim 36234285Sdim// Itinerary classes. 37234285Sdimdef NV_V4 : InstrItinClass; 38234285Sdimdef MEM_V4 : InstrItinClass; 39234285Sdim// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. 40239462Sdimdef PREFIX : InstrItinClass; 41234285Sdim 42239462Sdimdef HexagonItinerariesV4 : 43249423Sdim ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ 44239462Sdim InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 45239462Sdim InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>, 46239462Sdim InstrItinData<CR , [InstrStage<1, [SLOT3]>]>, 47239462Sdim InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>, 48239462Sdim InstrItinData<JR , [InstrStage<1, [SLOT2]>]>, 49239462Sdim InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>, 50249423Sdim InstrItinData<LD0 , [InstrStage<1, [SLOT0]>]>, 51239462Sdim InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>, 52239462Sdim InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>, 53249423Sdim InstrItinData<ST0 , [InstrStage<1, [SLOT0]>]>, 54239462Sdim InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>, 55239462Sdim InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>, 56239462Sdim InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>, 57239462Sdim InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>, 58249423Sdim InstrItinData<ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>, 59239462Sdim InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 60249423Sdim InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, 61249423Sdim InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, 62249423Sdim InstrStage<1, [SLOT2, SLOT3]>]> 63239462Sdim ]>; 64234285Sdim 65239462Sdimdef HexagonModelV4 : SchedMachineModel { 66239462Sdim // Max issue per cycle == bundle width. 67239462Sdim let IssueWidth = 4; 68239462Sdim let Itineraries = HexagonItinerariesV4; 69243830Sdim let LoadLatency = 1; 70239462Sdim} 71239462Sdim 72234285Sdim//===----------------------------------------------------------------------===// 73234285Sdim// Hexagon V4 Resource Definitions - 74234285Sdim//===----------------------------------------------------------------------===// 75