1234285Sdim//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim 10234285Sdim// Functional Units 11249423Sdimdef LSUNIT : FuncUnit; // SLOT0 12249423Sdimdef LUNIT : FuncUnit; // SLOT1 13249423Sdimdef MUNIT : FuncUnit; // SLOT2 14249423Sdimdef SUNIT : FuncUnit; // SLOT3 15249423Sdimdef LOOPUNIT : FuncUnit; 16234285Sdim 17234285Sdim// Itinerary classes 18234285Sdimdef ALU32 : InstrItinClass; 19234285Sdimdef ALU64 : InstrItinClass; 20234285Sdimdef CR : InstrItinClass; 21234285Sdimdef J : InstrItinClass; 22234285Sdimdef JR : InstrItinClass; 23234285Sdimdef LD : InstrItinClass; 24249423Sdimdef LD0 : InstrItinClass; 25234285Sdimdef M : InstrItinClass; 26234285Sdimdef ST : InstrItinClass; 27249423Sdimdef ST0 : InstrItinClass; 28234285Sdimdef S : InstrItinClass; 29239462Sdimdef SYS : InstrItinClass; 30249423Sdimdef ENDLOOP : InstrItinClass; 31234285Sdimdef PSEUDO : InstrItinClass; 32249423Sdimdef PSEUDOM : InstrItinClass; 33234285Sdim 34234285Sdimdef HexagonItineraries : 35249423Sdim ProcessorItineraries<[LSUNIT, LUNIT, MUNIT, SUNIT, LOOPUNIT], [], [ 36239462Sdim InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, 37239462Sdim InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>, 38239462Sdim InstrItinData<CR , [InstrStage<1, [SUNIT]>]>, 39239462Sdim InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>, 40239462Sdim InstrItinData<JR , [InstrStage<1, [MUNIT]>]>, 41239462Sdim InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>, 42249423Sdim InstrItinData<LD0 , [InstrStage<1, [LSUNIT]>]>, 43239462Sdim InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>, 44239462Sdim InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>, 45249423Sdim InstrItinData<ST0 , [InstrStage<1, [LSUNIT]>]>, 46239462Sdim InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>, 47239462Sdim InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>, 48249423Sdim InstrItinData<ENDLOOP, [InstrStage<1, [LOOPUNIT]>]>, 49249423Sdim InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, 50249423Sdim InstrItinData<PSEUDOM, [InstrStage<1, [MUNIT, SUNIT], 0>, 51249423Sdim InstrStage<1, [MUNIT, SUNIT]>]> 52239462Sdim ]>; 53234285Sdim 54239462Sdimdef HexagonModel : SchedMachineModel { 55239462Sdim // Max issue per cycle == bundle width. 56239462Sdim let IssueWidth = 4; 57239462Sdim let Itineraries = HexagonItineraries; 58243830Sdim let LoadLatency = 1; 59239462Sdim} 60234982Sdim 61234285Sdim//===----------------------------------------------------------------------===// 62234285Sdim// V4 Machine Info + 63234285Sdim//===----------------------------------------------------------------------===// 64234285Sdim 65234285Sdiminclude "HexagonScheduleV4.td" 66234285Sdim 67234285Sdim//===----------------------------------------------------------------------===// 68234285Sdim// V4 Machine Info - 69234285Sdim//===----------------------------------------------------------------------===// 70