1234285Sdim//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim 10234285Sdim//===----------------------------------------------------------------------===// 11234285Sdim// Declarations that describe the Hexagon register file. 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14234285Sdimlet Namespace = "Hexagon" in { 15234285Sdim 16234285Sdim class HexagonReg<string n> : Register<n> { 17234285Sdim field bits<5> Num; 18234285Sdim } 19234285Sdim 20234285Sdim class HexagonDoubleReg<string n, list<Register> subregs> : 21234285Sdim RegisterWithSubRegs<n, subregs> { 22234285Sdim field bits<5> Num; 23234285Sdim } 24234285Sdim 25234285Sdim // Registers are identified with 5-bit ID numbers. 26234285Sdim // Ri - 32-bit integer registers. 27234285Sdim class Ri<bits<5> num, string n> : HexagonReg<n> { 28234285Sdim let Num = num; 29234285Sdim } 30234285Sdim 31234285Sdim // Rf - 32-bit floating-point registers. 32234285Sdim class Rf<bits<5> num, string n> : HexagonReg<n> { 33234285Sdim let Num = num; 34234285Sdim } 35234285Sdim 36234285Sdim 37234285Sdim // Rd - 64-bit registers. 38234285Sdim class Rd<bits<5> num, string n, list<Register> subregs> : 39234285Sdim HexagonDoubleReg<n, subregs> { 40234285Sdim let Num = num; 41234285Sdim let SubRegs = subregs; 42234285Sdim } 43234285Sdim 44234285Sdim // Rp - predicate registers 45234285Sdim class Rp<bits<5> num, string n> : HexagonReg<n> { 46234285Sdim let Num = num; 47234285Sdim } 48234285Sdim 49234285Sdim // Rc - control registers 50234285Sdim class Rc<bits<5> num, string n> : HexagonReg<n> { 51234285Sdim let Num = num; 52234285Sdim } 53234285Sdim 54234285Sdim // Rj - aliased integer registers 55234285Sdim class Rj<string n, Ri R>: HexagonReg<n> { 56234285Sdim let Num = R.Num; 57234285Sdim let Aliases = [R]; 58234285Sdim } 59234285Sdim 60263508Sdim def subreg_loreg : SubRegIndex<32>; 61263508Sdim def subreg_hireg : SubRegIndex<32, 32>; 62234285Sdim 63234285Sdim // Integer registers. 64234285Sdim def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; 65234285Sdim def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; 66234285Sdim def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; 67234285Sdim def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; 68234285Sdim def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; 69234285Sdim def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; 70234285Sdim def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; 71234285Sdim def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; 72234285Sdim def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; 73234285Sdim def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; 74234285Sdim def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; 75234285Sdim def R11 : Ri<11, "r11">, DwarfRegNum<[11]>; 76234285Sdim def R12 : Ri<12, "r12">, DwarfRegNum<[12]>; 77234285Sdim def R13 : Ri<13, "r13">, DwarfRegNum<[13]>; 78234285Sdim def R14 : Ri<14, "r14">, DwarfRegNum<[14]>; 79234285Sdim def R15 : Ri<15, "r15">, DwarfRegNum<[15]>; 80234285Sdim def R16 : Ri<16, "r16">, DwarfRegNum<[16]>; 81234285Sdim def R17 : Ri<17, "r17">, DwarfRegNum<[17]>; 82234285Sdim def R18 : Ri<18, "r18">, DwarfRegNum<[18]>; 83234285Sdim def R19 : Ri<19, "r19">, DwarfRegNum<[19]>; 84234285Sdim def R20 : Ri<20, "r20">, DwarfRegNum<[20]>; 85234285Sdim def R21 : Ri<21, "r21">, DwarfRegNum<[21]>; 86234285Sdim def R22 : Ri<22, "r22">, DwarfRegNum<[22]>; 87234285Sdim def R23 : Ri<23, "r23">, DwarfRegNum<[23]>; 88234285Sdim def R24 : Ri<24, "r24">, DwarfRegNum<[24]>; 89234285Sdim def R25 : Ri<25, "r25">, DwarfRegNum<[25]>; 90234285Sdim def R26 : Ri<26, "r26">, DwarfRegNum<[26]>; 91234285Sdim def R27 : Ri<27, "r27">, DwarfRegNum<[27]>; 92234285Sdim def R28 : Ri<28, "r28">, DwarfRegNum<[28]>; 93234285Sdim def R29 : Ri<29, "r29">, DwarfRegNum<[29]>; 94234285Sdim def R30 : Ri<30, "r30">, DwarfRegNum<[30]>; 95234285Sdim def R31 : Ri<31, "r31">, DwarfRegNum<[31]>; 96234285Sdim 97234285Sdim def SP : Rj<"sp", R29>, DwarfRegNum<[29]>; 98234285Sdim def FP : Rj<"fp", R30>, DwarfRegNum<[30]>; 99234285Sdim def LR : Rj<"lr", R31>, DwarfRegNum<[31]>; 100234285Sdim 101234285Sdim // Aliases of the R* registers used to hold 64-bit int values (doubles). 102234285Sdim let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { 103234285Sdim def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 104234285Sdim def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 105234285Sdim def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 106234285Sdim def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 107234285Sdim def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 108234285Sdim def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 109234285Sdim def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 110234285Sdim def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 111234285Sdim def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 112234285Sdim def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 113234285Sdim def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 114234285Sdim def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 115234285Sdim def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 116234285Sdim def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 117234285Sdim def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 118234285Sdim def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>; 119234285Sdim } 120234285Sdim 121234285Sdim // Predicate registers. 122234285Sdim def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 123234285Sdim def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 124234285Sdim def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 125234285Sdim def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 126234285Sdim 127234285Sdim // Control registers. 128234285Sdim def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>; 129234285Sdim def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>; 130234285Sdim 131234285Sdim def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>; 132234285Sdim def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>; 133234285Sdim 134239462Sdim def M0 : Rc<6, "m0">, DwarfRegNum<[71]>; 135239462Sdim def M1 : Rc<7, "m1">, DwarfRegNum<[72]>; 136239462Sdim 137234285Sdim def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct? 138234285Sdim def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct? 139234285Sdim} 140234285Sdim 141234285Sdim// Register classes. 142234285Sdim// 143234285Sdim// FIXME: the register order should be defined in terms of the preferred 144234285Sdim// allocation order... 145234285Sdim// 146239462Sdimdef IntRegs : RegisterClass<"Hexagon", [i32,f32], 32, 147234285Sdim (add (sequence "R%u", 0, 9), 148234285Sdim (sequence "R%u", 12, 28), 149234285Sdim R10, R11, R29, R30, R31)> { 150234285Sdim} 151234285Sdim 152239462Sdimdef DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64, 153234285Sdim (add (sequence "D%u", 0, 4), 154239462Sdim (sequence "D%u", 6, 13), D5, D14, D15)>; 155234285Sdim 156234285Sdim 157234285Sdimdef PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> 158234285Sdim{ 159234285Sdim let Size = 32; 160234285Sdim} 161234285Sdim 162234285Sdimdef CRRegs : RegisterClass<"Hexagon", [i32], 32, 163234285Sdim (add (sequence "LC%u", 0, 1), 164239462Sdim (sequence "SA%u", 0, 1), 165239462Sdim (sequence "M%u", 0, 1), PC, GP)> { 166234285Sdim let Size = 32; 167234285Sdim} 168