1234285Sdim//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// This is populated based on the following specs: 10234285Sdim// Hexagon V4 Architecture Extensions 11234285Sdim// Application-Level Specification 12234285Sdim// 80-V9418-12 Rev. A 13234285Sdim// June 15, 2010 14234285Sdim 15234285Sdim 16234285Sdim// 17234285Sdim// ALU 32 types. 18234285Sdim// 19234285Sdim 20234285Sdimclass si_ALU32_sisi_not<string opc, Intrinsic IntID> 21234285Sdim : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), 22234285Sdim !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")), 23234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; 24234285Sdim 25234285Sdimclass di_ALU32_s8si<string opc, Intrinsic IntID> 26234285Sdim : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2), 27234285Sdim !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")), 28234285Sdim [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>; 29234285Sdim 30234285Sdimclass di_ALU32_sis8<string opc, Intrinsic IntID> 31234285Sdim : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), 32234285Sdim !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 33234285Sdim [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 34234285Sdim 35234285Sdimclass qi_neg_ALU32_sisi<string opc, Intrinsic IntID> 36234285Sdim : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), 37234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), 38234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; 39234285Sdim 40234285Sdimclass qi_neg_ALU32_sis10<string opc, Intrinsic IntID> 41234285Sdim : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2), 42234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), 43234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 44234285Sdim 45234285Sdimclass qi_neg_ALU32_siu9<string opc, Intrinsic IntID> 46234285Sdim : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2), 47234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), 48234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 49234285Sdim 50234285Sdimclass si_neg_ALU32_sisi<string opc, Intrinsic IntID> 51234285Sdim : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), 52234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), 53234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; 54234285Sdim 55234285Sdimclass si_neg_ALU32_sis8<string opc, Intrinsic IntID> 56234285Sdim : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), 57234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")), 58234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 59234285Sdim 60234285Sdimclass si_ALU32_sis8<string opc, Intrinsic IntID> 61234285Sdim : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2), 62234285Sdim !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")), 63234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 64234285Sdim 65234285Sdim 66234285Sdim// 67234285Sdim// SInst Classes. 68234285Sdim// 69234285Sdimclass qi_neg_SInst_qiqi<string opc, Intrinsic IntID> 70234285Sdim : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), 71234285Sdim !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")), 72234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; 73234285Sdim 74234285Sdimclass qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID> 75234285Sdim : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, 76234285Sdim IntRegs:$src3), 77234285Sdim !strconcat("$dst = ", !strconcat(opc , 78234285Sdim "($src1, and($src2, !$src3)")), 79234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 80234285Sdim IntRegs:$src3))]>; 81234285Sdim 82234285Sdimclass qi_SInst_qi_andqiqi<string opc, Intrinsic IntID> 83234285Sdim : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, 84234285Sdim IntRegs:$src3), 85234285Sdim !strconcat("$dst = ", !strconcat(opc , 86234285Sdim "($src1, and($src2, $src3)")), 87234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 88234285Sdim IntRegs:$src3))]>; 89234285Sdim 90234285Sdimclass qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID> 91234285Sdim : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, 92234285Sdim IntRegs:$src3), 93234285Sdim !strconcat("$dst = ", !strconcat(opc , 94234285Sdim "($src1, or($src2, !$src3)")), 95234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 96234285Sdim IntRegs:$src3))]>; 97234285Sdim 98234285Sdimclass qi_SInst_qi_orqiqi<string opc, Intrinsic IntID> 99234285Sdim : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, 100234285Sdim IntRegs:$src3), 101234285Sdim !strconcat("$dst = ", !strconcat(opc , 102234285Sdim "($src1, or($src2, $src3)")), 103234285Sdim [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 104234285Sdim IntRegs:$src3))]>; 105234285Sdim 106234285Sdimclass si_SInst_si_addsis6<string opc, Intrinsic IntID> 107234285Sdim : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3), 108234285Sdim !strconcat("$dst = ", !strconcat(opc , 109234285Sdim "($src1, add($src2, #$src3)")), 110234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 111234285Sdim imm:$src3))]>; 112234285Sdim 113234285Sdimclass si_SInst_si_subs6si<string opc, Intrinsic IntID> 114234285Sdim : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3), 115234285Sdim !strconcat("$dst = ", !strconcat(opc , 116234285Sdim "($src1, sub(#$src2, $src3)")), 117234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, 118234285Sdim IntRegs:$src3))]>; 119234285Sdim 120234285Sdimclass di_ALU64_didi_neg<string opc, Intrinsic IntID> 121234285Sdim : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2), 122234285Sdim !strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")), 123234285Sdim [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>; 124234285Sdim 125234285Sdimclass di_MInst_dididi_xacc<string opc, Intrinsic IntID> 126234285Sdim : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, 127234285Sdim DoubleRegs:$src2), 128234285Sdim !strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")), 129234285Sdim [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1, 130234285Sdim DoubleRegs:$src2))], 131234285Sdim "$dst2 = $dst">; 132234285Sdim 133234285Sdimclass si_MInst_sisisi_and<string opc, Intrinsic IntID> 134234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 135234285Sdim IntRegs:$src3), 136234285Sdim !strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")), 137234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 138234285Sdim IntRegs:$src3))]>; 139234285Sdim 140234285Sdimclass si_MInst_sisisi_andn<string opc, Intrinsic IntID> 141234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 142234285Sdim IntRegs:$src3), 143234285Sdim !strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")), 144234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 145234285Sdim IntRegs:$src3))]>; 146234285Sdim 147234285Sdimclass si_SInst_sisis10_andi<string opc, Intrinsic IntID> 148234285Sdim : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3), 149234285Sdim !strconcat("$dst = ", !strconcat(opc , 150234285Sdim "($src1, and($src2, #$src3))")), 151234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2, 152234285Sdim imm:$src3))]>; 153234285Sdim 154234285Sdimclass si_MInst_sisisi_xor<string opc, Intrinsic IntID> 155234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 156234285Sdim IntRegs:$src3), 157234285Sdim !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")), 158234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 159234285Sdim IntRegs:$src3))]>; 160234285Sdim 161234285Sdimclass si_MInst_sisisi_xorn<string opc, Intrinsic IntID> 162234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 163234285Sdim IntRegs:$src3), 164234285Sdim !strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")), 165234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 166234285Sdim IntRegs:$src3))]>; 167234285Sdim 168234285Sdimclass si_SInst_sisis10_or<string opc, Intrinsic IntID> 169234285Sdim : SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3), 170234285Sdim !strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")), 171234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 172234285Sdim imm:$src3))]>; 173234285Sdim 174234285Sdimclass si_MInst_sisisi_or<string opc, Intrinsic IntID> 175234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 176234285Sdim IntRegs:$src3), 177234285Sdim !strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")), 178234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 179234285Sdim IntRegs:$src3))]>; 180234285Sdim 181234285Sdimclass si_MInst_sisisi_orn<string opc, Intrinsic IntID> 182234285Sdim : MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, 183234285Sdim IntRegs:$src3), 184234285Sdim !strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")), 185234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2, 186234285Sdim IntRegs:$src3))]>; 187234285Sdim 188234285Sdimclass si_SInst_siu5_sat<string opc, Intrinsic IntID> 189234285Sdim : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2), 190234285Sdim !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")), 191234285Sdim [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>; 192234285Sdim 193234285Sdim 194234285Sdim/******************************************************************** 195234285Sdim* ALU32/ALU * 196234285Sdim*********************************************************************/ 197234285Sdim 198234285Sdim// ALU32 / ALU / Logical Operations. 199234285Sdimdef Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>; 200234285Sdimdef Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>; 201234285Sdim 202234285Sdim 203234285Sdim/******************************************************************** 204234285Sdim* ALU32/PERM * 205234285Sdim*********************************************************************/ 206234285Sdim 207234285Sdim// ALU32 / PERM / Combine Words Into Doublewords. 208234285Sdimdef Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>; 209234285Sdimdef Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>; 210234285Sdim 211234285Sdim 212234285Sdim/******************************************************************** 213234285Sdim* ALU32/PRED * 214234285Sdim*********************************************************************/ 215234285Sdim 216234285Sdim// ALU32 / PRED / Conditional Shift Halfword. 217234285Sdim// ALU32 / PRED / Conditional Sign Extend. 218234285Sdim// ALU32 / PRED / Conditional Zero Extend. 219234285Sdim// ALU32 / PRED / Compare. 220234285Sdimdef Hexagon_C4_cmpneq : qi_neg_ALU32_sisi <"cmp.eq", int_hexagon_C4_cmpneq>; 221234285Sdimdef Hexagon_C4_cmpneqi : qi_neg_ALU32_sis10 <"cmp.eq", int_hexagon_C4_cmpneqi>; 222234285Sdimdef Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>; 223234285Sdimdef Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>; 224234285Sdimdef Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>; 225234285Sdimdef Hexagon_C4_cmplteui: qi_neg_ALU32_siu9 <"cmp.gtu",int_hexagon_C4_cmplteui>; 226234285Sdim 227234285Sdim// ALU32 / PRED / cmpare To General Register. 228234285Sdimdef Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>; 229234285Sdimdef Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>; 230234285Sdimdef Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>; 231234285Sdimdef Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>; 232234285Sdim 233234285Sdim 234234285Sdim/******************************************************************** 235234285Sdim* CR * 236234285Sdim*********************************************************************/ 237234285Sdim 238234285Sdim// CR / Corner Detection Acceleration. 239234285Sdimdef Hexagon_C4_fastcorner9: 240234285Sdim qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>; 241234285Sdimdef Hexagon_C4_fastcorner9_not: 242234285Sdim qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>; 243234285Sdim 244234285Sdim// CR / Logical Operations On Predicates. 245234285Sdimdef Hexagon_C4_and_andn: 246234285Sdim qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>; 247234285Sdimdef Hexagon_C4_and_and: 248234285Sdim qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>; 249234285Sdimdef Hexagon_C4_and_orn: 250234285Sdim qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>; 251234285Sdimdef Hexagon_C4_and_or: 252234285Sdim qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>; 253234285Sdimdef Hexagon_C4_or_andn: 254234285Sdim qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>; 255234285Sdimdef Hexagon_C4_or_and: 256234285Sdim qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>; 257234285Sdimdef Hexagon_C4_or_orn: 258234285Sdim qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>; 259234285Sdimdef Hexagon_C4_or_or: 260234285Sdim qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>; 261234285Sdim 262234285Sdim 263234285Sdim/******************************************************************** 264234285Sdim* XTYPE/ALU * 265234285Sdim*********************************************************************/ 266234285Sdim 267234285Sdim// XTYPE / ALU / Add And Accumulate. 268234285Sdimdef Hexagon_S4_addaddi: 269234285Sdim si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>; 270234285Sdimdef Hexagon_S4_subaddi: 271234285Sdim si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>; 272234285Sdim 273234285Sdim// XTYPE / ALU / Logical Doublewords. 274234285Sdimdef Hexagon_S4_andnp: 275234285Sdim di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>; 276234285Sdimdef Hexagon_S4_ornp: 277234285Sdim di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>; 278234285Sdim 279234285Sdim// XTYPE / ALU / Logical-logical Doublewords. 280234285Sdimdef Hexagon_M4_xor_xacc: 281234285Sdim di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>; 282234285Sdim 283234285Sdim// XTYPE / ALU / Logical-logical Words. 284234285Sdimdef HEXAGON_M4_and_and: 285234285Sdim si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>; 286234285Sdimdef HEXAGON_M4_and_or: 287234285Sdim si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>; 288234285Sdimdef HEXAGON_M4_and_xor: 289234285Sdim si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>; 290234285Sdimdef HEXAGON_M4_and_andn: 291234285Sdim si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>; 292234285Sdimdef HEXAGON_M4_xor_and: 293234285Sdim si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>; 294234285Sdimdef HEXAGON_M4_xor_or: 295234285Sdim si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>; 296234285Sdimdef HEXAGON_M4_xor_andn: 297234285Sdim si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>; 298234285Sdimdef HEXAGON_M4_or_and: 299234285Sdim si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>; 300234285Sdimdef HEXAGON_M4_or_or: 301234285Sdim si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>; 302234285Sdimdef HEXAGON_M4_or_xor: 303234285Sdim si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>; 304234285Sdimdef HEXAGON_M4_or_andn: 305234285Sdim si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>; 306234285Sdimdef HEXAGON_S4_or_andix: 307234285Sdim si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>; 308234285Sdimdef HEXAGON_S4_or_andi: 309234285Sdim si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>; 310234285Sdimdef HEXAGON_S4_or_ori: 311234285Sdim si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>; 312234285Sdim 313234285Sdim// XTYPE / ALU / Modulo wrap. 314234285Sdimdef HEXAGON_A4_modwrapu: 315234285Sdim si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>; 316234285Sdim 317234285Sdim// XTYPE / ALU / Round. 318234285Sdimdef HEXAGON_A4_cround_ri: 319234285Sdim si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>; 320234285Sdimdef HEXAGON_A4_cround_rr: 321234285Sdim si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>; 322234285Sdimdef HEXAGON_A4_round_ri: 323234285Sdim si_SInst_siu5 <"round", int_hexagon_A4_round_ri>; 324234285Sdimdef HEXAGON_A4_round_rr: 325234285Sdim si_SInst_sisi <"round", int_hexagon_A4_round_rr>; 326234285Sdimdef HEXAGON_A4_round_ri_sat: 327234285Sdim si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>; 328234285Sdimdef HEXAGON_A4_round_rr_sat: 329234285Sdim si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>; 330234285Sdim 331234285Sdim// XTYPE / ALU / Vector reduce add unsigned halfwords. 332234285Sdim// XTYPE / ALU / Vector add bytes. 333234285Sdim// XTYPE / ALU / Vector conditional negate. 334234285Sdim// XTYPE / ALU / Vector maximum bytes. 335234285Sdim// XTYPE / ALU / Vector reduce maximum halfwords. 336234285Sdim// XTYPE / ALU / Vector reduce maximum words. 337234285Sdim// XTYPE / ALU / Vector minimum bytes. 338234285Sdim// XTYPE / ALU / Vector reduce minimum halfwords. 339234285Sdim// XTYPE / ALU / Vector reduce minimum words. 340234285Sdim// XTYPE / ALU / Vector subtract bytes. 341234285Sdim 342234285Sdim 343234285Sdim/******************************************************************** 344234285Sdim* XTYPE/BIT * 345234285Sdim*********************************************************************/ 346234285Sdim 347234285Sdim// XTYPE / BIT / Count leading. 348234285Sdim// XTYPE / BIT / Count trailing. 349234285Sdim// XTYPE / BIT / Extract bitfield. 350234285Sdim// XTYPE / BIT / Masked parity. 351234285Sdim// XTYPE / BIT / Bit reverse. 352234285Sdim// XTYPE / BIT / Split bitfield. 353234285Sdim 354234285Sdim 355234285Sdim/******************************************************************** 356234285Sdim* XTYPE/COMPLEX * 357234285Sdim*********************************************************************/ 358234285Sdim 359234285Sdim// XTYPE / COMPLEX / Complex add/sub halfwords. 360234285Sdim// XTYPE / COMPLEX / Complex add/sub words. 361234285Sdim// XTYPE / COMPLEX / Complex multiply 32x16. 362234285Sdim// XTYPE / COMPLEX / Vector reduce complex rotate. 363234285Sdim 364234285Sdim 365234285Sdim/******************************************************************** 366234285Sdim* XTYPE/MPY * 367234285Sdim*********************************************************************/ 368234285Sdim 369234285Sdim// XTYPE / COMPLEX / Complex add/sub halfwords. 370