1234285Sdim//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
2234285Sdim//
3234285Sdim//                     The LLVM Compiler Infrastructure
4234285Sdim//
5234285Sdim// This file is distributed under the University of Illinois Open Source
6234285Sdim// License. See LICENSE.TXT for details.
7234285Sdim//
8234285Sdim//===----------------------------------------------------------------------===//
9234285Sdim//
10234285Sdim// This file describes the Hexagon V3 instructions in TableGen format.
11234285Sdim//
12234285Sdim//===----------------------------------------------------------------------===//
13234285Sdim
14251662Sdimdef callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15251662Sdim           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
16234285Sdim
17251662Sdimdef callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18251662Sdim           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
19251662Sdim
20234285Sdim//===----------------------------------------------------------------------===//
21234285Sdim// J +
22234285Sdim//===----------------------------------------------------------------------===//
23234285Sdim// Call subroutine.
24234285Sdimlet isCall = 1, neverHasSideEffects = 1,
25234285Sdim  Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
26234285Sdim                P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
27239462Sdim  def CALLv3 : JInst<(outs), (ins calltarget:$dst),
28234285Sdim             "call $dst", []>, Requires<[HasV3T]>;
29234285Sdim}
30234285Sdim
31234285Sdim//===----------------------------------------------------------------------===//
32234285Sdim// J -
33234285Sdim//===----------------------------------------------------------------------===//
34234285Sdim
35234285Sdim
36234285Sdim//===----------------------------------------------------------------------===//
37234285Sdim// JR +
38234285Sdim//===----------------------------------------------------------------------===//
39234285Sdim// Call subroutine from register.
40234285Sdimlet isCall = 1, neverHasSideEffects = 1,
41234285Sdim  Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
42234285Sdim                P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
43239462Sdim  def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
44234285Sdim              "callr $dst",
45234285Sdim              []>, Requires<[HasV3TOnly]>;
46234285Sdim }
47234285Sdim
48234285Sdim//===----------------------------------------------------------------------===//
49234285Sdim// JR -
50234285Sdim//===----------------------------------------------------------------------===//
51234285Sdim
52234285Sdim//===----------------------------------------------------------------------===//
53234285Sdim// ALU64/ALU +
54234285Sdim//===----------------------------------------------------------------------===//
55234285Sdim
56234285Sdimlet AddedComplexity = 200 in
57234285Sdimdef MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
58234285Sdim                                                    DoubleRegs:$src2),
59234285Sdim              "$dst = max($src2, $src1)",
60239462Sdim              [(set (i64 DoubleRegs:$dst),
61239462Sdim                    (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
62239462Sdim                                            (i64 DoubleRegs:$src1))),
63239462Sdim                                 (i64 DoubleRegs:$src1),
64239462Sdim                                 (i64 DoubleRegs:$src2))))]>,
65234285SdimRequires<[HasV3T]>;
66234285Sdim
67234285Sdimlet AddedComplexity = 200 in
68234285Sdimdef MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
69234285Sdim                                                    DoubleRegs:$src2),
70234285Sdim              "$dst = min($src2, $src1)",
71239462Sdim              [(set (i64 DoubleRegs:$dst),
72239462Sdim                    (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
73239462Sdim                                            (i64 DoubleRegs:$src1))),
74239462Sdim                                 (i64 DoubleRegs:$src1),
75239462Sdim                                 (i64 DoubleRegs:$src2))))]>,
76234285SdimRequires<[HasV3T]>;
77234285Sdim
78234285Sdim//===----------------------------------------------------------------------===//
79234285Sdim// ALU64/ALU -
80234285Sdim//===----------------------------------------------------------------------===//
81234285Sdim
82234285Sdim
83234285Sdim
84234285Sdim
85239462Sdim//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
86239462Sdim//      (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
87234285Sdim
88239462Sdim//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
89239462Sdim//      (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
90234285Sdim
91239462Sdim//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
92239462Sdim//      (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
93234285Sdim
94239462Sdim//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
95239462Sdim//      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
96234285Sdim
97239462Sdim//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
98239462Sdim//      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
99234285Sdim
100234285Sdim
101234285Sdim// Map call instruction
102239462Sdimdef : Pat<(call (i32 IntRegs:$dst)),
103239462Sdim      (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
104234285Sdimdef : Pat<(call tglobaladdr:$dst),
105234285Sdim      (CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
106234285Sdimdef : Pat<(call texternalsym:$dst),
107234285Sdim      (CALLv3 texternalsym:$dst)>, Requires<[HasV3T]>;
108