1234285Sdim//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This file describes the Hexagon V4 instruction classes in TableGen format. 11234285Sdim// 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14239462Sdim//----------------------------------------------------------------------------// 15239462Sdim// Hexagon Intruction Flags + 16234285Sdim// 17239462Sdim// *** Must match BaseInfo.h *** 18239462Sdim//----------------------------------------------------------------------------// 19239462Sdim 20249423Sdimdef TypeMEMOP : IType<9>; 21249423Sdimdef TypeNV : IType<10>; 22249423Sdimdef TypePREFIX : IType<30>; 23239462Sdim 24239462Sdim//----------------------------------------------------------------------------// 25239462Sdim// Intruction Classes Definitions + 26239462Sdim//----------------------------------------------------------------------------// 27239462Sdim 28239462Sdim// 29234285Sdim// NV type instructions. 30234285Sdim// 31249423Sdimclass NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 32249423Sdim string cstr = ""> 33249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>; 34234285Sdim 35249423Sdimclass NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], 36249423Sdim string cstr = ""> 37249423Sdim : NVInst<outs, ins, asmstr, pattern, cstr>; 38249423Sdim 39234285Sdim// Definition of Post increment new value store. 40249423Sdimclass NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], 41249423Sdim string cstr = ""> 42249423Sdim : NVInst<outs, ins, asmstr, pattern, cstr>; 43234285Sdim 44234285Sdim// Post increment ST Instruction. 45249423Sdimlet mayStore = 1 in 46249423Sdimclass NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], 47249423Sdim string cstr = ""> 48249423Sdim : NVInst<outs, ins, asmstr, pattern, cstr>; 49234285Sdim 50249423Sdim// New-value conditional branch. 51249423Sdimclass NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 52249423Sdim string cstr = ""> 53249423Sdim : NVInst<outs, ins, asmstr, pattern, cstr>; 54239462Sdim 55249423Sdimlet mayLoad = 1, mayStore = 1 in 56249423Sdimclass MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 57249423Sdim string cstr = ""> 58249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, MEM_V4, TypeMEMOP>; 59239462Sdim 60249423Sdimclass MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], 61249423Sdim string cstr = ""> 62249423Sdim : MEMInst<outs, ins, asmstr, pattern, cstr>; 63249423Sdim 64249423Sdimlet isCodeGenOnly = 1 in 65249423Sdimclass EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []> 66249423Sdim : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>; 67