1234285Sdim//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim 10234285Sdim//===----------------------------------------------------------------------===// 11234285Sdim// Hexagon Intruction Flags + 12234285Sdim// 13234285Sdim// *** Must match HexagonBaseInfo.h *** 14234285Sdim//===----------------------------------------------------------------------===// 15234285Sdim 16249423Sdimclass IType<bits<5> t> { 17239462Sdim bits<5> Value = t; 18239462Sdim} 19249423Sdimdef TypePSEUDO : IType<0>; 20249423Sdimdef TypeALU32 : IType<1>; 21249423Sdimdef TypeCR : IType<2>; 22249423Sdimdef TypeJR : IType<3>; 23249423Sdimdef TypeJ : IType<4>; 24249423Sdimdef TypeLD : IType<5>; 25249423Sdimdef TypeST : IType<6>; 26249423Sdimdef TypeSYSTEM : IType<7>; 27249423Sdimdef TypeXTYPE : IType<8>; 28249423Sdimdef TypeENDLOOP: IType<31>; 29234285Sdim 30249423Sdim// Maintain list of valid subtargets for each instruction. 31249423Sdimclass SubTarget<bits<4> value> { 32249423Sdim bits<4> Value = value; 33249423Sdim} 34249423Sdim 35249423Sdimdef HasV2SubT : SubTarget<0xf>; 36249423Sdimdef HasV2SubTOnly : SubTarget<0x1>; 37249423Sdimdef NoV2SubT : SubTarget<0x0>; 38249423Sdimdef HasV3SubT : SubTarget<0xe>; 39249423Sdimdef HasV3SubTOnly : SubTarget<0x2>; 40249423Sdimdef NoV3SubT : SubTarget<0x1>; 41249423Sdimdef HasV4SubT : SubTarget<0xc>; 42249423Sdimdef NoV4SubT : SubTarget<0x3>; 43249423Sdimdef HasV5SubT : SubTarget<0x8>; 44249423Sdimdef NoV5SubT : SubTarget<0x7>; 45249423Sdim 46249423Sdim// Addressing modes for load/store instructions 47249423Sdimclass AddrModeType<bits<3> value> { 48249423Sdim bits<3> Value = value; 49249423Sdim} 50249423Sdim 51249423Sdimdef NoAddrMode : AddrModeType<0>; // No addressing mode 52249423Sdimdef Absolute : AddrModeType<1>; // Absolute addressing mode 53249423Sdimdef AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode 54249423Sdimdef BaseImmOffset : AddrModeType<3>; // Indirect with offset 55249423Sdimdef BaseLongOffset : AddrModeType<4>; // Indirect with long offset 56249423Sdimdef BaseRegOffset : AddrModeType<5>; // Indirect with register offset 57263508Sdimdef PostInc : AddrModeType<6>; // Post increment addressing mode 58249423Sdim 59249423Sdimclass MemAccessSize<bits<3> value> { 60249423Sdim bits<3> Value = value; 61249423Sdim} 62249423Sdim 63249423Sdimdef NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. 64249423Sdimdef ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). 65249423Sdimdef HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). 66263508Sdimdef WordAccess : MemAccessSize<3>;// Word access instruction (memw). 67249423Sdimdef DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) 68249423Sdim 69249423Sdim 70234285Sdim//===----------------------------------------------------------------------===// 71234285Sdim// Intruction Class Declaration + 72234285Sdim//===----------------------------------------------------------------------===// 73234285Sdim 74249423Sdimclass OpcodeHexagon { 75249423Sdim field bits<32> Inst = ?; // Default to an invalid insn. 76249423Sdim bits<4> IClass = 0; // ICLASS 77249423Sdim bits<2> IParse = 0; // Parse bits. 78249423Sdim 79249423Sdim let Inst{31-28} = IClass; 80249423Sdim let Inst{15-14} = IParse; 81249423Sdim 82249423Sdim bits<1> zero = 0; 83249423Sdim} 84249423Sdim 85234285Sdimclass InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, 86249423Sdim string cstr, InstrItinClass itin, IType type> 87249423Sdim : Instruction, OpcodeHexagon { 88234285Sdim let Namespace = "Hexagon"; 89234285Sdim 90234285Sdim dag OutOperandList = outs; 91234285Sdim dag InOperandList = ins; 92239462Sdim let AsmString = asmstr; 93234285Sdim let Pattern = pattern; 94234285Sdim let Constraints = cstr; 95239462Sdim let Itinerary = itin; 96239462Sdim let Size = 4; 97234285Sdim 98249423Sdim // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 99249423Sdim 100239462Sdim // Instruction type according to the ISA. 101249423Sdim IType Type = type; 102249423Sdim let TSFlags{4-0} = Type.Value; 103249423Sdim 104239462Sdim // Solo instructions, i.e., those that cannot be in a packet with others. 105249423Sdim bits<1> isSolo = 0; 106249423Sdim let TSFlags{5} = isSolo; 107249423Sdim 108234285Sdim // Predicated instructions. 109234285Sdim bits<1> isPredicated = 0; 110239462Sdim let TSFlags{6} = isPredicated; 111249423Sdim bits<1> isPredicatedFalse = 0; 112249423Sdim let TSFlags{7} = isPredicatedFalse; 113249423Sdim bits<1> isPredicatedNew = 0; 114249423Sdim let TSFlags{8} = isPredicatedNew; 115234285Sdim 116249423Sdim // New-value insn helper fields. 117249423Sdim bits<1> isNewValue = 0; 118249423Sdim let TSFlags{9} = isNewValue; // New-value consumer insn. 119249423Sdim bits<1> hasNewValue = 0; 120249423Sdim let TSFlags{10} = hasNewValue; // New-value producer insn. 121249423Sdim bits<3> opNewValue = 0; 122249423Sdim let TSFlags{13-11} = opNewValue; // New-value produced operand. 123249423Sdim bits<2> opNewBits = 0; 124249423Sdim let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16. 125249423Sdim bits<1> isNVStorable = 0; 126249423Sdim let TSFlags{16} = isNVStorable; // Store that can become new-value store. 127243830Sdim bits<1> isNVStore = 0; 128249423Sdim let TSFlags{17} = isNVStore; // New-value store insn. 129243830Sdim 130249423Sdim // Immediate extender helper fields. 131249423Sdim bits<1> isExtendable = 0; 132249423Sdim let TSFlags{18} = isExtendable; // Insn may be extended. 133249423Sdim bits<1> isExtended = 0; 134249423Sdim let TSFlags{19} = isExtended; // Insn must be extended. 135249423Sdim bits<3> opExtendable = 0; 136249423Sdim let TSFlags{22-20} = opExtendable; // Which operand may be extended. 137249423Sdim bits<1> isExtentSigned = 0; 138249423Sdim let TSFlags{23} = isExtentSigned; // Signed or unsigned range. 139249423Sdim bits<5> opExtentBits = 0; 140249423Sdim let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending. 141249423Sdim 142249423Sdim // If an instruction is valid on a subtarget (v2-v5), set the corresponding 143249423Sdim // bit from validSubTargets. v2 is the least significant bit. 144249423Sdim // By default, instruction is valid on all subtargets. 145249423Sdim SubTarget validSubTargets = HasV2SubT; 146249423Sdim let TSFlags{32-29} = validSubTargets.Value; 147249423Sdim 148249423Sdim // Addressing mode for load/store instructions. 149249423Sdim AddrModeType addrMode = NoAddrMode; 150249423Sdim let TSFlags{35-33} = addrMode.Value; 151249423Sdim 152249423Sdim // Memory access size for mem access instructions (load/store) 153249423Sdim MemAccessSize accessSize = NoMemAccess; 154249423Sdim let TSFlags{38-36} = accessSize.Value; 155249423Sdim 156243830Sdim // Fields used for relation models. 157243830Sdim string BaseOpcode = ""; 158243830Sdim string CextOpcode = ""; 159243830Sdim string PredSense = ""; 160243830Sdim string PNewValue = ""; 161263508Sdim string NValueST = ""; // Set to "true" for new-value stores. 162243830Sdim string InputType = ""; // Input is "imm" or "reg" type. 163249423Sdim string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. 164249423Sdim string isFloat = "false"; // Set to "true" for the floating-point load/store. 165249423Sdim string isBrTaken = ""; // Set to "true"/"false" for jump instructions 166249423Sdim 167249423Sdim let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), 168249423Sdim ""); 169249423Sdim let PNewValue = !if(isPredicatedNew, "new", ""); 170263508Sdim let NValueST = !if(isNVStore, "true", "false"); 171249423Sdim 172249423Sdim // *** Must match MCTargetDesc/HexagonBaseInfo.h *** 173234285Sdim} 174234285Sdim 175234285Sdim//===----------------------------------------------------------------------===// 176234285Sdim// Intruction Classes Definitions + 177234285Sdim//===----------------------------------------------------------------------===// 178234285Sdim 179234285Sdim// LD Instruction Class in V2/V3/V4. 180234285Sdim// Definition of the instruction class NOT CHANGED. 181249423Sdimclass LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 182249423Sdim string cstr = ""> 183249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>; 184234285Sdim 185249423Sdimlet mayLoad = 1 in 186249423Sdimclass LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], 187249423Sdim string cstr = ""> 188249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 189239462Sdim 190249423Sdimclass CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 191249423Sdim string cstr = ""> 192249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 193249423Sdim 194234285Sdim// LD Instruction Class in V2/V3/V4. 195234285Sdim// Definition of the instruction class NOT CHANGED. 196249423Sdimclass LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], 197249423Sdim string cstr = ""> 198249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 199234285Sdim 200249423Sdimlet mayLoad = 1 in 201249423Sdimclass LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 202249423Sdim string cstr = ""> 203249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 204249423Sdim 205234285Sdim// ST Instruction Class in V2/V3 can take SLOT0 only. 206234285Sdim// ST Instruction Class in V4 can take SLOT0 & SLOT1. 207234285Sdim// Definition of the instruction class CHANGED from V2/V3 to V4. 208249423Sdimlet mayStore = 1 in 209249423Sdimclass STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 210249423Sdim string cstr = ""> 211249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>; 212234285Sdim 213249423Sdimclass STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], 214249423Sdim string cstr = ""> 215249423Sdim : STInst<outs, ins, asmstr, pattern, cstr>; 216239462Sdim 217249423Sdimlet mayStore = 1 in 218249423Sdimclass ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 219249423Sdim string cstr = ""> 220249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>; 221239462Sdim 222234285Sdim// ST Instruction Class in V2/V3 can take SLOT0 only. 223234285Sdim// ST Instruction Class in V4 can take SLOT0 & SLOT1. 224234285Sdim// Definition of the instruction class CHANGED from V2/V3 to V4. 225249423Sdimclass STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], 226249423Sdim string cstr = ""> 227249423Sdim : STInst<outs, ins, asmstr, pattern, cstr>; 228234285Sdim 229249423Sdim// SYSTEM Instruction Class in V4 can take SLOT0 only 230249423Sdim// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. 231249423Sdimclass SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 232249423Sdim string cstr = ""> 233249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>; 234249423Sdim 235234285Sdim// ALU32 Instruction Class in V2/V3/V4. 236234285Sdim// Definition of the instruction class NOT CHANGED. 237249423Sdimclass ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 238249423Sdim string cstr = ""> 239249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>; 240234285Sdim 241234285Sdim// ALU64 Instruction Class in V2/V3. 242234285Sdim// XTYPE Instruction Class in V4. 243234285Sdim// Definition of the instruction class NOT CHANGED. 244234285Sdim// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. 245249423Sdimclass ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 246249423Sdim string cstr = ""> 247249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>; 248234285Sdim 249249423Sdimclass ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 250249423Sdim string cstr = ""> 251249423Sdim : ALU64Inst<outs, ins, asmstr, pattern, cstr>; 252239462Sdim 253249423Sdim 254234285Sdim// M Instruction Class in V2/V3. 255234285Sdim// XTYPE Instruction Class in V4. 256234285Sdim// Definition of the instruction class NOT CHANGED. 257234285Sdim// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 258249423Sdimclass MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 259249423Sdim string cstr = ""> 260249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>; 261234285Sdim 262234285Sdim// M Instruction Class in V2/V3. 263234285Sdim// XTYPE Instruction Class in V4. 264234285Sdim// Definition of the instruction class NOT CHANGED. 265234285Sdim// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. 266249423Sdimclass MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 267249423Sdim string cstr = ""> 268249423Sdim : MInst<outs, ins, asmstr, pattern, cstr>; 269234285Sdim 270234285Sdim// S Instruction Class in V2/V3. 271234285Sdim// XTYPE Instruction Class in V4. 272234285Sdim// Definition of the instruction class NOT CHANGED. 273234285Sdim// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 274249423Sdimclass SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 275249423Sdim string cstr = ""> 276249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>; 277234285Sdim 278234285Sdim// S Instruction Class in V2/V3. 279234285Sdim// XTYPE Instruction Class in V4. 280234285Sdim// Definition of the instruction class NOT CHANGED. 281234285Sdim// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. 282249423Sdimclass SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], 283249423Sdim string cstr = ""> 284249423Sdim : SInst<outs, ins, asmstr, pattern, cstr>; 285234285Sdim 286234285Sdim// J Instruction Class in V2/V3/V4. 287234285Sdim// Definition of the instruction class NOT CHANGED. 288249423Sdimclass JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 289249423Sdim string cstr = ""> 290249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>; 291234285Sdim 292234285Sdim// JR Instruction Class in V2/V3/V4. 293234285Sdim// Definition of the instruction class NOT CHANGED. 294249423Sdimclass JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 295249423Sdim string cstr = ""> 296249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>; 297234285Sdim 298234285Sdim// CR Instruction Class in V2/V3/V4. 299234285Sdim// Definition of the instruction class NOT CHANGED. 300249423Sdimclass CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], 301249423Sdim string cstr = ""> 302249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>; 303234285Sdim 304249423Sdimlet isCodeGenOnly = 1, isPseudo = 1 in 305249423Sdimclass Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [], 306249423Sdim string cstr = ""> 307249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>; 308234285Sdim 309249423Sdimlet isCodeGenOnly = 1, isPseudo = 1 in 310249423Sdimclass Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [], 311249423Sdim string cstr = ""> 312249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>; 313234285Sdim 314249423Sdimlet isCodeGenOnly = 1, isPseudo = 1 in 315249423Sdimclass PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], 316249423Sdim string cstr=""> 317249423Sdim : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>; 318249423Sdim 319234285Sdim//===----------------------------------------------------------------------===// 320234285Sdim// Intruction Classes Definitions - 321234285Sdim//===----------------------------------------------------------------------===// 322234285Sdim 323234285Sdim 324234285Sdim// 325234285Sdim// ALU32 patterns 326234285Sdim//. 327249423Sdimclass ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern, 328249423Sdim string cstr = ""> 329249423Sdim : ALU32Inst<outs, ins, asmstr, pattern, cstr>; 330234285Sdim 331249423Sdimclass ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern, 332249423Sdim string cstr = ""> 333249423Sdim : ALU32Inst<outs, ins, asmstr, pattern, cstr>; 334234285Sdim 335249423Sdimclass ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern, 336249423Sdim string cstr = ""> 337249423Sdim : ALU32Inst<outs, ins, asmstr, pattern, cstr>; 338234285Sdim 339249423Sdimclass ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern, 340249423Sdim string cstr = ""> 341249423Sdim : ALU32Inst<outs, ins, asmstr, pattern, cstr>; 342234285Sdim 343234285Sdim// 344234285Sdim// ALU64 patterns. 345234285Sdim// 346249423Sdimclass ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern, 347249423Sdim string cstr = ""> 348249423Sdim : ALU64Inst<outs, ins, asmstr, pattern, cstr>; 349234285Sdim 350249423Sdimclass ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern, 351249423Sdim string cstr = ""> 352249423Sdim : ALU64Inst<outs, ins, asmstr, pattern, cstr>; 353239462Sdim 354234285Sdim// Post increment ST Instruction. 355249423Sdimclass STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 356249423Sdim string cstr = ""> 357249423Sdim : STInst<outs, ins, asmstr, pattern, cstr>; 358234285Sdim 359249423Sdimlet mayStore = 1 in 360249423Sdimclass STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 361249423Sdim string cstr = ""> 362249423Sdim : STInst<outs, ins, asmstr, pattern, cstr>; 363239462Sdim 364234285Sdim// Post increment LD Instruction. 365249423Sdimclass LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 366249423Sdim string cstr = ""> 367249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 368234285Sdim 369249423Sdimlet mayLoad = 1 in 370249423Sdimclass LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern = [], 371249423Sdim string cstr = ""> 372249423Sdim : LDInst<outs, ins, asmstr, pattern, cstr>; 373239462Sdim 374234285Sdim//===----------------------------------------------------------------------===// 375234285Sdim// V4 Instruction Format Definitions + 376234285Sdim//===----------------------------------------------------------------------===// 377234285Sdim 378234285Sdiminclude "HexagonInstrFormatsV4.td" 379234285Sdim 380234285Sdim//===----------------------------------------------------------------------===// 381234285Sdim// V4 Instruction Format Definitions + 382234285Sdim//===----------------------------------------------------------------------===// 383