1234285Sdim//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// 10234285Sdim// This is the top level entry point for the Hexagon target. 11234285Sdim// 12234285Sdim//===----------------------------------------------------------------------===// 13234285Sdim 14234285Sdim//===----------------------------------------------------------------------===// 15234285Sdim// Target-independent interfaces which we are implementing 16234285Sdim//===----------------------------------------------------------------------===// 17234285Sdim 18234285Sdiminclude "llvm/Target/Target.td" 19234285Sdim 20234285Sdim//===----------------------------------------------------------------------===// 21234285Sdim// Hexagon Subtarget features. 22234285Sdim//===----------------------------------------------------------------------===// 23234285Sdim 24234285Sdim// Hexagon Archtectures 25234285Sdimdef ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", 26234285Sdim "Hexagon v2">; 27234285Sdimdef ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3", 28234285Sdim "Hexagon v3">; 29234285Sdimdef ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4", 30234285Sdim "Hexagon v4">; 31239462Sdimdef ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5", 32239462Sdim "Hexagon v5">; 33234285Sdim 34234285Sdim//===----------------------------------------------------------------------===// 35249423Sdim// Hexagon Instruction Predicate Definitions. 36249423Sdim//===----------------------------------------------------------------------===// 37249423Sdimdef HasV2T : Predicate<"Subtarget.hasV2TOps()">; 38249423Sdimdef HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">; 39249423Sdimdef NoV2T : Predicate<"!Subtarget.hasV2TOps()">; 40249423Sdimdef HasV3T : Predicate<"Subtarget.hasV3TOps()">; 41249423Sdimdef HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">; 42249423Sdimdef NoV3T : Predicate<"!Subtarget.hasV3TOps()">; 43249423Sdimdef HasV4T : Predicate<"Subtarget.hasV4TOps()">; 44249423Sdimdef NoV4T : Predicate<"!Subtarget.hasV4TOps()">; 45249423Sdimdef HasV5T : Predicate<"Subtarget.hasV5TOps()">; 46249423Sdimdef NoV5T : Predicate<"!Subtarget.hasV5TOps()">; 47249423Sdimdef UseMEMOP : Predicate<"Subtarget.useMemOps()">; 48249423Sdimdef IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">; 49249423Sdim 50249423Sdim//===----------------------------------------------------------------------===// 51249423Sdim// Classes used for relation maps. 52249423Sdim//===----------------------------------------------------------------------===// 53249423Sdim// PredRel - Filter class used to relate non-predicated instructions with their 54249423Sdim// predicated forms. 55249423Sdimclass PredRel; 56249423Sdim// PredNewRel - Filter class used to relate predicated instructions with their 57249423Sdim// predicate-new forms. 58249423Sdimclass PredNewRel: PredRel; 59249423Sdim// ImmRegRel - Filter class used to relate instructions having reg-reg form 60249423Sdim// with their reg-imm counterparts. 61249423Sdimclass ImmRegRel; 62249423Sdim// NewValueRel - Filter class used to relate regular store instructions with 63249423Sdim// their new-value store form. 64249423Sdimclass NewValueRel: PredNewRel; 65249423Sdim// NewValueRel - Filter class used to relate load/store instructions having 66249423Sdim// different addressing modes with each other. 67249423Sdimclass AddrModeRel: NewValueRel; 68249423Sdim 69249423Sdim//===----------------------------------------------------------------------===// 70249423Sdim// Generate mapping table to relate non-predicate instructions with their 71249423Sdim// predicated formats - true and false. 72249423Sdim// 73249423Sdim 74249423Sdimdef getPredOpcode : InstrMapping { 75249423Sdim let FilterClass = "PredRel"; 76249423Sdim // Instructions with the same BaseOpcode and isNVStore values form a row. 77249423Sdim let RowFields = ["BaseOpcode", "isNVStore", "PNewValue"]; 78249423Sdim // Instructions with the same predicate sense form a column. 79249423Sdim let ColFields = ["PredSense"]; 80249423Sdim // The key column is the unpredicated instructions. 81249423Sdim let KeyCol = [""]; 82249423Sdim // Value columns are PredSense=true and PredSense=false 83249423Sdim let ValueCols = [["true"], ["false"]]; 84249423Sdim} 85249423Sdim 86249423Sdim//===----------------------------------------------------------------------===// 87251662Sdim// Generate mapping table to relate predicate-true instructions with their 88251662Sdim// predicate-false forms 89251662Sdim// 90251662Sdimdef getFalsePredOpcode : InstrMapping { 91251662Sdim let FilterClass = "PredRel"; 92251662Sdim let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; 93251662Sdim let ColFields = ["PredSense"]; 94251662Sdim let KeyCol = ["true"]; 95251662Sdim let ValueCols = [["false"]]; 96251662Sdim} 97251662Sdim 98251662Sdim//===----------------------------------------------------------------------===// 99251662Sdim// Generate mapping table to relate predicate-false instructions with their 100251662Sdim// predicate-true forms 101251662Sdim// 102251662Sdimdef getTruePredOpcode : InstrMapping { 103251662Sdim let FilterClass = "PredRel"; 104251662Sdim let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken"]; 105251662Sdim let ColFields = ["PredSense"]; 106251662Sdim let KeyCol = ["false"]; 107251662Sdim let ValueCols = [["true"]]; 108251662Sdim} 109251662Sdim 110251662Sdim//===----------------------------------------------------------------------===// 111249423Sdim// Generate mapping table to relate predicated instructions with their .new 112249423Sdim// format. 113249423Sdim// 114249423Sdimdef getPredNewOpcode : InstrMapping { 115249423Sdim let FilterClass = "PredNewRel"; 116251662Sdim let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 117249423Sdim let ColFields = ["PNewValue"]; 118249423Sdim let KeyCol = [""]; 119249423Sdim let ValueCols = [["new"]]; 120249423Sdim} 121249423Sdim 122249423Sdim//===----------------------------------------------------------------------===// 123263508Sdim// Generate mapping table to relate .new predicated instructions with their old 124263508Sdim// format. 125263508Sdim// 126263508Sdimdef getPredOldOpcode : InstrMapping { 127263508Sdim let FilterClass = "PredNewRel"; 128263508Sdim let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; 129263508Sdim let ColFields = ["PNewValue"]; 130263508Sdim let KeyCol = ["new"]; 131263508Sdim let ValueCols = [[""]]; 132263508Sdim} 133263508Sdim 134263508Sdim//===----------------------------------------------------------------------===// 135249423Sdim// Generate mapping table to relate store instructions with their new-value 136249423Sdim// format. 137249423Sdim// 138249423Sdimdef getNewValueOpcode : InstrMapping { 139249423Sdim let FilterClass = "NewValueRel"; 140249423Sdim let RowFields = ["BaseOpcode", "PredSense", "PNewValue"]; 141263508Sdim let ColFields = ["NValueST"]; 142263508Sdim let KeyCol = ["false"]; 143263508Sdim let ValueCols = [["true"]]; 144249423Sdim} 145249423Sdim 146263508Sdim//===----------------------------------------------------------------------===// 147263508Sdim// Generate mapping table to relate new-value store instructions with their old 148263508Sdim// format. 149263508Sdim// 150263508Sdimdef getNonNVStore : InstrMapping { 151263508Sdim let FilterClass = "NewValueRel"; 152263508Sdim let RowFields = ["BaseOpcode", "PredSense", "PNewValue"]; 153263508Sdim let ColFields = ["NValueST"]; 154263508Sdim let KeyCol = ["true"]; 155263508Sdim let ValueCols = [["false"]]; 156263508Sdim} 157263508Sdim 158249423Sdimdef getBasedWithImmOffset : InstrMapping { 159249423Sdim let FilterClass = "AddrModeRel"; 160249423Sdim let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 161249423Sdim "isMEMri", "isFloat"]; 162249423Sdim let ColFields = ["addrMode"]; 163249423Sdim let KeyCol = ["Absolute"]; 164249423Sdim let ValueCols = [["BaseImmOffset"]]; 165249423Sdim} 166249423Sdim 167249423Sdimdef getBaseWithRegOffset : InstrMapping { 168249423Sdim let FilterClass = "AddrModeRel"; 169249423Sdim let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 170249423Sdim let ColFields = ["addrMode"]; 171249423Sdim let KeyCol = ["BaseImmOffset"]; 172249423Sdim let ValueCols = [["BaseRegOffset"]]; 173249423Sdim} 174249423Sdim 175249423Sdimdef getRegForm : InstrMapping { 176249423Sdim let FilterClass = "ImmRegRel"; 177249423Sdim let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 178249423Sdim let ColFields = ["InputType"]; 179249423Sdim let KeyCol = ["imm"]; 180249423Sdim let ValueCols = [["reg"]]; 181249423Sdim} 182249423Sdim 183249423Sdim//===----------------------------------------------------------------------===// 184234285Sdim// Register File, Calling Conv, Instruction Descriptions 185234285Sdim//===----------------------------------------------------------------------===// 186234285Sdiminclude "HexagonSchedule.td" 187234285Sdiminclude "HexagonRegisterInfo.td" 188234285Sdiminclude "HexagonCallingConv.td" 189234285Sdiminclude "HexagonInstrInfo.td" 190234285Sdiminclude "HexagonIntrinsics.td" 191234285Sdiminclude "HexagonIntrinsicsDerived.td" 192234285Sdim 193234285Sdimdef HexagonInstrInfo : InstrInfo; 194234285Sdim 195234285Sdim//===----------------------------------------------------------------------===// 196234285Sdim// Hexagon processors supported. 197234285Sdim//===----------------------------------------------------------------------===// 198234285Sdim 199239462Sdimclass Proc<string Name, SchedMachineModel Model, 200234285Sdim list<SubtargetFeature> Features> 201239462Sdim : ProcessorModel<Name, Model, Features>; 202234285Sdim 203239462Sdimdef : Proc<"hexagonv2", HexagonModel, [ArchV2]>; 204239462Sdimdef : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; 205239462Sdimdef : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; 206239462Sdimdef : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; 207234285Sdim 208239462Sdim 209234285Sdim// Hexagon Uses the MC printer for assembler output, so make sure the TableGen 210234285Sdim// AsmWriter bits get associated with the correct class. 211234285Sdimdef HexagonAsmWriter : AsmWriter { 212234285Sdim string AsmWriterClassName = "InstPrinter"; 213234285Sdim bit isMCAsmWriter = 1; 214234285Sdim} 215234285Sdim 216234285Sdim//===----------------------------------------------------------------------===// 217234285Sdim// Declare the target which we are implementing 218234285Sdim//===----------------------------------------------------------------------===// 219234285Sdim 220234285Sdimdef Hexagon : Target { 221234285Sdim // Pull in Instruction Info: 222234285Sdim let InstructionSet = HexagonInstrInfo; 223234285Sdim 224234285Sdim let AssemblyWriters = [HexagonAsmWriter]; 225234285Sdim} 226