1224133Sdim//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file provides ARM specific target descriptions. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14224133Sdim#ifndef ARMMCTARGETDESC_H 15224133Sdim#define ARMMCTARGETDESC_H 16224133Sdim 17226633Sdim#include "llvm/Support/DataTypes.h" 18224133Sdim#include <string> 19224133Sdim 20224133Sdimnamespace llvm { 21263508Sdimclass formatted_raw_ostream; 22226633Sdimclass MCAsmBackend; 23226633Sdimclass MCCodeEmitter; 24226633Sdimclass MCContext; 25226633Sdimclass MCInstrInfo; 26263508Sdimclass MCInstPrinter; 27226633Sdimclass MCObjectWriter; 28239462Sdimclass MCRegisterInfo; 29224133Sdimclass MCSubtargetInfo; 30263508Sdimclass MCStreamer; 31263508Sdimclass MCRelocationInfo; 32226633Sdimclass StringRef; 33224133Sdimclass Target; 34226633Sdimclass raw_ostream; 35224133Sdim 36224133Sdimextern Target TheARMTarget, TheThumbTarget; 37224133Sdim 38224133Sdimnamespace ARM_MC { 39239462Sdim std::string ParseARMTriple(StringRef TT, StringRef CPU); 40224133Sdim 41224133Sdim /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance. 42224133Sdim /// This is exposed so Asm parser, etc. do not need to go through 43224133Sdim /// TargetRegistry. 44224133Sdim MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 45224133Sdim StringRef FS); 46224133Sdim} 47224133Sdim 48263508SdimMCStreamer *createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 49263508Sdim bool isVerboseAsm, bool useLoc, bool useCFI, 50263508Sdim bool useDwarfDirectory, 51263508Sdim MCInstPrinter *InstPrint, MCCodeEmitter *CE, 52263508Sdim MCAsmBackend *TAB, bool ShowInst); 53263508Sdim 54226633SdimMCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII, 55239462Sdim const MCRegisterInfo &MRI, 56226633Sdim const MCSubtargetInfo &STI, 57226633Sdim MCContext &Ctx); 58226633Sdim 59263508SdimMCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, 60263508Sdim StringRef TT, StringRef CPU); 61226633Sdim 62234353Sdim/// createARMELFObjectWriter - Construct an ELF Mach-O object writer. 63234353SdimMCObjectWriter *createARMELFObjectWriter(raw_ostream &OS, 64234353Sdim uint8_t OSABI); 65234353Sdim 66226633Sdim/// createARMMachObjectWriter - Construct an ARM Mach-O object writer. 67226633SdimMCObjectWriter *createARMMachObjectWriter(raw_ostream &OS, 68226633Sdim bool Is64Bit, 69226633Sdim uint32_t CPUType, 70226633Sdim uint32_t CPUSubtype); 71226633Sdim 72263508Sdim 73263508Sdim/// createARMMachORelocationInfo - Construct ARM Mach-O relocation info. 74263508SdimMCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 75224133Sdim} // End llvm namespace 76224133Sdim 77224133Sdim// Defines symbolic names for ARM registers. This defines a mapping from 78224133Sdim// register name to register number. 79224133Sdim// 80224133Sdim#define GET_REGINFO_ENUM 81224133Sdim#include "ARMGenRegisterInfo.inc" 82224133Sdim 83224133Sdim// Defines symbolic names for the ARM instructions. 84224133Sdim// 85224133Sdim#define GET_INSTRINFO_ENUM 86224133Sdim#include "ARMGenInstrInfo.inc" 87224133Sdim 88224133Sdim#define GET_SUBTARGETINFO_ENUM 89224133Sdim#include "ARMGenSubtargetInfo.inc" 90224133Sdim 91224133Sdim#endif 92