1243789Sdim//=- ARMScheduleSwift.td - Swift Scheduling Definitions -*- tablegen -*----===// 2243789Sdim// 3243789Sdim// The LLVM Compiler Infrastructure 4243789Sdim// 5243789Sdim// This file is distributed under the University of Illinois Open Source 6243789Sdim// License. See LICENSE.TXT for details. 7243789Sdim// 8243789Sdim//===----------------------------------------------------------------------===// 9243789Sdim// 10243789Sdim// This file defines the itinerary class data for the Swift processor.. 11243789Sdim// 12243789Sdim//===----------------------------------------------------------------------===// 13243789Sdim 14243789Sdim// ===---------------------------------------------------------------------===// 15243789Sdim// This section contains legacy support for itineraries. This is 16243789Sdim// required until SD and PostRA schedulers are replaced by MachineScheduler. 17243789Sdim 18243789Sdimdef SW_DIS0 : FuncUnit; 19243789Sdimdef SW_DIS1 : FuncUnit; 20243789Sdimdef SW_DIS2 : FuncUnit; 21243789Sdim 22243789Sdimdef SW_ALU0 : FuncUnit; 23243789Sdimdef SW_ALU1 : FuncUnit; 24243789Sdimdef SW_LS : FuncUnit; 25243789Sdimdef SW_IDIV : FuncUnit; 26243789Sdimdef SW_FDIV : FuncUnit; 27243789Sdim 28243789Sdim// FIXME: Need bypasses. 29243789Sdim// FIXME: Model the multiple stages of IIC_iMOVix2, IIC_iMOVix2addpc, and 30243789Sdim// IIC_iMOVix2ld better. 31243789Sdim// FIXME: Model the special immediate shifts that are not microcoded. 32243789Sdim// FIXME: Do we need to model the fact that uses of r15 in a micro-op force it 33243789Sdim// to issue on pipe 1? 34243789Sdim// FIXME: Model the pipelined behavior of CMP / TST instructions. 35243789Sdim// FIXME: Better model the microcode stages of multiply instructions, especially 36243789Sdim// conditional variants. 37243789Sdim// FIXME: Add preload instruction when it is documented. 38243789Sdim// FIXME: Model non-pipelined nature of FP div / sqrt unit. 39243789Sdim 40243789Sdimdef SwiftItineraries : ProcessorItineraries< 41243789Sdim [SW_DIS0, SW_DIS1, SW_DIS2, SW_ALU0, SW_ALU1, SW_LS, SW_IDIV, SW_FDIV], [], [ 42243789Sdim // 43243789Sdim // Move instructions, unconditional 44243789Sdim InstrItinData<IIC_iMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 45243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 46243789Sdim [1]>, 47243789Sdim InstrItinData<IIC_iMOVr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 48243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 49243789Sdim [1]>, 50243789Sdim InstrItinData<IIC_iMOVsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 51243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 52243789Sdim [1]>, 53243789Sdim InstrItinData<IIC_iMOVsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 54243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 55243789Sdim [1]>, 56243789Sdim InstrItinData<IIC_iMOVix2 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 57243789Sdim InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 58243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 59243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 60243789Sdim [2]>, 61243789Sdim InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 62243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 63243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 64243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 65243789Sdim [3]>, 66243789Sdim InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 67243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 68243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 69243789Sdim InstrStage<1, [SW_LS]>], 70243789Sdim [5]>, 71243789Sdim // 72243789Sdim // MVN instructions 73243789Sdim InstrItinData<IIC_iMVNi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 74243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 75243789Sdim [1]>, 76243789Sdim InstrItinData<IIC_iMVNr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 77243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 78243789Sdim [1]>, 79243789Sdim InstrItinData<IIC_iMVNsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 80243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 81243789Sdim [1]>, 82243789Sdim InstrItinData<IIC_iMVNsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 83243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 84243789Sdim [1]>, 85243789Sdim // 86243789Sdim // No operand cycles 87243789Sdim InstrItinData<IIC_iALUx , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 88243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>]>, 89243789Sdim // 90243789Sdim // Binary Instructions that produce a result 91243789Sdim InstrItinData<IIC_iALUi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 92243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 93243789Sdim [1, 1]>, 94243789Sdim InstrItinData<IIC_iALUr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 95243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 96243789Sdim [1, 1, 1]>, 97243789Sdim InstrItinData<IIC_iALUsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 98243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 99243789Sdim [2, 1, 1]>, 100243789Sdim InstrItinData<IIC_iALUsir,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 101243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 102243789Sdim [2, 1, 1]>, 103243789Sdim InstrItinData<IIC_iALUsr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 104243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 105243789Sdim [2, 1, 1, 1]>, 106243789Sdim // 107243789Sdim // Bitwise Instructions that produce a result 108243789Sdim InstrItinData<IIC_iBITi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 109243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 110243789Sdim [1, 1]>, 111243789Sdim InstrItinData<IIC_iBITr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 112243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 113243789Sdim [1, 1, 1]>, 114243789Sdim InstrItinData<IIC_iBITsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 115243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 116243789Sdim [2, 1, 1]>, 117243789Sdim InstrItinData<IIC_iBITsr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 118243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 119243789Sdim [2, 1, 1, 1]>, 120243789Sdim // 121243789Sdim // Unary Instructions that produce a result 122243789Sdim 123243789Sdim // CLZ, RBIT, etc. 124243789Sdim InstrItinData<IIC_iUNAr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 125243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 126243789Sdim [1, 1]>, 127243789Sdim 128243789Sdim // BFC, BFI, UBFX, SBFX 129243789Sdim InstrItinData<IIC_iUNAsi, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 130243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 131243789Sdim [2, 1]>, 132243789Sdim 133243789Sdim // 134243789Sdim // Zero and sign extension instructions 135243789Sdim InstrItinData<IIC_iEXTr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 136243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 137243789Sdim [1, 1]>, 138243789Sdim InstrItinData<IIC_iEXTAr, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 139243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 140243789Sdim [1, 1, 1]>, 141243789Sdim InstrItinData<IIC_iEXTAsr,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 142243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 143243789Sdim [1, 1, 1, 1]>, 144243789Sdim // 145243789Sdim // Compare instructions 146243789Sdim InstrItinData<IIC_iCMPi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 147243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 148243789Sdim [1]>, 149243789Sdim InstrItinData<IIC_iCMPr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 150243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 151243789Sdim [1, 1]>, 152243789Sdim InstrItinData<IIC_iCMPsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 153243789Sdim InstrStage<2, [SW_ALU0, SW_ALU1]>], 154243789Sdim [1, 1]>, 155243789Sdim InstrItinData<IIC_iCMPsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 156243789Sdim InstrStage<2, [SW_ALU0, SW_ALU1]>], 157243789Sdim [1, 1, 1]>, 158243789Sdim // 159243789Sdim // Test instructions 160243789Sdim InstrItinData<IIC_iTSTi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 161243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 162243789Sdim [1]>, 163243789Sdim InstrItinData<IIC_iTSTr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 164243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 165243789Sdim [1, 1]>, 166243789Sdim InstrItinData<IIC_iTSTsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 167243789Sdim InstrStage<2, [SW_ALU0, SW_ALU1]>], 168243789Sdim [1, 1]>, 169243789Sdim InstrItinData<IIC_iTSTsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 170243789Sdim InstrStage<2, [SW_ALU0, SW_ALU1]>], 171243789Sdim [1, 1, 1]>, 172243789Sdim // 173243789Sdim // Move instructions, conditional 174243789Sdim // FIXME: Correctly model the extra input dep on the destination. 175243789Sdim InstrItinData<IIC_iCMOVi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 176243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 177243789Sdim [1]>, 178243789Sdim InstrItinData<IIC_iCMOVr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 179243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 180243789Sdim [1, 1]>, 181243789Sdim InstrItinData<IIC_iCMOVsi , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 182243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 183243789Sdim [1, 1]>, 184243789Sdim InstrItinData<IIC_iCMOVsr , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 185243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 186243789Sdim [2, 1, 1]>, 187243789Sdim InstrItinData<IIC_iCMOVix2, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 188243789Sdim InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 189243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>, 190243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 191243789Sdim [2]>, 192243789Sdim 193243789Sdim // Integer multiply pipeline 194243789Sdim // 195243789Sdim InstrItinData<IIC_iMUL16 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 196243789Sdim InstrStage<1, [SW_ALU0]>], 197243789Sdim [3, 1, 1]>, 198243789Sdim InstrItinData<IIC_iMAC16 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 199243789Sdim InstrStage<1, [SW_ALU0]>], 200243789Sdim [3, 1, 1, 1]>, 201243789Sdim InstrItinData<IIC_iMUL32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 202243789Sdim InstrStage<1, [SW_ALU0]>], 203243789Sdim [4, 1, 1]>, 204243789Sdim InstrItinData<IIC_iMAC32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 205243789Sdim InstrStage<1, [SW_ALU0]>], 206243789Sdim [4, 1, 1, 1]>, 207243789Sdim InstrItinData<IIC_iMUL64 , [InstrStage<1, [SW_DIS0], 0>, 208243789Sdim InstrStage<1, [SW_DIS1], 0>, 209243789Sdim InstrStage<1, [SW_DIS2], 0>, 210243789Sdim InstrStage<1, [SW_ALU0], 1>, 211243789Sdim InstrStage<1, [SW_ALU0], 3>, 212243789Sdim InstrStage<1, [SW_ALU0]>], 213243789Sdim [5, 5, 1, 1]>, 214243789Sdim InstrItinData<IIC_iMAC64 , [InstrStage<1, [SW_DIS0], 0>, 215243789Sdim InstrStage<1, [SW_DIS1], 0>, 216243789Sdim InstrStage<1, [SW_DIS2], 0>, 217243789Sdim InstrStage<1, [SW_ALU0], 1>, 218243789Sdim InstrStage<1, [SW_ALU0], 1>, 219243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 3>, 220243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 221243789Sdim [5, 6, 1, 1]>, 222243789Sdim // 223243789Sdim // Integer divide 224243789Sdim InstrItinData<IIC_iDIV , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 225243789Sdim InstrStage<1, [SW_ALU0], 0>, 226243789Sdim InstrStage<14, [SW_IDIV]>], 227243789Sdim [14, 1, 1]>, 228243789Sdim 229243789Sdim // Integer load pipeline 230243789Sdim // FIXME: The timings are some rough approximations 231243789Sdim // 232243789Sdim // Immediate offset 233243789Sdim InstrItinData<IIC_iLoad_i , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 234243789Sdim InstrStage<1, [SW_LS]>], 235243789Sdim [3, 1]>, 236243789Sdim InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 237243789Sdim InstrStage<1, [SW_LS]>], 238243789Sdim [3, 1]>, 239243789Sdim InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [SW_DIS0], 0>, 240243789Sdim InstrStage<1, [SW_DIS1], 0>, 241243789Sdim InstrStage<1, [SW_LS], 1>, 242243789Sdim InstrStage<1, [SW_LS]>], 243243789Sdim [3, 4, 1]>, 244243789Sdim // 245243789Sdim // Register offset 246243789Sdim InstrItinData<IIC_iLoad_r , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 247243789Sdim InstrStage<1, [SW_LS]>], 248243789Sdim [3, 1, 1]>, 249243789Sdim InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 250243789Sdim InstrStage<1, [SW_LS]>], 251243789Sdim [3, 1, 1]>, 252243789Sdim InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [SW_DIS0], 0>, 253243789Sdim InstrStage<1, [SW_DIS1], 0>, 254243789Sdim InstrStage<1, [SW_DIS2], 0>, 255243789Sdim InstrStage<1, [SW_LS], 1>, 256243789Sdim InstrStage<1, [SW_LS], 3>, 257243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 258243789Sdim [3, 4, 1, 1]>, 259243789Sdim // 260243789Sdim // Scaled register offset 261243789Sdim InstrItinData<IIC_iLoad_si , [InstrStage<1, [SW_DIS0], 0>, 262243789Sdim InstrStage<1, [SW_DIS1], 0>, 263243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 264243789Sdim InstrStage<1, [SW_LS]>], 265243789Sdim [5, 1, 1]>, 266243789Sdim InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [SW_DIS0], 0>, 267243789Sdim InstrStage<1, [SW_DIS1], 0>, 268243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 269243789Sdim InstrStage<1, [SW_LS]>], 270243789Sdim [5, 1, 1]>, 271243789Sdim // 272243789Sdim // Immediate offset with update 273243789Sdim InstrItinData<IIC_iLoad_iu , [InstrStage<1, [SW_DIS0], 0>, 274243789Sdim InstrStage<1, [SW_DIS1], 0>, 275243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 276243789Sdim InstrStage<1, [SW_LS]>], 277243789Sdim [3, 1, 1]>, 278243789Sdim InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [SW_DIS0], 0>, 279243789Sdim InstrStage<1, [SW_DIS1], 0>, 280243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 281243789Sdim InstrStage<1, [SW_LS]>], 282243789Sdim [3, 1, 1]>, 283243789Sdim // 284243789Sdim // Register offset with update 285243789Sdim InstrItinData<IIC_iLoad_ru , [InstrStage<1, [SW_DIS0], 0>, 286243789Sdim InstrStage<1, [SW_DIS1], 0>, 287243789Sdim InstrStage<1, [SW_ALU0], 1>, 288243789Sdim InstrStage<1, [SW_LS]>], 289243789Sdim [3, 1, 1, 1]>, 290243789Sdim InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [SW_DIS0], 0>, 291243789Sdim InstrStage<1, [SW_DIS1], 0>, 292243789Sdim InstrStage<1, [SW_ALU0], 1>, 293243789Sdim InstrStage<1, [SW_LS]>], 294243789Sdim [3, 1, 1, 1]>, 295243789Sdim InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [SW_DIS0], 0>, 296243789Sdim InstrStage<1, [SW_DIS1], 0>, 297243789Sdim InstrStage<1, [SW_DIS2], 0>, 298243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 0>, 299243789Sdim InstrStage<1, [SW_LS], 3>, 300243789Sdim InstrStage<1, [SW_LS], 0>, 301243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 302243789Sdim [3, 4, 1, 1]>, 303243789Sdim // 304243789Sdim // Scaled register offset with update 305243789Sdim InstrItinData<IIC_iLoad_siu , [InstrStage<1, [SW_DIS0], 0>, 306243789Sdim InstrStage<1, [SW_DIS1], 0>, 307243789Sdim InstrStage<1, [SW_DIS2], 0>, 308243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 309243789Sdim InstrStage<1, [SW_LS], 3>, 310243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 311243789Sdim [5, 3, 1, 1]>, 312243789Sdim InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [SW_DIS0], 0>, 313243789Sdim InstrStage<1, [SW_DIS1], 0>, 314243789Sdim InstrStage<1, [SW_DIS2], 0>, 315243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 316243789Sdim InstrStage<1, [SW_LS], 0>, 317243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 318243789Sdim [5, 3, 1, 1]>, 319243789Sdim // 320243789Sdim // Load multiple, def is the 5th operand. 321243789Sdim // FIXME: This assumes 3 to 4 registers. 322243789Sdim InstrItinData<IIC_iLoad_m , [InstrStage<1, [SW_DIS0], 0>, 323243789Sdim InstrStage<1, [SW_DIS1], 0>, 324243789Sdim InstrStage<1, [SW_DIS2], 0>, 325243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 326243789Sdim InstrStage<1, [SW_LS]>], 327243789Sdim [1, 1, 1, 1, 3], [], -1>, // dynamic uops 328243789Sdim 329243789Sdim // 330243789Sdim // Load multiple + update, defs are the 1st and 5th operands. 331243789Sdim InstrItinData<IIC_iLoad_mu , [InstrStage<1, [SW_DIS0], 0>, 332243789Sdim InstrStage<1, [SW_DIS1], 0>, 333243789Sdim InstrStage<1, [SW_DIS2], 0>, 334243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 0>, 335243789Sdim InstrStage<1, [SW_LS], 3>, 336243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 337243789Sdim [2, 1, 1, 1, 3], [], -1>, // dynamic uops 338243789Sdim // 339243789Sdim // Load multiple plus branch 340243789Sdim InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [SW_DIS0], 0>, 341243789Sdim InstrStage<1, [SW_DIS1], 0>, 342243789Sdim InstrStage<1, [SW_DIS2], 0>, 343243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 344243789Sdim InstrStage<1, [SW_LS]>], 345243789Sdim [1, 1, 1, 1, 3], [], -1>, // dynamic uops 346243789Sdim // 347243789Sdim // Pop, def is the 3rd operand. 348243789Sdim InstrItinData<IIC_iPop , [InstrStage<1, [SW_DIS0], 0>, 349243789Sdim InstrStage<1, [SW_DIS1], 0>, 350243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 351243789Sdim InstrStage<1, [SW_LS]>], 352243789Sdim [1, 1, 3], [], -1>, // dynamic uops 353243789Sdim // 354243789Sdim // Pop + branch, def is the 3rd operand. 355243789Sdim InstrItinData<IIC_iPop_Br, [InstrStage<1, [SW_DIS0], 0>, 356243789Sdim InstrStage<1, [SW_DIS1], 0>, 357243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 358243789Sdim InstrStage<1, [SW_LS]>], 359243789Sdim [1, 1, 3], [], -1>, // dynamic uops 360243789Sdim 361243789Sdim // 362243789Sdim // iLoadi + iALUr for t2LDRpci_pic. 363243789Sdim InstrItinData<IIC_iLoadiALU, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 364243789Sdim InstrStage<1, [SW_LS], 3>, 365243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 366243789Sdim [4, 1]>, 367243789Sdim 368243789Sdim // Integer store pipeline 369243789Sdim /// 370243789Sdim // Immediate offset 371243789Sdim InstrItinData<IIC_iStore_i , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 372243789Sdim InstrStage<1, [SW_LS]>], 373243789Sdim [1, 1]>, 374243789Sdim InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 375243789Sdim InstrStage<1, [SW_LS]>], 376243789Sdim [1, 1]>, 377243789Sdim InstrItinData<IIC_iStore_d_i, [InstrStage<1, [SW_DIS0], 0>, 378243789Sdim InstrStage<1, [SW_DIS1], 0>, 379243789Sdim InstrStage<1, [SW_DIS2], 0>, 380243789Sdim InstrStage<1, [SW_LS], 0>, 381243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 382243789Sdim InstrStage<1, [SW_LS]>], 383243789Sdim [1, 1]>, 384243789Sdim // 385243789Sdim // Register offset 386243789Sdim InstrItinData<IIC_iStore_r , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 387243789Sdim InstrStage<1, [SW_LS]>], 388243789Sdim [1, 1, 1]>, 389243789Sdim InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 390243789Sdim InstrStage<1, [SW_LS]>], 391243789Sdim [1, 1, 1]>, 392243789Sdim InstrItinData<IIC_iStore_d_r, [InstrStage<1, [SW_DIS0], 0>, 393243789Sdim InstrStage<1, [SW_DIS1], 0>, 394243789Sdim InstrStage<1, [SW_DIS2], 0>, 395243789Sdim InstrStage<1, [SW_LS], 0>, 396243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 397243789Sdim InstrStage<1, [SW_LS]>], 398243789Sdim [1, 1, 1]>, 399243789Sdim // 400243789Sdim // Scaled register offset 401243789Sdim InstrItinData<IIC_iStore_si , [InstrStage<1, [SW_DIS0], 0>, 402243789Sdim InstrStage<1, [SW_DIS1], 0>, 403243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 404243789Sdim InstrStage<1, [SW_LS]>], 405243789Sdim [1, 1, 1]>, 406243789Sdim InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [SW_DIS0], 0>, 407243789Sdim InstrStage<1, [SW_DIS1], 0>, 408243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 409243789Sdim InstrStage<1, [SW_LS]>], 410243789Sdim [1, 1, 1]>, 411243789Sdim // 412243789Sdim // Immediate offset with update 413243789Sdim InstrItinData<IIC_iStore_iu , [InstrStage<1, [SW_DIS0], 0>, 414243789Sdim InstrStage<1, [SW_DIS1], 0>, 415243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 416243789Sdim InstrStage<1, [SW_LS]>], 417243789Sdim [1, 1, 1]>, 418243789Sdim InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [SW_DIS0], 0>, 419243789Sdim InstrStage<1, [SW_DIS1], 0>, 420243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 421243789Sdim InstrStage<1, [SW_LS]>], 422243789Sdim [1, 1, 1]>, 423243789Sdim // 424243789Sdim // Register offset with update 425243789Sdim InstrItinData<IIC_iStore_ru , [InstrStage<1, [SW_DIS0], 0>, 426243789Sdim InstrStage<1, [SW_DIS1], 0>, 427243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 428243789Sdim InstrStage<1, [SW_LS]>], 429243789Sdim [1, 1, 1, 1]>, 430243789Sdim InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [SW_DIS0], 0>, 431243789Sdim InstrStage<1, [SW_DIS1], 0>, 432243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 433243789Sdim InstrStage<1, [SW_LS]>], 434243789Sdim [1, 1, 1, 1]>, 435243789Sdim InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [SW_DIS0], 0>, 436243789Sdim InstrStage<1, [SW_DIS1], 0>, 437243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 438243789Sdim InstrStage<1, [SW_LS]>], 439243789Sdim [1, 1, 1, 1]>, 440243789Sdim // 441243789Sdim // Scaled register offset with update 442243789Sdim InstrItinData<IIC_iStore_siu, [InstrStage<1, [SW_DIS0], 0>, 443243789Sdim InstrStage<1, [SW_DIS1], 0>, 444243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 445243789Sdim InstrStage<1, [SW_LS], 0>, 446243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>], 447243789Sdim [3, 1, 1, 1]>, 448243789Sdim InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [SW_DIS0], 0>, 449243789Sdim InstrStage<1, [SW_DIS1], 0>, 450243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 2>, 451243789Sdim InstrStage<1, [SW_LS], 0>, 452243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>], 453243789Sdim [3, 1, 1, 1]>, 454243789Sdim // 455243789Sdim // Store multiple 456243789Sdim InstrItinData<IIC_iStore_m , [InstrStage<1, [SW_DIS0], 0>, 457243789Sdim InstrStage<1, [SW_DIS1], 0>, 458243789Sdim InstrStage<1, [SW_DIS2], 0>, 459243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 460243789Sdim InstrStage<1, [SW_LS], 1>, 461243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 462243789Sdim InstrStage<1, [SW_LS], 1>, 463243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 464243789Sdim InstrStage<1, [SW_LS]>], 465243789Sdim [], [], -1>, // dynamic uops 466243789Sdim // 467243789Sdim // Store multiple + update 468243789Sdim InstrItinData<IIC_iStore_mu, [InstrStage<1, [SW_DIS0], 0>, 469243789Sdim InstrStage<1, [SW_DIS1], 0>, 470243789Sdim InstrStage<1, [SW_DIS2], 0>, 471243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 472243789Sdim InstrStage<1, [SW_LS], 1>, 473243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 474243789Sdim InstrStage<1, [SW_LS], 1>, 475243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1], 1>, 476243789Sdim InstrStage<1, [SW_LS]>], 477243789Sdim [2], [], -1>, // dynamic uops 478243789Sdim 479243789Sdim // 480243789Sdim // Preload 481243789Sdim InstrItinData<IIC_Preload, [InstrStage<1, [SW_DIS0], 0>], [1, 1]>, 482243789Sdim 483243789Sdim // Branch 484243789Sdim // 485243789Sdim // no delay slots, so the latency of a branch is unimportant 486243789Sdim InstrItinData<IIC_Br , [InstrStage<1, [SW_DIS0], 0>]>, 487243789Sdim 488243789Sdim // FP Special Register to Integer Register File Move 489243789Sdim InstrItinData<IIC_fpSTAT , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 490243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 491243789Sdim [1]>, 492243789Sdim // 493243789Sdim // Single-precision FP Unary 494243789Sdim // 495243789Sdim // Most floating-point moves get issued on ALU0. 496243789Sdim InstrItinData<IIC_fpUNA32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 497243789Sdim InstrStage<1, [SW_ALU0]>], 498243789Sdim [2, 1]>, 499243789Sdim // 500243789Sdim // Double-precision FP Unary 501243789Sdim InstrItinData<IIC_fpUNA64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 502243789Sdim InstrStage<1, [SW_ALU0]>], 503243789Sdim [2, 1]>, 504243789Sdim 505243789Sdim // 506243789Sdim // Single-precision FP Compare 507243789Sdim InstrItinData<IIC_fpCMP32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 508243789Sdim InstrStage<1, [SW_ALU0]>], 509243789Sdim [1, 1]>, 510243789Sdim // 511243789Sdim // Double-precision FP Compare 512243789Sdim InstrItinData<IIC_fpCMP64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 513243789Sdim InstrStage<1, [SW_ALU0]>], 514243789Sdim [1, 1]>, 515243789Sdim // 516243789Sdim // Single to Double FP Convert 517243789Sdim InstrItinData<IIC_fpCVTSD , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 518243789Sdim InstrStage<1, [SW_ALU1]>], 519243789Sdim [4, 1]>, 520243789Sdim // 521243789Sdim // Double to Single FP Convert 522243789Sdim InstrItinData<IIC_fpCVTDS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 523243789Sdim InstrStage<1, [SW_ALU1]>], 524243789Sdim [4, 1]>, 525243789Sdim 526243789Sdim // 527243789Sdim // Single to Half FP Convert 528243789Sdim InstrItinData<IIC_fpCVTSH , [InstrStage<1, [SW_DIS0], 0>, 529243789Sdim InstrStage<1, [SW_DIS1], 0>, 530243789Sdim InstrStage<1, [SW_ALU1], 4>, 531243789Sdim InstrStage<1, [SW_ALU1]>], 532243789Sdim [6, 1]>, 533243789Sdim // 534243789Sdim // Half to Single FP Convert 535243789Sdim InstrItinData<IIC_fpCVTHS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 536243789Sdim InstrStage<1, [SW_ALU1]>], 537243789Sdim [4, 1]>, 538243789Sdim 539243789Sdim // 540243789Sdim // Single-Precision FP to Integer Convert 541243789Sdim InstrItinData<IIC_fpCVTSI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 542243789Sdim InstrStage<1, [SW_ALU1]>], 543243789Sdim [4, 1]>, 544243789Sdim // 545243789Sdim // Double-Precision FP to Integer Convert 546243789Sdim InstrItinData<IIC_fpCVTDI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 547243789Sdim InstrStage<1, [SW_ALU1]>], 548243789Sdim [4, 1]>, 549243789Sdim // 550243789Sdim // Integer to Single-Precision FP Convert 551243789Sdim InstrItinData<IIC_fpCVTIS , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 552243789Sdim InstrStage<1, [SW_ALU1]>], 553243789Sdim [4, 1]>, 554243789Sdim // 555243789Sdim // Integer to Double-Precision FP Convert 556243789Sdim InstrItinData<IIC_fpCVTID , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 557243789Sdim InstrStage<1, [SW_ALU1]>], 558243789Sdim [4, 1]>, 559243789Sdim // 560243789Sdim // Single-precision FP ALU 561243789Sdim InstrItinData<IIC_fpALU32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 562243789Sdim InstrStage<1, [SW_ALU0]>], 563243789Sdim [2, 1, 1]>, 564243789Sdim // 565243789Sdim // Double-precision FP ALU 566243789Sdim InstrItinData<IIC_fpALU64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 567243789Sdim InstrStage<1, [SW_ALU0]>], 568243789Sdim [2, 1, 1]>, 569243789Sdim // 570243789Sdim // Single-precision FP Multiply 571243789Sdim InstrItinData<IIC_fpMUL32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 572243789Sdim InstrStage<1, [SW_ALU1]>], 573243789Sdim [4, 1, 1]>, 574243789Sdim // 575243789Sdim // Double-precision FP Multiply 576243789Sdim InstrItinData<IIC_fpMUL64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 577243789Sdim InstrStage<1, [SW_ALU1]>], 578243789Sdim [6, 1, 1]>, 579243789Sdim // 580243789Sdim // Single-precision FP MAC 581243789Sdim InstrItinData<IIC_fpMAC32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 582243789Sdim InstrStage<1, [SW_ALU1]>], 583243789Sdim [8, 1, 1]>, 584243789Sdim // 585243789Sdim // Double-precision FP MAC 586243789Sdim InstrItinData<IIC_fpMAC64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 587243789Sdim InstrStage<1, [SW_ALU1]>], 588243789Sdim [12, 1, 1]>, 589243789Sdim // 590243789Sdim // Single-precision Fused FP MAC 591243789Sdim InstrItinData<IIC_fpFMAC32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 592243789Sdim InstrStage<1, [SW_ALU1]>], 593243789Sdim [8, 1, 1]>, 594243789Sdim // 595243789Sdim // Double-precision Fused FP MAC 596243789Sdim InstrItinData<IIC_fpFMAC64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 597243789Sdim InstrStage<1, [SW_ALU1]>], 598243789Sdim [12, 1, 1]>, 599243789Sdim // 600243789Sdim // Single-precision FP DIV 601243789Sdim InstrItinData<IIC_fpDIV32 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 602243789Sdim InstrStage<1, [SW_ALU1], 0>, 603243789Sdim InstrStage<15, [SW_FDIV]>], 604243789Sdim [17, 1, 1]>, 605243789Sdim // 606243789Sdim // Double-precision FP DIV 607243789Sdim InstrItinData<IIC_fpDIV64 , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 608243789Sdim InstrStage<1, [SW_ALU1], 0>, 609243789Sdim InstrStage<30, [SW_FDIV]>], 610243789Sdim [32, 1, 1]>, 611243789Sdim // 612243789Sdim // Single-precision FP SQRT 613243789Sdim InstrItinData<IIC_fpSQRT32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 614243789Sdim InstrStage<1, [SW_ALU1], 0>, 615243789Sdim InstrStage<15, [SW_FDIV]>], 616243789Sdim [17, 1]>, 617243789Sdim // 618243789Sdim // Double-precision FP SQRT 619243789Sdim InstrItinData<IIC_fpSQRT64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 620243789Sdim InstrStage<1, [SW_ALU1], 0>, 621243789Sdim InstrStage<30, [SW_FDIV]>], 622243789Sdim [32, 1, 1]>, 623243789Sdim 624243789Sdim // 625243789Sdim // Integer to Single-precision Move 626243789Sdim InstrItinData<IIC_fpMOVIS, [InstrStage<1, [SW_DIS0], 0>, 627243789Sdim InstrStage<1, [SW_DIS1], 0>, 628243789Sdim InstrStage<1, [SW_LS], 4>, 629243789Sdim InstrStage<1, [SW_ALU0]>], 630243789Sdim [6, 1]>, 631243789Sdim // 632243789Sdim // Integer to Double-precision Move 633243789Sdim InstrItinData<IIC_fpMOVID, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 634243789Sdim InstrStage<1, [SW_LS]>], 635243789Sdim [4, 1]>, 636243789Sdim // 637243789Sdim // Single-precision to Integer Move 638243789Sdim InstrItinData<IIC_fpMOVSI, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 639243789Sdim InstrStage<1, [SW_LS]>], 640243789Sdim [3, 1]>, 641243789Sdim // 642243789Sdim // Double-precision to Integer Move 643243789Sdim InstrItinData<IIC_fpMOVDI, [InstrStage<1, [SW_DIS0], 0>, 644243789Sdim InstrStage<1, [SW_DIS1], 0>, 645243789Sdim InstrStage<1, [SW_LS], 3>, 646243789Sdim InstrStage<1, [SW_LS]>], 647243789Sdim [3, 4, 1]>, 648243789Sdim // 649243789Sdim // Single-precision FP Load 650243789Sdim InstrItinData<IIC_fpLoad32, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 651243789Sdim InstrStage<1, [SW_LS]>], 652243789Sdim [4, 1]>, 653243789Sdim // 654243789Sdim // Double-precision FP Load 655243789Sdim InstrItinData<IIC_fpLoad64, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 656243789Sdim InstrStage<1, [SW_LS]>], 657243789Sdim [4, 1]>, 658243789Sdim // 659243789Sdim // FP Load Multiple 660243789Sdim // FIXME: Assumes a single Q register. 661243789Sdim InstrItinData<IIC_fpLoad_m, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 662243789Sdim InstrStage<1, [SW_LS]>], 663243789Sdim [1, 1, 1, 4], [], -1>, // dynamic uops 664243789Sdim // 665243789Sdim // FP Load Multiple + update 666243789Sdim // FIXME: Assumes a single Q register. 667243789Sdim InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [SW_DIS0], 0>, 668243789Sdim InstrStage<1, [SW_DIS1], 0>, 669243789Sdim InstrStage<1, [SW_LS], 4>, 670243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 671243789Sdim [2, 1, 1, 1, 4], [], -1>, // dynamic uops 672243789Sdim // 673243789Sdim // Single-precision FP Store 674243789Sdim InstrItinData<IIC_fpStore32,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 675243789Sdim InstrStage<1, [SW_LS]>], 676243789Sdim [1, 1]>, 677243789Sdim // 678243789Sdim // Double-precision FP Store 679243789Sdim InstrItinData<IIC_fpStore64,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 680243789Sdim InstrStage<1, [SW_LS]>], 681243789Sdim [1, 1]>, 682243789Sdim // 683243789Sdim // FP Store Multiple 684243789Sdim // FIXME: Assumes a single Q register. 685243789Sdim InstrItinData<IIC_fpStore_m,[InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 686243789Sdim InstrStage<1, [SW_LS]>], 687243789Sdim [1, 1, 1], [], -1>, // dynamic uops 688243789Sdim // 689243789Sdim // FP Store Multiple + update 690243789Sdim // FIXME: Assumes a single Q register. 691243789Sdim InstrItinData<IIC_fpStore_mu,[InstrStage<1, [SW_DIS0], 0>, 692243789Sdim InstrStage<1, [SW_DIS1], 0>, 693243789Sdim InstrStage<1, [SW_LS], 4>, 694243789Sdim InstrStage<1, [SW_ALU0, SW_ALU1]>], 695243789Sdim [2, 1, 1, 1], [], -1>, // dynamic uops 696243789Sdim // NEON 697243789Sdim // 698243789Sdim // Double-register Integer Unary 699243789Sdim InstrItinData<IIC_VUNAiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 700243789Sdim InstrStage<1, [SW_ALU0]>], 701243789Sdim [4, 1]>, 702243789Sdim // 703243789Sdim // Quad-register Integer Unary 704243789Sdim InstrItinData<IIC_VUNAiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 705243789Sdim InstrStage<1, [SW_ALU0]>], 706243789Sdim [4, 1]>, 707243789Sdim // 708243789Sdim // Double-register Integer Q-Unary 709243789Sdim InstrItinData<IIC_VQUNAiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 710243789Sdim InstrStage<1, [SW_ALU0]>], 711243789Sdim [4, 1]>, 712243789Sdim // 713243789Sdim // Quad-register Integer CountQ-Unary 714243789Sdim InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 715243789Sdim InstrStage<1, [SW_ALU0]>], 716243789Sdim [4, 1]>, 717243789Sdim // 718243789Sdim // Double-register Integer Binary 719243789Sdim InstrItinData<IIC_VBINiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 720243789Sdim InstrStage<1, [SW_ALU0]>], 721243789Sdim [2, 1, 1]>, 722243789Sdim // 723243789Sdim // Quad-register Integer Binary 724243789Sdim InstrItinData<IIC_VBINiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 725243789Sdim InstrStage<1, [SW_ALU0]>], 726243789Sdim [2, 1, 1]>, 727243789Sdim // 728243789Sdim // Double-register Integer Subtract 729243789Sdim InstrItinData<IIC_VSUBiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 730243789Sdim InstrStage<1, [SW_ALU0]>], 731243789Sdim [2, 1, 1]>, 732243789Sdim // 733243789Sdim // Quad-register Integer Subtract 734243789Sdim InstrItinData<IIC_VSUBiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 735243789Sdim InstrStage<1, [SW_ALU0]>], 736243789Sdim [2, 1, 1]>, 737243789Sdim // 738243789Sdim // Double-register Integer Shift 739243789Sdim InstrItinData<IIC_VSHLiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 740243789Sdim InstrStage<1, [SW_ALU0]>], 741243789Sdim [2, 1, 1]>, 742243789Sdim // 743243789Sdim // Quad-register Integer Shift 744243789Sdim InstrItinData<IIC_VSHLiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 745243789Sdim InstrStage<1, [SW_ALU0]>], 746243789Sdim [2, 1, 1]>, 747243789Sdim // 748243789Sdim // Double-register Integer Shift (4 cycle) 749243789Sdim InstrItinData<IIC_VSHLi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 750243789Sdim InstrStage<1, [SW_ALU0]>], 751243789Sdim [4, 1, 1]>, 752243789Sdim // 753243789Sdim // Quad-register Integer Shift (4 cycle) 754243789Sdim InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 755243789Sdim InstrStage<1, [SW_ALU0]>], 756243789Sdim [4, 1, 1]>, 757243789Sdim // 758243789Sdim // Double-register Integer Binary (4 cycle) 759243789Sdim InstrItinData<IIC_VBINi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 760243789Sdim InstrStage<1, [SW_ALU0]>], 761243789Sdim [4, 1, 1]>, 762243789Sdim // 763243789Sdim // Quad-register Integer Binary (4 cycle) 764243789Sdim InstrItinData<IIC_VBINi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 765243789Sdim InstrStage<1, [SW_ALU0]>], 766243789Sdim [4, 1, 1]>, 767243789Sdim // 768243789Sdim // Double-register Integer Subtract (4 cycle) 769243789Sdim InstrItinData<IIC_VSUBi4D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 770243789Sdim InstrStage<1, [SW_ALU0]>], 771243789Sdim [4, 1, 1]>, 772243789Sdim // 773243789Sdim // Quad-register Integer Subtract (4 cycle) 774243789Sdim InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 775243789Sdim InstrStage<1, [SW_ALU0]>], 776243789Sdim [4, 1, 1]>, 777243789Sdim 778243789Sdim // 779243789Sdim // Double-register Integer Count 780243789Sdim InstrItinData<IIC_VCNTiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 781243789Sdim InstrStage<1, [SW_ALU0]>], 782243789Sdim [2, 1, 1]>, 783243789Sdim // 784243789Sdim // Quad-register Integer Count 785243789Sdim InstrItinData<IIC_VCNTiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 786243789Sdim InstrStage<1, [SW_ALU0]>], 787243789Sdim [2, 1, 1]>, 788243789Sdim // 789243789Sdim // Double-register Absolute Difference and Accumulate 790243789Sdim InstrItinData<IIC_VABAD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 791243789Sdim InstrStage<1, [SW_ALU0]>], 792243789Sdim [4, 1, 1, 1]>, 793243789Sdim // 794243789Sdim // Quad-register Absolute Difference and Accumulate 795243789Sdim InstrItinData<IIC_VABAQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 796243789Sdim InstrStage<1, [SW_ALU0]>], 797243789Sdim [4, 1, 1, 1]>, 798243789Sdim // 799243789Sdim // Double-register Integer Pair Add Long 800243789Sdim InstrItinData<IIC_VPALiD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 801243789Sdim InstrStage<1, [SW_ALU0]>], 802243789Sdim [4, 1, 1]>, 803243789Sdim // 804243789Sdim // Quad-register Integer Pair Add Long 805243789Sdim InstrItinData<IIC_VPALiQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 806243789Sdim InstrStage<1, [SW_ALU0]>], 807243789Sdim [4, 1, 1]>, 808243789Sdim 809243789Sdim // 810243789Sdim // Double-register Integer Multiply (.8, .16) 811243789Sdim InstrItinData<IIC_VMULi16D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 812243789Sdim InstrStage<1, [SW_ALU1]>], 813243789Sdim [4, 1, 1]>, 814243789Sdim // 815243789Sdim // Quad-register Integer Multiply (.8, .16) 816243789Sdim InstrItinData<IIC_VMULi16Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 817243789Sdim InstrStage<1, [SW_ALU1]>], 818243789Sdim [4, 1, 1]>, 819243789Sdim 820243789Sdim // 821243789Sdim // Double-register Integer Multiply (.32) 822243789Sdim InstrItinData<IIC_VMULi32D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 823243789Sdim InstrStage<1, [SW_ALU1]>], 824243789Sdim [4, 1, 1]>, 825243789Sdim // 826243789Sdim // Quad-register Integer Multiply (.32) 827243789Sdim InstrItinData<IIC_VMULi32Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 828243789Sdim InstrStage<1, [SW_ALU1]>], 829243789Sdim [4, 1, 1]>, 830243789Sdim // 831243789Sdim // Double-register Integer Multiply-Accumulate (.8, .16) 832243789Sdim InstrItinData<IIC_VMACi16D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 833243789Sdim InstrStage<1, [SW_ALU1]>], 834243789Sdim [4, 1, 1, 1]>, 835243789Sdim // 836243789Sdim // Double-register Integer Multiply-Accumulate (.32) 837243789Sdim InstrItinData<IIC_VMACi32D, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 838243789Sdim InstrStage<1, [SW_ALU1]>], 839243789Sdim [4, 1, 1, 1]>, 840243789Sdim // 841243789Sdim // Quad-register Integer Multiply-Accumulate (.8, .16) 842243789Sdim InstrItinData<IIC_VMACi16Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 843243789Sdim InstrStage<1, [SW_ALU1]>], 844243789Sdim [4, 1, 1, 1]>, 845243789Sdim // 846243789Sdim // Quad-register Integer Multiply-Accumulate (.32) 847243789Sdim InstrItinData<IIC_VMACi32Q, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 848243789Sdim InstrStage<1, [SW_ALU1]>], 849243789Sdim [4, 1, 1, 1]>, 850243789Sdim 851243789Sdim // 852243789Sdim // Move 853243789Sdim InstrItinData<IIC_VMOV, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 854243789Sdim InstrStage<1, [SW_ALU0]>], 855243789Sdim [2, 1]>, 856243789Sdim // 857243789Sdim // Move Immediate 858243789Sdim InstrItinData<IIC_VMOVImm, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 859243789Sdim InstrStage<1, [SW_ALU0]>], 860243789Sdim [2]>, 861243789Sdim // 862243789Sdim // Double-register Permute Move 863243789Sdim InstrItinData<IIC_VMOVD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 864243789Sdim InstrStage<1, [SW_ALU1]>], 865243789Sdim [2, 1]>, 866243789Sdim // 867243789Sdim // Quad-register Permute Move 868243789Sdim InstrItinData<IIC_VMOVQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 869243789Sdim InstrStage<1, [SW_ALU1]>], 870243789Sdim [2, 1]>, 871243789Sdim // 872243789Sdim // Integer to Single-precision Move 873243789Sdim InstrItinData<IIC_VMOVIS , [InstrStage<1, [SW_DIS0], 0>, 874243789Sdim InstrStage<1, [SW_DIS1], 0>, 875243789Sdim InstrStage<1, [SW_LS], 4>, 876243789Sdim InstrStage<1, [SW_ALU0]>], 877243789Sdim [6, 1]>, 878243789Sdim // 879243789Sdim // Integer to Double-precision Move 880243789Sdim InstrItinData<IIC_VMOVID , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 881243789Sdim InstrStage<1, [SW_LS]>], 882243789Sdim [4, 1, 1]>, 883243789Sdim // 884243789Sdim // Single-precision to Integer Move 885243789Sdim InstrItinData<IIC_VMOVSI , [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 886243789Sdim InstrStage<1, [SW_LS]>], 887243789Sdim [3, 1]>, 888243789Sdim // 889243789Sdim // Double-precision to Integer Move 890243789Sdim InstrItinData<IIC_VMOVDI , [InstrStage<1, [SW_DIS0], 0>, 891243789Sdim InstrStage<1, [SW_DIS1], 0>, 892243789Sdim InstrStage<1, [SW_LS], 3>, 893243789Sdim InstrStage<1, [SW_LS]>], 894243789Sdim [3, 4, 1]>, 895243789Sdim // 896243789Sdim // Integer to Lane Move 897243789Sdim // FIXME: I think this is correct, but it is not clear from the tuning guide. 898243789Sdim InstrItinData<IIC_VMOVISL , [InstrStage<1, [SW_DIS0], 0>, 899243789Sdim InstrStage<1, [SW_DIS1], 0>, 900243789Sdim InstrStage<1, [SW_LS], 4>, 901243789Sdim InstrStage<1, [SW_ALU0]>], 902243789Sdim [6, 1]>, 903243789Sdim 904243789Sdim // 905243789Sdim // Vector narrow move 906243789Sdim InstrItinData<IIC_VMOVN, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 907243789Sdim InstrStage<1, [SW_ALU1]>], 908243789Sdim [2, 1]>, 909243789Sdim // 910243789Sdim // Double-register FP Unary 911243789Sdim // FIXME: VRECPE / VRSQRTE has a longer latency than VABS, which is used here, 912243789Sdim // and they issue on a different pipeline. 913243789Sdim InstrItinData<IIC_VUNAD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 914243789Sdim InstrStage<1, [SW_ALU0]>], 915243789Sdim [2, 1]>, 916243789Sdim // 917243789Sdim // Quad-register FP Unary 918243789Sdim // FIXME: VRECPE / VRSQRTE has a longer latency than VABS, which is used here, 919243789Sdim // and they issue on a different pipeline. 920243789Sdim InstrItinData<IIC_VUNAQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 921243789Sdim InstrStage<1, [SW_ALU0]>], 922243789Sdim [2, 1]>, 923243789Sdim // 924243789Sdim // Double-register FP Binary 925243789Sdim // FIXME: We're using this itin for many instructions. 926243789Sdim InstrItinData<IIC_VBIND, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 927243789Sdim InstrStage<1, [SW_ALU0]>], 928243789Sdim [4, 1, 1]>, 929243789Sdim 930243789Sdim // 931243789Sdim // VPADD, etc. 932243789Sdim InstrItinData<IIC_VPBIND, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 933243789Sdim InstrStage<1, [SW_ALU0]>], 934243789Sdim [4, 1, 1]>, 935243789Sdim // 936243789Sdim // Double-register FP VMUL 937243789Sdim InstrItinData<IIC_VFMULD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 938243789Sdim InstrStage<1, [SW_ALU1]>], 939243789Sdim [4, 1, 1]>, 940243789Sdim // 941243789Sdim // Quad-register FP Binary 942243789Sdim InstrItinData<IIC_VBINQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 943243789Sdim InstrStage<1, [SW_ALU0]>], 944243789Sdim [4, 1, 1]>, 945243789Sdim // 946243789Sdim // Quad-register FP VMUL 947243789Sdim InstrItinData<IIC_VFMULQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 948243789Sdim InstrStage<1, [SW_ALU1]>], 949243789Sdim [4, 1, 1]>, 950243789Sdim // 951243789Sdim // Double-register FP Multiple-Accumulate 952243789Sdim InstrItinData<IIC_VMACD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 953243789Sdim InstrStage<1, [SW_ALU1]>], 954243789Sdim [8, 1, 1]>, 955243789Sdim // 956243789Sdim // Quad-register FP Multiple-Accumulate 957243789Sdim InstrItinData<IIC_VMACQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 958243789Sdim InstrStage<1, [SW_ALU1]>], 959243789Sdim [8, 1, 1]>, 960243789Sdim // 961243789Sdim // Double-register Fused FP Multiple-Accumulate 962243789Sdim InstrItinData<IIC_VFMACD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 963243789Sdim InstrStage<1, [SW_ALU1]>], 964243789Sdim [8, 1, 1]>, 965243789Sdim // 966243789Sdim // Quad-register FusedF P Multiple-Accumulate 967243789Sdim InstrItinData<IIC_VFMACQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 968243789Sdim InstrStage<1, [SW_ALU1]>], 969243789Sdim [8, 1, 1]>, 970243789Sdim // 971243789Sdim // Double-register Reciprical Step 972243789Sdim InstrItinData<IIC_VRECSD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 973243789Sdim InstrStage<1, [SW_ALU1]>], 974243789Sdim [8, 1, 1]>, 975243789Sdim // 976243789Sdim // Quad-register Reciprical Step 977243789Sdim InstrItinData<IIC_VRECSQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 978243789Sdim InstrStage<1, [SW_ALU1]>], 979243789Sdim [8, 1, 1]>, 980243789Sdim // 981243789Sdim // Double-register Permute 982243789Sdim // FIXME: The latencies are unclear from the documentation. 983243789Sdim InstrItinData<IIC_VPERMD, [InstrStage<1, [SW_DIS0], 0>, 984243789Sdim InstrStage<1, [SW_DIS1], 0>, 985243789Sdim InstrStage<1, [SW_DIS2], 0>, 986243789Sdim InstrStage<1, [SW_ALU1], 2>, 987243789Sdim InstrStage<1, [SW_ALU1], 2>, 988243789Sdim InstrStage<1, [SW_ALU1]>], 989243789Sdim [3, 4, 3, 4]>, 990243789Sdim // 991243789Sdim // Quad-register Permute 992243789Sdim // FIXME: The latencies are unclear from the documentation. 993243789Sdim InstrItinData<IIC_VPERMQ, [InstrStage<1, [SW_DIS0], 0>, 994243789Sdim InstrStage<1, [SW_DIS1], 0>, 995243789Sdim InstrStage<1, [SW_DIS2], 0>, 996243789Sdim InstrStage<1, [SW_ALU1], 2>, 997243789Sdim InstrStage<1, [SW_ALU1], 2>, 998243789Sdim InstrStage<1, [SW_ALU1]>], 999243789Sdim [3, 4, 3, 4]>, 1000243789Sdim // 1001243789Sdim // Quad-register Permute (3 cycle issue on A9) 1002243789Sdim InstrItinData<IIC_VPERMQ3, [InstrStage<1, [SW_DIS0], 0>, 1003243789Sdim InstrStage<1, [SW_DIS1], 0>, 1004243789Sdim InstrStage<1, [SW_DIS2], 0>, 1005243789Sdim InstrStage<1, [SW_ALU1], 2>, 1006243789Sdim InstrStage<1, [SW_ALU1], 2>, 1007243789Sdim InstrStage<1, [SW_ALU1]>], 1008243789Sdim [3, 4, 3, 4]>, 1009243789Sdim 1010243789Sdim // 1011243789Sdim // Double-register VEXT 1012243789Sdim InstrItinData<IIC_VEXTD, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 1013243789Sdim InstrStage<1, [SW_ALU1]>], 1014243789Sdim [2, 1, 1]>, 1015243789Sdim // 1016243789Sdim // Quad-register VEXT 1017243789Sdim InstrItinData<IIC_VEXTQ, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 1018243789Sdim InstrStage<1, [SW_ALU1]>], 1019243789Sdim [2, 1, 1]>, 1020243789Sdim // 1021243789Sdim // VTB 1022243789Sdim InstrItinData<IIC_VTB1, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 1023243789Sdim InstrStage<1, [SW_ALU1]>], 1024243789Sdim [2, 1, 1]>, 1025243789Sdim InstrItinData<IIC_VTB2, [InstrStage<1, [SW_DIS0], 0>, 1026243789Sdim InstrStage<1, [SW_DIS1], 0>, 1027243789Sdim InstrStage<1, [SW_ALU1], 2>, 1028243789Sdim InstrStage<1, [SW_ALU1]>], 1029243789Sdim [4, 1, 3, 3]>, 1030243789Sdim InstrItinData<IIC_VTB3, [InstrStage<1, [SW_DIS0], 0>, 1031243789Sdim InstrStage<1, [SW_DIS1], 0>, 1032243789Sdim InstrStage<1, [SW_DIS2], 0>, 1033243789Sdim InstrStage<1, [SW_ALU1], 2>, 1034243789Sdim InstrStage<1, [SW_ALU1], 2>, 1035243789Sdim InstrStage<1, [SW_ALU1]>], 1036243789Sdim [6, 1, 3, 5, 5]>, 1037243789Sdim InstrItinData<IIC_VTB4, [InstrStage<1, [SW_DIS0], 0>, 1038243789Sdim InstrStage<1, [SW_DIS1], 0>, 1039243789Sdim InstrStage<1, [SW_DIS2], 0>, 1040243789Sdim InstrStage<1, [SW_ALU1], 2>, 1041243789Sdim InstrStage<1, [SW_ALU1], 2>, 1042243789Sdim InstrStage<1, [SW_ALU1], 2>, 1043243789Sdim InstrStage<1, [SW_ALU1]>], 1044243789Sdim [8, 1, 3, 5, 7, 7]>, 1045243789Sdim // 1046243789Sdim // VTBX 1047243789Sdim InstrItinData<IIC_VTBX1, [InstrStage<1, [SW_DIS0, SW_DIS1, SW_DIS2], 0>, 1048243789Sdim InstrStage<1, [SW_ALU1]>], 1049243789Sdim [2, 1, 1]>, 1050243789Sdim InstrItinData<IIC_VTBX2, [InstrStage<1, [SW_DIS0], 0>, 1051243789Sdim InstrStage<1, [SW_DIS1], 0>, 1052243789Sdim InstrStage<1, [SW_ALU1], 2>, 1053243789Sdim InstrStage<1, [SW_ALU1]>], 1054243789Sdim [4, 1, 3, 3]>, 1055243789Sdim InstrItinData<IIC_VTBX3, [InstrStage<1, [SW_DIS0], 0>, 1056243789Sdim InstrStage<1, [SW_DIS1], 0>, 1057243789Sdim InstrStage<1, [SW_DIS2], 0>, 1058243789Sdim InstrStage<1, [SW_ALU1], 2>, 1059243789Sdim InstrStage<1, [SW_ALU1], 2>, 1060243789Sdim InstrStage<1, [SW_ALU1]>], 1061243789Sdim [6, 1, 3, 5, 5]>, 1062243789Sdim InstrItinData<IIC_VTBX4, [InstrStage<1, [SW_DIS0], 0>, 1063243789Sdim InstrStage<1, [SW_DIS1], 0>, 1064243789Sdim InstrStage<1, [SW_DIS2], 0>, 1065243789Sdim InstrStage<1, [SW_ALU1], 2>, 1066243789Sdim InstrStage<1, [SW_ALU1], 2>, 1067243789Sdim InstrStage<1, [SW_ALU1], 2>, 1068243789Sdim InstrStage<1, [SW_ALU1]>], 1069243789Sdim [8, 1, 3, 5, 7, 7]> 1070243789Sdim]>; 1071243789Sdim 1072243789Sdim// ===---------------------------------------------------------------------===// 1073243789Sdim// This following definitions describe the simple machine model which 1074243789Sdim// will replace itineraries. 1075243789Sdim 1076243789Sdim// Swift machine model for scheduling and other instruction cost heuristics. 1077243789Sdimdef SwiftModel : SchedMachineModel { 1078243789Sdim let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. 1079263508Sdim let MicroOpBufferSize = 45; // Based on NEON renamed registers. 1080243789Sdim let LoadLatency = 3; 1081249423Sdim let MispredictPenalty = 14; // A branch direction mispredict. 1082243789Sdim 1083243789Sdim let Itineraries = SwiftItineraries; 1084243789Sdim} 1085243789Sdim 1086249423Sdim// Swift predicates. 1087249423Sdimdef IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>; 1088249423Sdim 1089249423Sdim// Swift resource mapping. 1090249423Sdimlet SchedModel = SwiftModel in { 1091249423Sdim // Processor resources. 1092249423Sdim def SwiftUnitP01 : ProcResource<2>; // ALU unit. 1093249423Sdim def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit. 1094249423Sdim def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit. 1095249423Sdim def SwiftUnitP2 : ProcResource<1>; // LS unit. 1096249423Sdim def SwiftUnitDiv : ProcResource<1>; 1097249423Sdim 1098249423Sdim // Generic resource requirements. 1099263508Sdim def SwiftWriteP0OneCycle : SchedWriteRes<[SwiftUnitP0]>; 1100263508Sdim def SwiftWriteP0TwoCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 2; } 1101263508Sdim def SwiftWriteP0FourCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 4; } 1102263508Sdim def SwiftWriteP0SixCycle : SchedWriteRes<[SwiftUnitP0]> { let Latency = 6; } 1103263508Sdim def SwiftWriteP0P1FourCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { 1104263508Sdim let Latency = 4; 1105263508Sdim } 1106263508Sdim def SwiftWriteP0P1SixCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP1]> { 1107263508Sdim let Latency = 6; 1108263508Sdim } 1109263508Sdim def SwiftWriteP01OneCycle : SchedWriteRes<[SwiftUnitP01]>; 1110263508Sdim def SwiftWriteP1TwoCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 2; } 1111263508Sdim def SwiftWriteP1FourCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 4; } 1112263508Sdim def SwiftWriteP1SixCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 6; } 1113263508Sdim def SwiftWriteP1EightCycle : SchedWriteRes<[SwiftUnitP1]> { let Latency = 8; } 1114263508Sdim def SwiftWriteP1TwelveCyc : SchedWriteRes<[SwiftUnitP1]> { let Latency = 12; } 1115263508Sdim def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>; 1116263508Sdim def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>; 1117249423Sdim def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; } 1118263508Sdim def SwiftWriteP01ThreeCycleTwoUops : SchedWriteRes<[SwiftUnitP01, 1119263508Sdim SwiftUnitP01]> { 1120249423Sdim let Latency = 3; 1121249423Sdim let NumMicroOps = 2; 1122249423Sdim } 1123249423Sdim def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> { 1124249423Sdim let Latency = 3; 1125249423Sdim let NumMicroOps = 3; 1126249423Sdim let ResourceCycles = [3]; 1127249423Sdim } 1128263508Sdim // Plain load without writeback. 1129263508Sdim def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> { 1130263508Sdim let Latency = 3; 1131263508Sdim } 1132263508Sdim def SwiftWriteP2FourCycle : SchedWriteRes<[SwiftUnitP2]> { 1133263508Sdim let Latency = 4; 1134263508Sdim } 1135263508Sdim // A store does not write to a register. 1136263508Sdim def SwiftWriteP2 : SchedWriteRes<[SwiftUnitP2]> { 1137263508Sdim let Latency = 0; 1138263508Sdim } 1139263508Sdim foreach Num = 1-4 in { 1140263508Sdim def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>; 1141263508Sdim } 1142263508Sdim def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle, 1143263508Sdim SwiftWriteP01OneCycle, 1144263508Sdim SwiftWriteP2ThreeCycle]>; 1145249423Sdim // 4.2.4 Arithmetic and Logical. 1146249423Sdim // ALU operation register shifted by immediate variant. 1147249423Sdim def SwiftWriteALUsi : SchedWriteVariant<[ 1148249423Sdim // lsl #2, lsl #1, or lsr #1. 1149249423Sdim SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>, 1150249423Sdim SchedVar<NoSchedPred, [WriteALU]> 1151249423Sdim ]>; 1152249423Sdim def SwiftWriteALUsr : SchedWriteVariant<[ 1153249423Sdim SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>, 1154249423Sdim SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 1155249423Sdim ]>; 1156249423Sdim def SwiftWriteALUSsr : SchedWriteVariant<[ 1157249423Sdim SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>, 1158249423Sdim SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 1159249423Sdim ]>; 1160249423Sdim def SwiftReadAdvanceALUsr : SchedReadVariant<[ 1161249423Sdim SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>, 1162249423Sdim SchedVar<NoSchedPred, [NoReadAdvance]> 1163249423Sdim ]>; 1164249423Sdim // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR 1165249423Sdim // AND,BIC,EOR,ORN,ORR 1166249423Sdim // CLZ,RBIT,REV,REV16,REVSH,PKH 1167249423Sdim def : WriteRes<WriteALU, [SwiftUnitP01]>; 1168249423Sdim def : SchedAlias<WriteALUsi, SwiftWriteALUsi>; 1169249423Sdim def : SchedAlias<WriteALUsr, SwiftWriteALUsr>; 1170249423Sdim def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>; 1171249423Sdim def : ReadAdvance<ReadALU, 0>; 1172249423Sdim def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>; 1173249423Sdim 1174263508Sdim 1175263508Sdim def SwiftChooseShiftKindP01OneOrTwoCycle : SchedWriteVariant<[ 1176263508Sdim SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01OneCycle]>, 1177263508Sdim SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> 1178263508Sdim ]>; 1179263508Sdim 1180249423Sdim // 4.2.5 Integer comparison 1181249423Sdim def : WriteRes<WriteCMP, [SwiftUnitP01]>; 1182263508Sdim def : SchedAlias<WriteCMPsi, SwiftChooseShiftKindP01OneOrTwoCycle>; 1183263508Sdim def : SchedAlias<WriteCMPsr, SwiftWriteP01TwoCycle>; 1184263508Sdim 1185263508Sdim // 4.2.6 Shift, Move 1186263508Sdim // Shift 1187263508Sdim // ASR,LSL,ROR,RRX 1188263508Sdim // MOV(register-shiftedregister) MVN(register-shiftedregister) 1189263508Sdim // Move 1190263508Sdim // MOV,MVN 1191263508Sdim // MOVT 1192263508Sdim // Sign/Zero extension 1193263508Sdim def : InstRW<[SwiftWriteP01OneCycle], 1194263508Sdim (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16", 1195263508Sdim "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", 1196263508Sdim "t2UXTB16")>; 1197263508Sdim // Pseudo instructions. 1198263508Sdim def : InstRW<[SwiftWriteP01OneCycle2x], 1199263508Sdim (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi32imm", 1200263508Sdim "t2MOVi32imm", "t2MOV_ga_dyn")>; 1201263508Sdim def : InstRW<[SwiftWriteP01OneCycle3x], 1202263508Sdim (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>; 1203263508Sdim def : InstRW<[SwiftWriteP01OneCycle2x_load], 1204263508Sdim (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>; 1205263508Sdim 1206263508Sdim def SwiftWriteP0TwoCyleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>; 1207263508Sdim 1208263508Sdim def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[ 1209263508Sdim SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCyleTwoUops ]>, 1210263508Sdim SchedVar<NoSchedPred, [ SwiftWriteP0OneCycle ]> 1211263508Sdim ]>; 1212263508Sdim 1213263508Sdim // 4.2.7 Select 1214263508Sdim // SEL 1215263508Sdim def : InstRW<[SwiftPredP0OneOrTwoCycle], (instregex "SEL", "t2SEL")>; 1216263508Sdim 1217263508Sdim // 4.2.8 Bitfield 1218263508Sdim // BFI,BFC, SBFX,UBFX 1219263508Sdim def : InstRW< [SwiftWriteP01TwoCycle], 1220263508Sdim (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI", 1221263508Sdim "(t|t2)UBFX", "(t|t2)SBFX")>; 1222263508Sdim 1223263508Sdim // 4.2.9 Saturating arithmetic 1224263508Sdim def : InstRW< [SwiftWriteP01TwoCycle], 1225263508Sdim (instregex "QADD", "QSUB", "QDADD", "QDSUB", "SSAT", "SSAT16", "USAT", 1226263508Sdim "USAT16", "QADD8", "QADD16", "QSUB8", "QSUB16", "QASX", "QSAX", 1227263508Sdim "UQADD8", "UQADD16","UQSUB8","UQSUB16","UQASX","UQSAX", "t2QADD", 1228263508Sdim "t2QSUB", "t2QDADD", "t2QDSUB", "t2SSAT", "t2SSAT16", "t2USAT", 1229263508Sdim "t2QADD8", "t2QADD16", "t2QSUB8", "t2QSUB16", "t2QASX", "t2QSAX", 1230263508Sdim "t2UQADD8", "t2UQADD16","t2UQSUB8","t2UQSUB16","t2UQASX","t2UQSAX")>; 1231263508Sdim 1232263508Sdim // 4.2.10 Parallel Arithmetic 1233263508Sdim // Not flag setting. 1234263508Sdim def : InstRW< [SwiftWriteALUsr], 1235263508Sdim (instregex "SADD8", "SADD16", "SSUB8", "SSUB16", "SASX", "SSAX", 1236263508Sdim "UADD8", "UADD16", "USUB8", "USUB16", "UASX", "USAX", "t2SADD8", 1237263508Sdim "t2SADD16", "t2SSUB8", "t2SSUB16", "t2SASX", "t2SSAX", "t2UADD8", 1238263508Sdim "t2UADD16", "t2USUB8", "t2USUB16", "t2UASX", "t2USAX")>; 1239263508Sdim // Flag setting. 1240263508Sdim def : InstRW< [SwiftWriteP01TwoCycle], 1241263508Sdim (instregex "SHADD8", "SHADD16", "SHSUB8", "SHSUB16", "SHASX", "SHSAX", 1242263508Sdim "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16", 1243263508Sdim "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16", 1244263508Sdim "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16", 1245263508Sdim "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX", 1246263508Sdim "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>; 1247263508Sdim 1248263508Sdim // 4.2.11 Sum of Absolute Difference 1249263508Sdim def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >; 1250263508Sdim def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>], 1251263508Sdim (instregex "USADA8")>; 1252263508Sdim 1253263508Sdim // 4.2.12 Integer Multiply (32-bit result) 1254263508Sdim // Two sources. 1255263508Sdim def : InstRW< [SwiftWriteP0FourCycle], 1256263508Sdim (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT", 1257263508Sdim "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL", 1258263508Sdim "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT", 1259263508Sdim "t2SMULWB", "t2SMULWT", "t2SMUSD")>; 1260263508Sdim 1261263508Sdim def SwiftWriteP0P01FiveCycleTwoUops : 1262263508Sdim SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 1263263508Sdim let Latency = 5; 1264263508Sdim } 1265263508Sdim 1266263508Sdim def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[ 1267263508Sdim SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>, 1268263508Sdim SchedVar<NoSchedPred, [ SwiftWriteP0FourCycle ]> 1269263508Sdim ]>; 1270263508Sdim 1271263508Sdim def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[ 1272263508Sdim SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>, 1273263508Sdim SchedVar<NoSchedPred, [ReadALU]> 1274263508Sdim ]>; 1275263508Sdim 1276263508Sdim // Multiply accumulate, three sources 1277263508Sdim def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, 1278263508Sdim SwiftReadAdvanceFourCyclesPred], 1279263508Sdim (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR", 1280263508Sdim "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", 1281263508Sdim "t2SMMLSR")>; 1282263508Sdim 1283263508Sdim // 4.2.13 Integer Multiply (32-bit result, Q flag) 1284263508Sdim def : InstRW< [SwiftWriteP0FourCycle], 1285263508Sdim (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>; 1286263508Sdim def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU, 1287263508Sdim SwiftReadAdvanceFourCyclesPred], 1288263508Sdim (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX", 1289263508Sdim "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT", 1290263508Sdim "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT")>; 1291263508Sdim def : InstRW< [SwiftPredP0P01FourFiveCycle], 1292263508Sdim (instregex "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX")>; 1293263508Sdim 1294263508Sdim def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 1295263508Sdim let Latency = 5; 1296263508Sdim let NumMicroOps = 3; 1297263508Sdim let ResourceCycles = [2, 1]; 1298263508Sdim } 1299263508Sdim def SwiftWrite1Cycle : SchedWriteRes<[]> { 1300263508Sdim let Latency = 1; 1301263508Sdim let NumMicroOps = 0; 1302263508Sdim } 1303263508Sdim def SwiftWrite5Cycle : SchedWriteRes<[]> { 1304263508Sdim let Latency = 5; 1305263508Sdim let NumMicroOps = 0; 1306263508Sdim } 1307263508Sdim def SwiftWrite6Cycle : SchedWriteRes<[]> { 1308263508Sdim let Latency = 6; 1309263508Sdim let NumMicroOps = 0; 1310263508Sdim } 1311263508Sdim 1312263508Sdim // 4.2.14 Integer Multiply, Long 1313263508Sdim def : InstRW< [SwiftP0P0P01FiveCycle, SwiftWrite5Cycle], 1314263508Sdim (instregex "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$")>; 1315263508Sdim 1316263508Sdim def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> { 1317263508Sdim let Latency = 7; 1318263508Sdim let NumMicroOps = 5; 1319263508Sdim let ResourceCycles = [2, 3]; 1320263508Sdim } 1321263508Sdim 1322263508Sdim // 4.2.15 Integer Multiply Accumulate, Long 1323263508Sdim // 4.2.16 Integer Multiply Accumulate, Dual 1324263508Sdim // 4.2.17 Integer Multiply Accumulate Accumulate, Long 1325263508Sdim // We are being a bit inaccurate here. 1326263508Sdim def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU, 1327263508Sdim SchedReadAdvance<4>, SchedReadAdvance<3>], 1328263508Sdim (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT", 1329263508Sdim "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX", 1330263508Sdim "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT", 1331263508Sdim "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX", 1332263508Sdim "t2UMAAL")>; 1333263508Sdim 1334263508Sdim def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 1335263508Sdim let NumMicroOps = 1; 1336263508Sdim let Latency = 14; 1337263508Sdim let ResourceCycles = [1, 14]; 1338263508Sdim } 1339263508Sdim // 4.2.18 Integer Divide 1340263508Sdim def : WriteRes<WriteDiv, [SwiftUnitDiv]>; // Workaround. 1341263508Sdim def : InstRW <[SwiftDiv], 1342263508Sdim (instregex "SDIV", "UDIV", "t2SDIV", "t2UDIV")>; 1343263508Sdim 1344263508Sdim // 4.2.19 Integer Load Single Element 1345263508Sdim // 4.2.20 Integer Load Signextended 1346263508Sdim def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 1347263508Sdim let Latency = 3; 1348263508Sdim let NumMicroOps = 2; 1349263508Sdim } 1350263508Sdim def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 1351263508Sdim let Latency = 4; 1352263508Sdim let NumMicroOps = 2; 1353263508Sdim } 1354263508Sdim def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01, 1355263508Sdim SwiftUnitP01]> { 1356263508Sdim let Latency = 4; 1357263508Sdim let NumMicroOps = 3; 1358263508Sdim } 1359263508Sdim def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> { 1360263508Sdim let Latency = 3; 1361263508Sdim let NumMicroOps = 2; 1362263508Sdim } 1363263508Sdim def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2, 1364263508Sdim SwiftUnitP01]> { 1365263508Sdim let Latency = 3; 1366263508Sdim let NumMicroOps = 3; 1367263508Sdim } 1368263508Sdim def SwiftWrBackOne : SchedWriteRes<[]> { 1369263508Sdim let Latency = 1; 1370263508Sdim let NumMicroOps = 0; 1371263508Sdim } 1372263508Sdim def SwiftWriteLdFour : SchedWriteRes<[]> { 1373263508Sdim let Latency = 4; 1374263508Sdim let NumMicroOps = 0; 1375263508Sdim } 1376263508Sdim // Not accurate. 1377263508Sdim def : InstRW<[SwiftWriteP2ThreeCycle], 1378263508Sdim (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)", 1379263508Sdim "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)", 1380263508Sdim "tLDR(r|i|spi|pci|pciASM)")>; 1381263508Sdim def : InstRW<[SwiftWriteP2ThreeCycle], 1382263508Sdim (instregex "LDRH$", "PICLDR$", "PICLDR(H|B)$", "LDRcp$")>; 1383263508Sdim def : InstRW<[SwiftWriteP2P01FourCyle], 1384263508Sdim (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$", 1385263508Sdim "t2LDRpci_pic", "tLDRS(B|H)")>; 1386263508Sdim def : InstRW<[SwiftWriteP2P01ThreeCycle, SwiftWrBackOne], 1387263508Sdim (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)", 1388263508Sdim "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)", 1389263508Sdim "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>; 1390263508Sdim def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne], 1391263508Sdim (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)", 1392263508Sdim "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>; 1393263508Sdim 1394263508Sdim // 4.2.21 Integer Dual Load 1395263508Sdim // Not accurate. 1396263508Sdim def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour], 1397263508Sdim (instregex "t2LDRDi8", "LDRD$")>; 1398263508Sdim def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne], 1399263508Sdim (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>; 1400263508Sdim 1401263508Sdim // 4.2.22 Integer Load, Multiple 1402263508Sdim // NumReg = 1 .. 16 1403263508Sdim foreach Lat = 3-25 in { 1404263508Sdim def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> { 1405263508Sdim let Latency = Lat; 1406263508Sdim } 1407263508Sdim def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { 1408263508Sdim let Latency = Lat; 1409263508Sdim let NumMicroOps = 0; 1410263508Sdim } 1411263508Sdim } 1412263508Sdim // Predicate. 1413263508Sdim foreach NumAddr = 1-16 in { 1414263508Sdim def SwiftLMAddr#NumAddr#Pred : SchedPredicate<"TII->getNumLDMAddresses(MI) == "#NumAddr>; 1415263508Sdim } 1416263508Sdim def SwiftWriteLDMAddrNoWB : SchedWriteRes<[SwiftUnitP01]> { let Latency = 0; } 1417263508Sdim def SwiftWriteLDMAddrWB : SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]>; 1418263508Sdim def SwiftWriteLM : SchedWriteVariant<[ 1419263508Sdim SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy]>, 1420263508Sdim SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1421263508Sdim SwiftWriteLM5Cy]>, 1422263508Sdim SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1423263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy]>, 1424263508Sdim SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1425263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1426263508Sdim SwiftWriteLM7Cy]>, 1427263508Sdim SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1428263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1429263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy]>, 1430263508Sdim SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1431263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1432263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1433263508Sdim SwiftWriteLM9Cy]>, 1434263508Sdim SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1435263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1436263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1437263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy]>, 1438263508Sdim SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1439263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1440263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1441263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1442263508Sdim SwiftWriteLM11Cy]>, 1443263508Sdim SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1444263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1445263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1446263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1447263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy]>, 1448263508Sdim SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1449263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1450263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1451263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1452263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1453263508Sdim SwiftWriteLM13Cy]>, 1454263508Sdim SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1455263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1456263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1457263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1458263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1459263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy]>, 1460263508Sdim SchedVar<SwiftLMAddr13Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1461263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1462263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1463263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1464263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1465263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy, 1466263508Sdim SwiftWriteLM15Cy]>, 1467263508Sdim SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1468263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1469263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1470263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1471263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1472263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy, 1473263508Sdim SwiftWriteLM15Cy, SwiftWriteLM16Cy]>, 1474263508Sdim SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1475263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1476263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1477263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1478263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1479263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy, 1480263508Sdim SwiftWriteLM15Cy, SwiftWriteLM16Cy, 1481263508Sdim SwiftWriteLM17Cy]>, 1482263508Sdim SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1483263508Sdim SwiftWriteLM5Cy, SwiftWriteLM6Cy, 1484263508Sdim SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1485263508Sdim SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1486263508Sdim SwiftWriteLM11Cy, SwiftWriteLM12Cy, 1487263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy, 1488263508Sdim SwiftWriteLM15Cy, SwiftWriteLM16Cy, 1489263508Sdim SwiftWriteLM17Cy, SwiftWriteLM18Cy]>, 1490263508Sdim // Unknow number of registers, just use resources for two registers. 1491263508Sdim SchedVar<NoSchedPred, [SwiftWriteLM3Cy, SwiftWriteLM4Cy, 1492263508Sdim SwiftWriteLM5CyNo, SwiftWriteLM6CyNo, 1493263508Sdim SwiftWriteLM7CyNo, SwiftWriteLM8CyNo, 1494263508Sdim SwiftWriteLM9CyNo, SwiftWriteLM10CyNo, 1495263508Sdim SwiftWriteLM11CyNo, SwiftWriteLM12CyNo, 1496263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, 1497263508Sdim SwiftWriteLM15CyNo, SwiftWriteLM16CyNo, 1498263508Sdim SwiftWriteLM17CyNo, SwiftWriteLM18CyNo]> 1499263508Sdim 1500263508Sdim ]> { let Variadic=1; } 1501263508Sdim 1502263508Sdim def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB], 1503263508Sdim (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$", 1504263508Sdim "(t|sys)LDM(IA|DA|DB|IB)$")>; 1505263508Sdim def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM], 1506263508Sdim (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/ 1507263508Sdim "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>; 1508263508Sdim def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle], 1509263508Sdim (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>; 1510263508Sdim // 4.2.23 Integer Store, Single Element 1511263508Sdim def : InstRW<[SwiftWriteP2], 1512263508Sdim (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", 1513263508Sdim "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>; 1514263508Sdim 1515263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2], 1516263508Sdim (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)", 1517263508Sdim "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)", 1518263508Sdim "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)", 1519263508Sdim "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>; 1520263508Sdim 1521263508Sdim // 4.2.24 Integer Store, Dual 1522263508Sdim def : InstRW<[SwiftWriteP2, SwiftWriteP2, SwiftWriteP01OneCycle], 1523263508Sdim (instregex "STRD$", "t2STRDi8")>; 1524263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2, SwiftWriteP2, 1525263508Sdim SwiftWriteP01OneCycle], 1526263508Sdim (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>; 1527263508Sdim 1528263508Sdim // 4.2.25 Integer Store, Multiple 1529263508Sdim def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { 1530263508Sdim let Latency = 0; 1531263508Sdim let NumMicroOps = 2; 1532263508Sdim } 1533263508Sdim foreach NumAddr = 1-16 in { 1534263508Sdim def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>; 1535263508Sdim } 1536263508Sdim def SwiftWriteSTM : SchedWriteVariant<[ 1537263508Sdim SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM2]>, 1538263508Sdim SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM3]>, 1539263508Sdim SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM4]>, 1540263508Sdim SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM5]>, 1541263508Sdim SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM6]>, 1542263508Sdim SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM7]>, 1543263508Sdim SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM8]>, 1544263508Sdim SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM9]>, 1545263508Sdim SchedVar<SwiftLMAddr10Pred,[SwiftWriteSTM10]>, 1546263508Sdim SchedVar<SwiftLMAddr11Pred,[SwiftWriteSTM11]>, 1547263508Sdim SchedVar<SwiftLMAddr12Pred,[SwiftWriteSTM12]>, 1548263508Sdim SchedVar<SwiftLMAddr13Pred,[SwiftWriteSTM13]>, 1549263508Sdim SchedVar<SwiftLMAddr14Pred,[SwiftWriteSTM14]>, 1550263508Sdim SchedVar<SwiftLMAddr15Pred,[SwiftWriteSTM15]>, 1551263508Sdim SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>, 1552263508Sdim // Unknow number of registers, just use resources for two registers. 1553263508Sdim SchedVar<NoSchedPred, [SwiftWriteSTM2]> 1554263508Sdim ]>; 1555263508Sdim def : InstRW<[SwiftWriteSTM], 1556263508Sdim (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>; 1557263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM], 1558263508Sdim (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD", 1559263508Sdim "PUSH", "tPUSH")>; 1560263508Sdim 1561263508Sdim // 4.2.26 Branch 1562263508Sdim def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; } 1563263508Sdim def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; } 1564263508Sdim def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; } 1565263508Sdim 1566263508Sdim // 4.2.27 Not issued 1567263508Sdim def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; } 1568263508Sdim def : InstRW<[WriteNoop], (instregex "t2IT", "IT", "NOP")>; 1569263508Sdim 1570263508Sdim // 4.2.28 Advanced SIMD, Integer, 2 cycle 1571263508Sdim def : InstRW<[SwiftWriteP0TwoCycle], 1572263508Sdim (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL", 1573263508Sdim "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi", 1574263508Sdim "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST", 1575263508Sdim "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF", 1576263508Sdim "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>; 1577263508Sdim 1578263508Sdim def : InstRW<[SwiftWriteP1TwoCycle], 1579263508Sdim (instregex "VEXT", "VREV16", "VREV32", "VREV64")>; 1580263508Sdim 1581263508Sdim // 4.2.29 Advanced SIMD, Integer, 4 cycle 1582263508Sdim // 4.2.30 Advanced SIMD, Integer with Accumulate 1583263508Sdim def : InstRW<[SwiftWriteP0FourCycle], 1584263508Sdim (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT", 1585263508Sdim "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL", 1586263508Sdim "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD", 1587263508Sdim "VQSUB")>; 1588263508Sdim def : InstRW<[SwiftWriteP1FourCycle], 1589263508Sdim (instregex "VRECPE", "VRSQRTE")>; 1590263508Sdim 1591263508Sdim // 4.2.31 Advanced SIMD, Add and Shift with Narrow 1592263508Sdim def : InstRW<[SwiftWriteP0P1FourCycle], 1593263508Sdim (instregex "VADDHN", "VSUBHN", "VSHRN")>; 1594263508Sdim def : InstRW<[SwiftWriteP0P1SixCycle], 1595263508Sdim (instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN", 1596263508Sdim "VQRSHRN", "VQRSHRUN")>; 1597263508Sdim 1598263508Sdim // 4.2.32 Advanced SIMD, Vector Table Lookup 1599263508Sdim foreach Num = 1-4 in { 1600263508Sdim def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>; 1601263508Sdim } 1602263508Sdim def : InstRW<[SwiftWrite1xP1TwoCycle], 1603263508Sdim (instregex "VTB(L|X)1")>; 1604263508Sdim def : InstRW<[SwiftWrite2xP1TwoCycle], 1605263508Sdim (instregex "VTB(L|X)2")>; 1606263508Sdim def : InstRW<[SwiftWrite3xP1TwoCycle], 1607263508Sdim (instregex "VTB(L|X)3")>; 1608263508Sdim def : InstRW<[SwiftWrite4xP1TwoCycle], 1609263508Sdim (instregex "VTB(L|X)4")>; 1610263508Sdim 1611263508Sdim // 4.2.33 Advanced SIMD, Transpose 1612263508Sdim def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle, 1613263508Sdim SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>], 1614263508Sdim (instregex "VSWP", "VTRN", "VUZP", "VZIP")>; 1615263508Sdim 1616263508Sdim // 4.2.34 Advanced SIMD and VFP, Floating Point 1617263508Sdim def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>; 1618263508Sdim def : InstRW<[SwiftWriteP0FourCycle], 1619263508Sdim (instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>; 1620263508Sdim def : InstRW<[SwiftWriteP0FourCycle], 1621263508Sdim (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX", 1622263508Sdim "VPMIN")>; 1623263508Sdim def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>; 1624263508Sdim def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>; 1625263508Sdim 1626263508Sdim // 4.2.35 Advanced SIMD and VFP, Multiply 1627263508Sdim def : InstRW<[SwiftWriteP1FourCycle], 1628263508Sdim (instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH", 1629263508Sdim "VMULL", "VQDMULL")>; 1630263508Sdim def : InstRW<[SwiftWriteP1SixCycle], 1631263508Sdim (instregex "VMULD", "VNMULD")>; 1632263508Sdim def : InstRW<[SwiftWriteP1FourCycle], 1633263508Sdim (instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)", 1634263508Sdim "VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>; 1635263508Sdim def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>; 1636263508Sdim def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>; 1637263508Sdim 1638263508Sdim // 4.2.36 Advanced SIMD and VFP, Convert 1639263508Sdim def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>; 1640263508Sdim // Fixpoint conversions. 1641263508Sdim def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; } 1642263508Sdim 1643263508Sdim // 4.2.37 Advanced SIMD and VFP, Move 1644263508Sdim def : InstRW<[SwiftWriteP0TwoCycle], 1645263508Sdim (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc", 1646263508Sdim "VMVNv", "VMVN(d|q)", "VMVN(S|D)cc", 1647263508Sdim "FCONST(D|S)")>; 1648263508Sdim def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>; 1649263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>], 1650263508Sdim (instregex "VQMOVN")>; 1651263508Sdim def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>; 1652263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>], 1653263508Sdim (instregex "VDUP(8|16|32)")>; 1654263508Sdim def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>; 1655263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>], 1656263508Sdim (instregex "VMOVSR$", "VSETLN")>; 1657263508Sdim def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle], 1658263508Sdim (instregex "VMOVRR(D|S)$")>; 1659263508Sdim def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>; 1660263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>, 1661263508Sdim WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle, 1662263508Sdim SwiftWriteP1TwoCycle]>], 1663263508Sdim (instregex "VMOVSRR$")>; 1664263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>], 1665263508Sdim (instregex "VGETLN(u|i)")>; 1666263508Sdim def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle, 1667263508Sdim SwiftWriteP01OneCycle]>], 1668263508Sdim (instregex "VGETLNs")>; 1669263508Sdim 1670263508Sdim // 4.2.38 Advanced SIMD and VFP, Move FPSCR 1671263508Sdim // Serializing instructions. 1672263508Sdim def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> { 1673263508Sdim let Latency = 15; 1674263508Sdim let ResourceCycles = [15]; 1675263508Sdim } 1676263508Sdim def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> { 1677263508Sdim let Latency = 15; 1678263508Sdim let ResourceCycles = [15]; 1679263508Sdim } 1680263508Sdim def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> { 1681263508Sdim let Latency = 15; 1682263508Sdim let ResourceCycles = [15]; 1683263508Sdim } 1684263508Sdim def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy], 1685263508Sdim (instregex "VMRS")>; 1686263508Sdim def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy], 1687263508Sdim (instregex "VMSR")>; 1688263508Sdim // Not serializing. 1689263508Sdim def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>; 1690263508Sdim 1691263508Sdim // 4.2.39 Advanced SIMD and VFP, Load Single Element 1692263508Sdim def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDRD$", "VLDRS$")>; 1693263508Sdim 1694263508Sdim // 4.2.40 Advanced SIMD and VFP, Store Single Element 1695263508Sdim def : InstRW<[SwiftWriteLM4Cy], (instregex "VSTRD$", "VSTRS$")>; 1696263508Sdim 1697263508Sdim // 4.2.41 Advanced SIMD and VFP, Load Multiple 1698263508Sdim // 4.2.42 Advanced SIMD and VFP, Store Multiple 1699263508Sdim 1700263508Sdim // Resource requirement for permuting, just reserves the resources. 1701263508Sdim foreach Num = 1-28 in { 1702263508Sdim def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> { 1703263508Sdim let Latency = 0; 1704263508Sdim let NumMicroOps = Num; 1705263508Sdim let ResourceCycles = [Num]; 1706263508Sdim } 1707263508Sdim } 1708263508Sdim 1709263508Sdim // Pre RA pseudos - load/store to a Q register as a D register pair. 1710263508Sdim def : InstRW<[SwiftWriteLM4Cy], (instregex "VLDMQIA$", "VSTMQIA$")>; 1711263508Sdim 1712263508Sdim // Post RA not modelled accurately. We assume that register use of width 64 1713263508Sdim // bit maps to a D register, 128 maps to a Q register. Not all different kinds 1714263508Sdim // are accurately represented. 1715263508Sdim def SwiftWriteVLDM : SchedWriteVariant<[ 1716263508Sdim // Load of one S register. 1717263508Sdim SchedVar<SwiftLMAddr1Pred, [SwiftWriteLM4Cy]>, 1718263508Sdim // Load of one D register. 1719263508Sdim SchedVar<SwiftLMAddr2Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo]>, 1720263508Sdim // Load of 3 S register. 1721263508Sdim SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1722263508Sdim SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, 1723263508Sdim SwiftVLDMPerm3]>, 1724263508Sdim // Load of a Q register (not neccessarily true). We should not be mapping to 1725263508Sdim // 4 S registers, either. 1726263508Sdim SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo, 1727263508Sdim SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>, 1728263508Sdim // Load of 5 S registers. 1729263508Sdim SchedVar<SwiftLMAddr5Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1730263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM14CyNo, 1731263508Sdim SwiftWriteLM17CyNo, SwiftWriteP01OneCycle, 1732263508Sdim SwiftVLDMPerm5]>, 1733263508Sdim // Load of 3 D registers. (Must also be able to handle s register list - 1734263508Sdim // though, not accurate) 1735263508Sdim SchedVar<SwiftLMAddr6Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1736263508Sdim SwiftWriteLM10Cy, SwiftWriteLM14CyNo, 1737263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1738263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm5]>, 1739263508Sdim // Load of 7 S registers. 1740263508Sdim SchedVar<SwiftLMAddr7Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1741263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 1742263508Sdim SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 1743263508Sdim SwiftWriteLM21CyNo, SwiftWriteP01OneCycle, 1744263508Sdim SwiftVLDMPerm7]>, 1745263508Sdim // Load of two Q registers. 1746263508Sdim SchedVar<SwiftLMAddr8Pred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1747263508Sdim SwiftWriteLM13Cy, SwiftWriteLM13CyNo, 1748263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1749263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1750263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm2]>, 1751263508Sdim // Load of 9 S registers. 1752263508Sdim SchedVar<SwiftLMAddr9Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1753263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 1754263508Sdim SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 1755263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1756263508Sdim SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 1757263508Sdim SwiftVLDMPerm9]>, 1758263508Sdim // Load of 5 D registers. 1759263508Sdim SchedVar<SwiftLMAddr10Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1760263508Sdim SwiftWriteLM10Cy, SwiftWriteLM14Cy, 1761263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1762263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1763263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1764263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm5]>, 1765263508Sdim // Inaccurate: reuse describtion from 9 S registers. 1766263508Sdim SchedVar<SwiftLMAddr11Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1767263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 1768263508Sdim SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 1769263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1770263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1771263508Sdim SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 1772263508Sdim SwiftVLDMPerm9]>, 1773263508Sdim // Load of three Q registers. 1774263508Sdim SchedVar<SwiftLMAddr12Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1775263508Sdim SwiftWriteLM11Cy, SwiftWriteLM11Cy, 1776263508Sdim SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 1777263508Sdim SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 1778263508Sdim SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 1779263508Sdim SwiftWriteLM11CyNo, SwiftWriteLM11CyNo, 1780263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm3]>, 1781263508Sdim // Inaccurate: reuse describtion from 9 S registers. 1782263508Sdim SchedVar<SwiftLMAddr13Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1783263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14CyNo, 1784263508Sdim SwiftWriteLM17CyNo, SwiftWriteLM18CyNo, 1785263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1786263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1787263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1788263508Sdim SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 1789263508Sdim SwiftVLDMPerm9]>, 1790263508Sdim // Load of 7 D registers inaccurate. 1791263508Sdim SchedVar<SwiftLMAddr14Pred,[SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1792263508Sdim SwiftWriteLM10Cy, SwiftWriteLM14Cy, 1793263508Sdim SwiftWriteLM14Cy, SwiftWriteLM14CyNo, 1794263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1795263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1796263508Sdim SwiftWriteLM14CyNo, SwiftWriteLM14CyNo, 1797263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm7]>, 1798263508Sdim SchedVar<SwiftLMAddr15Pred,[SwiftWriteLM9Cy, SwiftWriteLM10Cy, 1799263508Sdim SwiftWriteLM13Cy, SwiftWriteLM14Cy, 1800263508Sdim SwiftWriteLM17Cy, SwiftWriteLM18CyNo, 1801263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1802263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1803263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1804263508Sdim SwiftWriteLM21CyNo, SwiftWriteLM22CyNo, 1805263508Sdim SwiftWriteLM25CyNo, SwiftWriteP01OneCycle, 1806263508Sdim SwiftVLDMPerm9]>, 1807263508Sdim // Load of 4 Q registers. 1808263508Sdim SchedVar<SwiftLMAddr16Pred,[SwiftWriteLM7Cy, SwiftWriteLM10Cy, 1809263508Sdim SwiftWriteLM11Cy, SwiftWriteLM14Cy, 1810263508Sdim SwiftWriteLM15Cy, SwiftWriteLM18CyNo, 1811263508Sdim SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 1812263508Sdim SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 1813263508Sdim SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 1814263508Sdim SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 1815263508Sdim SwiftWriteLM19CyNo, SwiftWriteLM22CyNo, 1816263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm4]>, 1817263508Sdim // Unknow number of registers, just use resources for two registers. 1818263508Sdim SchedVar<NoSchedPred, [SwiftWriteLM7Cy, SwiftWriteLM8Cy, 1819263508Sdim SwiftWriteLM13Cy, SwiftWriteLM13CyNo, 1820263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1821263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1822263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1823263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1824263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1825263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1826263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1827263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1828263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1829263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1830263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1831263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1832263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1833263508Sdim SwiftWriteLM13CyNo, SwiftWriteLM13CyNo, 1834263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm2]> 1835263508Sdim ]> { let Variadic = 1; } 1836263508Sdim 1837263508Sdim def : InstRW<[SwiftWriteVLDM], (instregex "VLDM[SD](IA|DB)$")>; 1838263508Sdim 1839263508Sdim def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVLDM], 1840263508Sdim (instregex "VLDM[SD](IA|DB)_UPD$")>; 1841263508Sdim 1842263508Sdim def SwiftWriteVSTM : SchedWriteVariant<[ 1843263508Sdim // One S register. 1844263508Sdim SchedVar<SwiftLMAddr1Pred, [SwiftWriteSTM1]>, 1845263508Sdim // One D register. 1846263508Sdim SchedVar<SwiftLMAddr2Pred, [SwiftWriteSTM1]>, 1847263508Sdim // Three S registers. 1848263508Sdim SchedVar<SwiftLMAddr3Pred, [SwiftWriteSTM4]>, 1849263508Sdim // Assume one Q register. 1850263508Sdim SchedVar<SwiftLMAddr4Pred, [SwiftWriteSTM1]>, 1851263508Sdim SchedVar<SwiftLMAddr5Pred, [SwiftWriteSTM6]>, 1852263508Sdim // Assume three D registers. 1853263508Sdim SchedVar<SwiftLMAddr6Pred, [SwiftWriteSTM4]>, 1854263508Sdim SchedVar<SwiftLMAddr7Pred, [SwiftWriteSTM8]>, 1855263508Sdim // Assume two Q registers. 1856263508Sdim SchedVar<SwiftLMAddr8Pred, [SwiftWriteSTM3]>, 1857263508Sdim SchedVar<SwiftLMAddr9Pred, [SwiftWriteSTM10]>, 1858263508Sdim // Assume 5 D registers. 1859263508Sdim SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>, 1860263508Sdim SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>, 1861263508Sdim // Asume three Q registers. 1862263508Sdim SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>, 1863263508Sdim SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>, 1864263508Sdim // Assume 7 D registers. 1865263508Sdim SchedVar<SwiftLMAddr14Pred, [SwiftWriteSTM8]>, 1866263508Sdim SchedVar<SwiftLMAddr15Pred, [SwiftWriteSTM16]>, 1867263508Sdim // Assume four Q registers. 1868263508Sdim SchedVar<SwiftLMAddr16Pred, [SwiftWriteSTM5]>, 1869263508Sdim // Asumme two Q registers. 1870263508Sdim SchedVar<NoSchedPred, [SwiftWriteSTM3]> 1871263508Sdim ]> { let Variadic = 1; } 1872263508Sdim 1873263508Sdim def : InstRW<[SwiftWriteVSTM], (instregex "VSTM[SD](IA|DB)$")>; 1874263508Sdim 1875263508Sdim def : InstRW<[SwiftWriteP01OneCycle2x, SwiftWriteVSTM], 1876263508Sdim (instregex "VSTM[SD](IA|DB)_UPD")>; 1877263508Sdim 1878263508Sdim // 4.2.43 Advanced SIMD, Element or Structure Load and Store 1879263508Sdim def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> { 1880263508Sdim let Latency = 4; 1881263508Sdim let ResourceCycles = [2]; 1882263508Sdim } 1883263508Sdim def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> { 1884263508Sdim let Latency = 4; 1885263508Sdim let ResourceCycles = [3]; 1886263508Sdim } 1887263508Sdim foreach Num = 1-2 in { 1888263508Sdim def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> { 1889263508Sdim let Latency = 0; 1890263508Sdim let NumMicroOps = Num; 1891263508Sdim let ResourceCycles = [Num]; 1892263508Sdim } 1893263508Sdim } 1894263508Sdim // VLDx 1895263508Sdim // Multiple structures. 1896263508Sdim // Single element structure loads. 1897263508Sdim // We assume aligned. 1898263508Sdim // Single/two register. 1899263508Sdim def : InstRW<[SwiftWriteLM4Cy], (instregex "VLD1(d|q)(8|16|32|64)$")>; 1900263508Sdim def : InstRW<[SwiftWriteLM4Cy, SwiftWriteP01OneCycle], 1901263508Sdim (instregex "VLD1(d|q)(8|16|32|64)wb")>; 1902263508Sdim // Three register. 1903263508Sdim def : InstRW<[SwiftWrite3xP2FourCy], 1904263508Sdim (instregex "VLD1(d|q)(8|16|32|64)T$", "VLD1d64TPseudo")>; 1905263508Sdim def : InstRW<[SwiftWrite3xP2FourCy, SwiftWriteP01OneCycle], 1906263508Sdim (instregex "VLD1(d|q)(8|16|32|64)Twb")>; 1907263508Sdim /// Four Register. 1908263508Sdim def : InstRW<[SwiftWrite2xP2FourCy], 1909263508Sdim (instregex "VLD1(d|q)(8|16|32|64)Q$", "VLD1d64QPseudo")>; 1910263508Sdim def : InstRW<[SwiftWrite2xP2FourCy, SwiftWriteP01OneCycle], 1911263508Sdim (instregex "VLD1(d|q)(8|16|32|64)Qwb")>; 1912263508Sdim // Two element structure loads. 1913263508Sdim // Two/four register. 1914263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftExt2xP0, SwiftVLDMPerm2], 1915263508Sdim (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>; 1916263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 1917263508Sdim SwiftVLDMPerm2], 1918263508Sdim (instregex "VLD2(d|q|b)(8|16|32)wb", "VLD2q(8|16|32)PseudoWB")>; 1919263508Sdim // Three element structure. 1920263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, 1921263508Sdim SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 1922263508Sdim (instregex "VLD3(d|q)(8|16|32)$")>; 1923263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 1924263508Sdim (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo$")>; 1925263508Sdim 1926263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftWriteLM9CyNo, SwiftWriteLM9CyNo, 1927263508Sdim SwiftWriteP01OneCycle, SwiftVLDMPerm3, SwiftWrite3xP2FourCy], 1928263508Sdim (instregex "VLD3(d|q)(8|16|32)_UPD$")>; 1929263508Sdim def : InstRW<[SwiftWriteLM9Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm3, 1930263508Sdim SwiftWrite3xP2FourCy], 1931263508Sdim (instregex "VLD3(d|q)(8|16|32)(oddP|P)seudo_UPD")>; 1932263508Sdim // Four element structure loads. 1933263508Sdim def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, 1934263508Sdim SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, 1935263508Sdim SwiftWrite3xP2FourCy], 1936263508Sdim (instregex "VLD4(d|q)(8|16|32)$")>; 1937263508Sdim def : InstRW<[SwiftWriteLM11Cy, SwiftExt2xP0, SwiftVLDMPerm4, 1938263508Sdim SwiftWrite3xP2FourCy], 1939263508Sdim (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo$")>; 1940263508Sdim def : InstRW<[SwiftWriteLM11Cy, SwiftWriteLM11Cy, SwiftWriteLM11Cy, 1941263508Sdim SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 1942263508Sdim SwiftVLDMPerm4, SwiftWrite3xP2FourCy], 1943263508Sdim (instregex "VLD4(d|q)(8|16|32)_UPD")>; 1944263508Sdim def : InstRW<[SwiftWriteLM11Cy, SwiftWriteP01OneCycle, SwiftExt2xP0, 1945263508Sdim SwiftVLDMPerm4, SwiftWrite3xP2FourCy], 1946263508Sdim (instregex "VLD4(d|q)(8|16|32)(oddP|P)seudo_UPD")>; 1947263508Sdim 1948263508Sdim // Single all/lane loads. 1949263508Sdim // One element structure. 1950263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftVLDMPerm2], 1951263508Sdim (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 1952263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftVLDMPerm2], 1953263508Sdim (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", 1954263508Sdim "VLD1LNq(8|16|32)Pseudo_UPD")>; 1955263508Sdim // Two element structure. 1956263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftExt1xP0, SwiftVLDMPerm2], 1957263508Sdim (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$", 1958263508Sdim "VLD2LN(d|q)(8|16|32)Pseudo$")>; 1959263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftWriteLM6Cy, SwiftWriteP01OneCycle, 1960263508Sdim SwiftExt1xP0, SwiftVLDMPerm2], 1961263508Sdim (instregex "VLD2LN(d|q)(8|16|32)_UPD$")>; 1962263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, 1963263508Sdim SwiftExt1xP0, SwiftVLDMPerm2], 1964263508Sdim (instregex "VLD2DUPd(8|16|32|8x2|16x2|32x2)wb")>; 1965263508Sdim def : InstRW<[SwiftWriteLM6Cy, SwiftWriteP01OneCycle, SwiftWriteLM6Cy, 1966263508Sdim SwiftExt1xP0, SwiftVLDMPerm2], 1967263508Sdim (instregex "VLD2LN(d|q)(8|16|32)Pseudo_UPD")>; 1968263508Sdim // Three element structure. 1969263508Sdim def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, SwiftExt1xP0, 1970263508Sdim SwiftVLDMPerm3], 1971263508Sdim (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$", 1972263508Sdim "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 1973263508Sdim def : InstRW<[SwiftWriteLM7Cy, SwiftWriteLM8Cy, SwiftWriteLM8Cy, 1974263508Sdim SwiftWriteP01OneCycle, SwiftExt1xP0, SwiftVLDMPerm3], 1975263508Sdim (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>; 1976263508Sdim def : InstRW<[SwiftWriteLM7Cy, SwiftWriteP01OneCycle, SwiftWriteLM8Cy, 1977263508Sdim SwiftWriteLM8Cy, SwiftExt1xP0, SwiftVLDMPerm3], 1978263508Sdim (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>; 1979263508Sdim // Four element struture. 1980263508Sdim def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, 1981263508Sdim SwiftWriteLM10CyNo, SwiftExt1xP0, SwiftVLDMPerm5], 1982263508Sdim (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$", 1983263508Sdim "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>; 1984263508Sdim def : InstRW<[SwiftWriteLM8Cy, SwiftWriteLM9Cy, SwiftWriteLM10CyNo, 1985263508Sdim SwiftWriteLM10CyNo, SwiftWriteP01OneCycle, SwiftExt1xP0, 1986263508Sdim SwiftVLDMPerm5], 1987263508Sdim (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>; 1988263508Sdim def : InstRW<[SwiftWriteLM8Cy, SwiftWriteP01OneCycle, SwiftWriteLM9Cy, 1989263508Sdim SwiftWriteLM10CyNo, SwiftWriteLM10CyNo, SwiftExt1xP0, 1990263508Sdim SwiftVLDMPerm5], 1991263508Sdim (instregex "VLD4(DUP|LN)(d|q)(8|16|32)Pseudo_UPD")>; 1992263508Sdim // VSTx 1993263508Sdim // Multiple structures. 1994263508Sdim // Single element structure store. 1995263508Sdim def : InstRW<[SwiftWrite1xP2], (instregex "VST1d(8|16|32|64)$")>; 1996263508Sdim def : InstRW<[SwiftWrite2xP2], (instregex "VST1q(8|16|32|64)$")>; 1997263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2], 1998263508Sdim (instregex "VST1d(8|16|32|64)wb")>; 1999263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2], 2000263508Sdim (instregex "VST1q(8|16|32|64)wb")>; 2001263508Sdim def : InstRW<[SwiftWrite3xP2], 2002263508Sdim (instregex "VST1d(8|16|32|64)T$", "VST1d64TPseudo$")>; 2003263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite3xP2], 2004263508Sdim (instregex "VST1d(8|16|32|64)Twb", "VST1d64TPseudoWB")>; 2005263508Sdim def : InstRW<[SwiftWrite4xP2], 2006263508Sdim (instregex "VST1d(8|16|32|64)(Q|QPseudo)$")>; 2007263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2], 2008263508Sdim (instregex "VST1d(8|16|32|64)(Qwb|QPseudoWB)")>; 2009263508Sdim // Two element structure store. 2010263508Sdim def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1], 2011263508Sdim (instregex "VST2(d|b)(8|16|32)$")>; 2012263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1], 2013263508Sdim (instregex "VST2(b|d)(8|16|32)wb")>; 2014263508Sdim def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 2015263508Sdim (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>; 2016263508Sdim def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 2017263508Sdim (instregex "VST2q(8|16|32)wb", "VST2q(8|16|32)PseudoWB")>; 2018263508Sdim // Three element structure store. 2019263508Sdim def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 2020263508Sdim (instregex "VST3(d|q)(8|16|32)$", "VST3(d|q)(8|16|32)(oddP|P)seudo$")>; 2021263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2], 2022263508Sdim (instregex "VST3(d|q)(8|16|32)_UPD", 2023263508Sdim "VST3(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; 2024263508Sdim // Four element structure store. 2025263508Sdim def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 2026263508Sdim (instregex "VST4(d|q)(8|16|32)$", "VST4(d|q)(8|16|32)(oddP|P)seudo$")>; 2027263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm4], 2028263508Sdim (instregex "VST4(d|q)(8|16|32)_UPD", 2029263508Sdim "VST4(d|q)(8|16|32)(oddP|P)seudo_UPD$")>; 2030263508Sdim // Single/all lane store. 2031263508Sdim // One element structure. 2032263508Sdim def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm1], 2033263508Sdim (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>; 2034263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm1], 2035263508Sdim (instregex "VST1LNd(8|16|32)_UPD", "VST1LNq(8|16|32)Pseudo_UPD")>; 2036263508Sdim // Two element structure. 2037263508Sdim def : InstRW<[SwiftWrite1xP2, SwiftVLDMPerm2], 2038263508Sdim (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>; 2039263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite1xP2, SwiftVLDMPerm2], 2040263508Sdim (instregex "VST2LN(d|q)(8|16|32)_UPD", 2041263508Sdim "VST2LN(d|q)(8|16|32)Pseudo_UPD")>; 2042263508Sdim // Three element structure. 2043263508Sdim def : InstRW<[SwiftWrite4xP2, SwiftVLDMPerm2], 2044263508Sdim (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>; 2045263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite4xP2, SwiftVLDMPerm2], 2046263508Sdim (instregex "VST3LN(d|q)(8|16|32)_UPD", 2047263508Sdim "VST3LN(d|q)(8|16|32)Pseudo_UPD")>; 2048263508Sdim // Four element structure. 2049263508Sdim def : InstRW<[SwiftWrite2xP2, SwiftVLDMPerm2], 2050263508Sdim (instregex "VST4LN(d|q)(8|16|32)$", "VST4LN(d|q)(8|16|32)Pseudo$")>; 2051263508Sdim def : InstRW<[SwiftWriteP01OneCycle, SwiftWrite2xP2, SwiftVLDMPerm2], 2052263508Sdim (instregex "VST4LN(d|q)(8|16|32)_UPD", 2053263508Sdim "VST4LN(d|q)(8|16|32)Pseudo_UPD")>; 2054263508Sdim 2055263508Sdim // 4.2.44 VFP, Divide and Square Root 2056263508Sdim def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 2057263508Sdim let NumMicroOps = 1; 2058263508Sdim let Latency = 17; 2059263508Sdim let ResourceCycles = [1, 15]; 2060263508Sdim } 2061263508Sdim def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { 2062263508Sdim let NumMicroOps = 1; 2063263508Sdim let Latency = 32; 2064263508Sdim let ResourceCycles = [1, 30]; 2065263508Sdim } 2066263508Sdim def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>; 2067263508Sdim def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>; 2068263508Sdim 2069263508Sdim // Not specified. 2070263508Sdim def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>; 2071263508Sdim // Preload. 2072263508Sdim def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; 2073263508Sdim let ResourceCycles = [0]; 2074263508Sdim } 2075263508Sdim 2076249423Sdim} 2077