1234353Sdim//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the ARM register file 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed// Registers are identified with 4-bit ID numbers. 15239462Sdimclass ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> { 16239462Sdim let HWEncoding = Enc; 17193323Sed let Namespace = "ARM"; 18193323Sed let SubRegs = subregs; 19234353Sdim // All bits of ARM registers with sub-registers are covered by sub-registers. 20234353Sdim let CoveredBySubRegs = 1; 21193323Sed} 22193323Sed 23239462Sdimclass ARMFReg<bits<16> Enc, string n> : Register<n> { 24239462Sdim let HWEncoding = Enc; 25193323Sed let Namespace = "ARM"; 26193323Sed} 27193323Sed 28208599Srdivacky// Subregister indices. 29208599Srdivackylet Namespace = "ARM" in { 30263508Sdimdef qqsub_0 : SubRegIndex<256>; 31263508Sdimdef qqsub_1 : SubRegIndex<256, 256>; 32234353Sdim 33208599Srdivacky// Note: Code depends on these having consecutive numbers. 34263508Sdimdef qsub_0 : SubRegIndex<128>; 35263508Sdimdef qsub_1 : SubRegIndex<128, 128>; 36263508Sdimdef qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>; 37263508Sdimdef qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>; 38208599Srdivacky 39263508Sdimdef dsub_0 : SubRegIndex<64>; 40263508Sdimdef dsub_1 : SubRegIndex<64, 64>; 41263508Sdimdef dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>; 42263508Sdimdef dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>; 43263508Sdimdef dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>; 44263508Sdimdef dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>; 45263508Sdimdef dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>; 46263508Sdimdef dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>; 47208599Srdivacky 48263508Sdimdef ssub_0 : SubRegIndex<32>; 49263508Sdimdef ssub_1 : SubRegIndex<32, 32>; 50263508Sdimdef ssub_2 : ComposedSubRegIndex<dsub_1, ssub_0>; 51263508Sdimdef ssub_3 : ComposedSubRegIndex<dsub_1, ssub_1>; 52243830Sdim 53263508Sdimdef gsub_0 : SubRegIndex<32>; 54263508Sdimdef gsub_1 : SubRegIndex<32, 32>; 55234353Sdim// Let TableGen synthesize the remaining 12 ssub_* indices. 56234353Sdim// We don't need to name them. 57208599Srdivacky} 58208599Srdivacky 59193323Sed// Integer registers 60193323Seddef R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>; 61193323Seddef R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>; 62193323Seddef R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>; 63193323Seddef R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>; 64193323Seddef R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>; 65193323Seddef R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>; 66193323Seddef R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>; 67193323Seddef R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>; 68221345Sdim// These require 32-bit instructions. 69221345Sdimlet CostPerUse = 1 in { 70193323Seddef R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>; 71193323Seddef R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>; 72193323Seddef R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>; 73193323Seddef R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>; 74193323Seddef R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>; 75193323Seddef SP : ARMReg<13, "sp">, DwarfRegNum<[13]>; 76193323Seddef LR : ARMReg<14, "lr">, DwarfRegNum<[14]>; 77193323Seddef PC : ARMReg<15, "pc">, DwarfRegNum<[15]>; 78221345Sdim} 79193323Sed 80193323Sed// Float registers 81193323Seddef S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">; 82193323Seddef S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">; 83193323Seddef S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">; 84193323Seddef S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">; 85193323Seddef S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">; 86193323Seddef S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">; 87193323Seddef S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">; 88193323Seddef S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">; 89193323Seddef S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">; 90193323Seddef S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">; 91193323Seddef S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">; 92193323Seddef S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">; 93193323Seddef S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">; 94193323Seddef S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">; 95193323Seddef S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 96193323Seddef S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; 97193323Sed 98193323Sed// Aliases of the F* registers used to hold 64-bit fp values (doubles) 99208599Srdivackylet SubRegIndices = [ssub_0, ssub_1] in { 100221345Sdimdef D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>; 101221345Sdimdef D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>; 102221345Sdimdef D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>; 103221345Sdimdef D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>; 104221345Sdimdef D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>; 105221345Sdimdef D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>; 106221345Sdimdef D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>; 107221345Sdimdef D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>; 108221345Sdimdef D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>; 109221345Sdimdef D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>; 110221345Sdimdef D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>; 111221345Sdimdef D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>; 112221345Sdimdef D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>; 113221345Sdimdef D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>; 114221345Sdimdef D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>; 115221345Sdimdef D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>; 116208599Srdivacky} 117193323Sed 118194710Sed// VFP3 defines 16 additional double registers 119221345Sdimdef D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>; 120221345Sdimdef D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>; 121221345Sdimdef D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>; 122221345Sdimdef D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>; 123221345Sdimdef D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>; 124221345Sdimdef D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>; 125221345Sdimdef D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>; 126221345Sdimdef D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>; 127221345Sdimdef D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>; 128221345Sdimdef D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>; 129221345Sdimdef D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>; 130221345Sdimdef D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>; 131221345Sdimdef D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>; 132221345Sdimdef D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>; 133221345Sdimdef D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>; 134221345Sdimdef D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>; 135194710Sed 136194710Sed// Advanced SIMD (NEON) defines 16 quad-word aliases 137234353Sdimlet SubRegIndices = [dsub_0, dsub_1] in { 138194710Seddef Q0 : ARMReg< 0, "q0", [D0, D1]>; 139198090Srdivackydef Q1 : ARMReg< 1, "q1", [D2, D3]>; 140194710Seddef Q2 : ARMReg< 2, "q2", [D4, D5]>; 141194710Seddef Q3 : ARMReg< 3, "q3", [D6, D7]>; 142194710Seddef Q4 : ARMReg< 4, "q4", [D8, D9]>; 143194710Seddef Q5 : ARMReg< 5, "q5", [D10, D11]>; 144194710Seddef Q6 : ARMReg< 6, "q6", [D12, D13]>; 145194710Seddef Q7 : ARMReg< 7, "q7", [D14, D15]>; 146208599Srdivacky} 147208599Srdivackylet SubRegIndices = [dsub_0, dsub_1] in { 148194710Seddef Q8 : ARMReg< 8, "q8", [D16, D17]>; 149194710Seddef Q9 : ARMReg< 9, "q9", [D18, D19]>; 150194710Seddef Q10 : ARMReg<10, "q10", [D20, D21]>; 151194710Seddef Q11 : ARMReg<11, "q11", [D22, D23]>; 152194710Seddef Q12 : ARMReg<12, "q12", [D24, D25]>; 153194710Seddef Q13 : ARMReg<13, "q13", [D26, D27]>; 154194710Seddef Q14 : ARMReg<14, "q14", [D28, D29]>; 155194710Seddef Q15 : ARMReg<15, "q15", [D30, D31]>; 156208599Srdivacky} 157194710Sed 158234353Sdim// Current Program Status Register. 159234353Sdim// We model fpscr with two registers: FPSCR models the control bits and will be 160263508Sdim// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV 161263508Sdim// models the APSR when it's accessed by some special instructions. In such cases 162263508Sdim// it has the same encoding as PC. 163263508Sdimdef CPSR : ARMReg<0, "cpsr">; 164263508Sdimdef APSR : ARMReg<1, "apsr">; 165263508Sdimdef APSR_NZCV : ARMReg<15, "apsr_nzcv">; 166263508Sdimdef SPSR : ARMReg<2, "spsr">; 167263508Sdimdef FPSCR : ARMReg<3, "fpscr">; 168263508Sdimdef FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { 169234353Sdim let Aliases = [FPSCR]; 170208599Srdivacky} 171234353Sdimdef ITSTATE : ARMReg<4, "itstate">; 172208599Srdivacky 173218893Sdim// Special Registers - only available in privileged mode. 174263508Sdimdef FPSID : ARMReg<0, "fpsid">; 175263508Sdimdef MVFR2 : ARMReg<5, "mvfr2">; 176263508Sdimdef MVFR1 : ARMReg<6, "mvfr1">; 177263508Sdimdef MVFR0 : ARMReg<7, "mvfr0">; 178263508Sdimdef FPEXC : ARMReg<8, "fpexc">; 179263508Sdimdef FPINST : ARMReg<9, "fpinst">; 180263508Sdimdef FPINST2 : ARMReg<10, "fpinst2">; 181218893Sdim 182193323Sed// Register classes. 183193323Sed// 184193323Sed// pc == Program Counter 185193323Sed// lr == Link Register 186193323Sed// sp == Stack Pointer 187193323Sed// r12 == ip (scratch) 188193323Sed// r7 == Frame Pointer (thumb-style backtraces) 189194710Sed// r9 == May be reserved as Thread Register 190193323Sed// r11 == Frame Pointer (arm-style backtraces) 191193323Sed// r10 == Stack Limit 192193323Sed// 193224145Sdimdef GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), 194224145Sdim SP, LR, PC)> { 195224145Sdim // Allocate LR as the first CSR since it is always saved anyway. 196224145Sdim // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't 197224145Sdim // know how to spill them. If we make our prologue/epilogue code smarter at 198224145Sdim // some point, we can go back to using the above allocation orders for the 199224145Sdim // Thumb1 instructions that know how to use hi regs. 200224145Sdim let AltOrders = [(add LR, GPR), (trunc GPR, 8)]; 201224145Sdim let AltOrderSelect = [{ 202224145Sdim return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 203193323Sed }]; 204193323Sed} 205193323Sed 206226633Sdim// GPRs without the PC. Some ARM instructions do not allow the PC in 207226633Sdim// certain operand slots, particularly as the destination. Primarily 208226633Sdim// useful for disassembly. 209226633Sdimdef GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { 210226633Sdim let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 211226633Sdim let AltOrderSelect = [{ 212226633Sdim return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 213226633Sdim }]; 214226633Sdim} 215226633Sdim 216263508Sdim// GPRs without the PC but with APSR. Some instructions allow accessing the 217263508Sdim// APSR, while actually encoding PC in the register field. This is usefull 218263508Sdim// for assembly and disassembly only. 219263508Sdimdef GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { 220263508Sdim let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; 221263508Sdim let AltOrderSelect = [{ 222263508Sdim return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 223263508Sdim }]; 224263508Sdim} 225263508Sdim 226226633Sdim// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the 227226633Sdim// implied SP argument list. 228226633Sdim// FIXME: It would be better to not use this at all and refactor the 229226633Sdim// instructions to not have SP an an explicit argument. That makes 230226633Sdim// frame index resolution a bit trickier, though. 231226633Sdimdef GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; 232226633Sdim 233212904Sdim// restricted GPR register class. Many Thumb2 instructions allow the full 234212904Sdim// register range for operands, but have undefined behaviours when PC 235218893Sdim// or SP (R13 or R15) are used. The ARM ISA refers to these operands 236212904Sdim// via the BadReg() pseudo-code description. 237224145Sdimdef rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { 238224145Sdim let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; 239224145Sdim let AltOrderSelect = [{ 240224145Sdim return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 241193323Sed }]; 242193323Sed} 243193323Sed 244212904Sdim// Thumb registers are R0-R7 normally. Some instructions can still use 245212904Sdim// the general GPR register class above (MOV, e.g.) 246224145Sdimdef tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>; 247212904Sdim 248224145Sdim// The high registers in thumb mode, R8-R15. 249224145Sdimdef hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; 250224145Sdim 251210299Sed// For tail calls, we can't use callee-saved registers, as they are restored 252210299Sed// to the saved value before the tail call, which would clobber a call address. 253210299Sed// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of 254210299Sed// this class and the preceding one(!) This is what we want. 255263508Sdimdef tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { 256224145Sdim let AltOrders = [(and tcGPR, tGPR)]; 257224145Sdim let AltOrderSelect = [{ 258224145Sdim return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); 259210299Sed }]; 260210299Sed} 261210299Sed 262234353Sdim// Condition code registers. 263234353Sdimdef CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> { 264234353Sdim let CopyCost = -1; // Don't allow copying of status registers. 265234353Sdim let isAllocatable = 0; 266234353Sdim} 267234353Sdim 268194710Sed// Scalar single precision floating point register class.. 269243830Sdim// FIXME: Allocation order changed to s0, s2, s4, ... as a quick hack to 270243830Sdim// avoid partial-write dependencies on D registers (S registers are 271243830Sdim// renamed as portions of D registers). 272243830Sdimdef SPR : RegisterClass<"ARM", [f32], 32, (add (decimate 273243830Sdim (sequence "S%u", 0, 31), 2), 274243830Sdim (sequence "S%u", 0, 31))>; 275193323Sed 276198090Srdivacky// Subset of SPR which can be used as a source of NEON scalars for 16-bit 277198090Srdivacky// operations 278243830Sdimdef SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)>; 279198090Srdivacky 280194710Sed// Scalar double precision floating point / generic 64-bit vector register 281194710Sed// class. 282193323Sed// ARM requires only word alignment for double. It's more performant if it 283193323Sed// is double-word alignment though. 284194710Seddef DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 285224145Sdim (sequence "D%u", 0, 31)> { 286224145Sdim // Allocate non-VFP2 registers D16-D31 first. 287224145Sdim let AltOrders = [(rotl DPR, 16)]; 288224145Sdim let AltOrderSelect = [{ return 1; }]; 289194710Sed} 290194710Sed 291198090Srdivacky// Subset of DPR that are accessible with VFP2 (and so that also have 292198090Srdivacky// 32-bit SPR subregs). 293198892Srdivackydef DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 294239462Sdim (trunc DPR, 16)>; 295198090Srdivacky 296198090Srdivacky// Subset of DPR which can be used as a source of NEON scalars for 16-bit 297198090Srdivacky// operations 298198892Srdivackydef DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64, 299239462Sdim (trunc DPR, 8)>; 300198090Srdivacky 301194710Sed// Generic 128-bit vector register class. 302194710Seddef QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128, 303224145Sdim (sequence "Q%u", 0, 15)> { 304224145Sdim // Allocate non-VFP2 aliases Q8-Q15 first. 305224145Sdim let AltOrders = [(rotl QPR, 8)]; 306224145Sdim let AltOrderSelect = [{ return 1; }]; 307194710Sed} 308194710Sed 309198090Srdivacky// Subset of QPR that have 32-bit SPR subregs. 310198090Srdivackydef QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 311239462Sdim 128, (trunc QPR, 8)>; 312198090Srdivacky 313198892Srdivacky// Subset of QPR that have DPR_8 and SPR_8 subregs. 314198892Srdivackydef QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 315239462Sdim 128, (trunc QPR, 4)>; 316198892Srdivacky 317234353Sdim// Pseudo-registers representing odd-even pairs of D registers. The even-odd 318234353Sdim// pairs are already represented by the Q registers. 319234353Sdim// These are needed by NEON instructions requiring two consecutive D registers. 320234353Sdim// There is no D31_D0 register as that is always an UNPREDICTABLE encoding. 321234353Sdimdef TuplesOE2D : RegisterTuples<[dsub_0, dsub_1], 322234353Sdim [(decimate (shl DPR, 1), 2), 323234353Sdim (decimate (shl DPR, 2), 2)]>; 324234353Sdim 325234353Sdim// Register class representing a pair of consecutive D registers. 326234353Sdim// Use the Q registers for the even-odd pairs. 327234353Sdimdef DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 328234353Sdim 128, (interleave QPR, TuplesOE2D)> { 329234353Sdim // Allocate starting at non-VFP2 registers D16-D31 first. 330234353Sdim // Prefer even-odd pairs as they are easier to copy. 331234353Sdim let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))]; 332234353Sdim let AltOrderSelect = [{ return 1; }]; 333234353Sdim} 334234353Sdim 335243830Sdim// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP. 336243830Sdim// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs. 337243830Sdimdef Tuples2R : RegisterTuples<[gsub_0, gsub_1], 338243830Sdim [(add R0, R2, R4, R6, R8, R10, R12), 339243830Sdim (add R1, R3, R5, R7, R9, R11, SP)]>; 340243830Sdim 341243830Sdim// Register class representing a pair of even-odd GPRs. 342243830Sdimdef GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2R)> { 343243830Sdim let Size = 64; // 2 x 32 bits, we have no predefined type of that size. 344243830Sdim} 345243830Sdim 346234353Sdim// Pseudo-registers representing 3 consecutive D registers. 347234353Sdimdef Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2], 348234353Sdim [(shl DPR, 0), 349234353Sdim (shl DPR, 1), 350234353Sdim (shl DPR, 2)]>; 351234353Sdim 352234353Sdim// 3 consecutive D registers. 353234353Sdimdef DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> { 354234353Sdim let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 355234353Sdim} 356234353Sdim 357234353Sdim// Pseudo 256-bit registers to represent pairs of Q registers. These should 358234353Sdim// never be present in the emitted code. 359234353Sdim// These are used for NEON load / store instructions, e.g., vld4, vst3. 360234353Sdimdef Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>; 361234353Sdim 362208599Srdivacky// Pseudo 256-bit vector register class to model pairs of Q registers 363208599Srdivacky// (4 consecutive D registers). 364234353Sdimdef QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> { 365224145Sdim // Allocate non-VFP2 aliases first. 366234353Sdim let AltOrders = [(rotl QQPR, 8)]; 367224145Sdim let AltOrderSelect = [{ return 1; }]; 368208599Srdivacky} 369194178Sed 370234353Sdim// Tuples of 4 D regs that isn't also a pair of Q regs. 371234353Sdimdef TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3], 372234353Sdim [(decimate (shl DPR, 1), 2), 373234353Sdim (decimate (shl DPR, 2), 2), 374234353Sdim (decimate (shl DPR, 3), 2), 375234353Sdim (decimate (shl DPR, 4), 2)]>; 376194178Sed 377234353Sdim// 4 consecutive D registers. 378234353Sdimdef DQuad : RegisterClass<"ARM", [v4i64], 256, 379234353Sdim (interleave Tuples2Q, TuplesOE4D)>; 380194710Sed 381234353Sdim// Pseudo 512-bit registers to represent four consecutive Q registers. 382234353Sdimdef Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1], 383234353Sdim [(shl QQPR, 0), (shl QQPR, 2)]>; 384234353Sdim 385208599Srdivacky// Pseudo 512-bit vector register class to model 4 consecutive Q registers 386208599Srdivacky// (8 consecutive D registers). 387234353Sdimdef QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> { 388224145Sdim // Allocate non-VFP2 aliases first. 389234353Sdim let AltOrders = [(rotl QQQQPR, 8)]; 390224145Sdim let AltOrderSelect = [{ return 1; }]; 391208599Srdivacky} 392194178Sed 393234353Sdim 394234353Sdim// Pseudo-registers representing 2-spaced consecutive D registers. 395234353Sdimdef Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2], 396234353Sdim [(shl DPR, 0), 397234353Sdim (shl DPR, 2)]>; 398234353Sdim 399234353Sdim// Spaced pairs of D registers. 400234353Sdimdef DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>; 401234353Sdim 402234353Sdimdef Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4], 403234353Sdim [(shl DPR, 0), 404234353Sdim (shl DPR, 2), 405234353Sdim (shl DPR, 4)]>; 406234353Sdim 407234353Sdim// Spaced triples of D registers. 408234353Sdimdef DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> { 409234353Sdim let Size = 192; // 3 x 64 bits, we have no predefined type of that size. 410223017Sdim} 411234353Sdim 412234353Sdimdef Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6], 413234353Sdim [(shl DPR, 0), 414234353Sdim (shl DPR, 2), 415234353Sdim (shl DPR, 4), 416234353Sdim (shl DPR, 6)]>; 417234353Sdim 418234353Sdim// Spaced quads of D registers. 419234353Sdimdef DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>; 420