ARMInstrInfo.td revision 263508
1178479Sjb//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2178479Sjb// 3178479Sjb// The LLVM Compiler Infrastructure 4178479Sjb// 5178479Sjb// This file is distributed under the University of Illinois Open Source 6178479Sjb// License. See LICENSE.TXT for details. 7178479Sjb// 8178479Sjb//===----------------------------------------------------------------------===// 9178479Sjb// 10178479Sjb// This file describes the ARM instructions in TableGen format. 11178479Sjb// 12178479Sjb//===----------------------------------------------------------------------===// 13178479Sjb 14178479Sjb//===----------------------------------------------------------------------===// 15178479Sjb// ARM specific DAG Nodes. 16178479Sjb// 17178479Sjb 18178479Sjb// Type profiles. 19178479Sjbdef SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20178479Sjbdef SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21178479Sjbdef SDT_ARMStructByVal : SDTypeProfile<0, 4, 22178479Sjb [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 23178479Sjb SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 24178479Sjb 25178479Sjbdef SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 26178479Sjb 27178479Sjbdef SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 28178479Sjb 29178479Sjbdef SDT_ARMCMov : SDTypeProfile<1, 3, 30178479Sjb [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 31178479Sjb SDTCisVT<3, i32>]>; 32178479Sjb 33178479Sjbdef SDT_ARMBrcond : SDTypeProfile<0, 2, 34178479Sjb [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 35178479Sjb 36178479Sjbdef SDT_ARMBrJT : SDTypeProfile<0, 3, 37178479Sjb [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 38178479Sjb SDTCisVT<2, i32>]>; 39178479Sjb 40178479Sjbdef SDT_ARMBr2JT : SDTypeProfile<0, 4, 41178479Sjb [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42178479Sjb SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 43178479Sjb 44178479Sjbdef SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45178479Sjb [SDTCisVT<0, i32>, 46178479Sjb SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47178479Sjb SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48178479Sjb SDTCisVT<5, OtherVT>]>; 49178479Sjb 50178479Sjbdef SDT_ARMAnd : SDTypeProfile<1, 2, 51178479Sjb [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52178479Sjb SDTCisVT<2, i32>]>; 53178479Sjb 54178479Sjbdef SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55178479Sjb 56178479Sjbdef SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 57178479Sjb SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 58178479Sjb 59178479Sjbdef SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 60178479Sjbdef SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 61178479Sjb SDTCisInt<2>]>; 62178479Sjbdef SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 63178479Sjb 64178479Sjbdef SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 65178479Sjb 66178479Sjbdef SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 67178479Sjb SDTCisInt<1>]>; 68178479Sjb 69178479Sjbdef SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 70 71def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 73 74def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 75def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>; 76 77def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, SDTCisVT<1, i32>]>; 81 82// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 83def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, 87 SDTCisVT<1, i32>, 88 SDTCisVT<4, i32>]>; 89 90def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, 91 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >; 93def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>; 94def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>; 95 96// Node definitions. 97def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 98def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>; 99def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 100def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 101 102def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 103 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 104def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 105 [SDNPHasChain, SDNPSideEffect, 106 SDNPOptInGlue, SDNPOutGlue]>; 107def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 108 SDT_ARMStructByVal, 109 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 110 SDNPMayStore, SDNPMayLoad]>; 111 112def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 114 SDNPVariadic]>; 115def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 117 SDNPVariadic]>; 118def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 119 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 120 SDNPVariadic]>; 121 122def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 124def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 126def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 127 [SDNPInGlue]>; 128 129def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 130 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 131 132def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 133 [SDNPHasChain]>; 134def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 135 [SDNPHasChain]>; 136 137def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 138 [SDNPHasChain]>; 139 140def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 141 [SDNPOutGlue]>; 142 143def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 144 [SDNPOutGlue]>; 145 146def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 147 [SDNPOutGlue, SDNPCommutative]>; 148 149def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 150 151def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 152def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 153def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 154 155def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 156 [SDNPCommutative]>; 157def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 158def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 159def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 160 161def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 162def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 163 SDT_ARMEH_SJLJ_Setjmp, 164 [SDNPHasChain, SDNPSideEffect]>; 165def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 166 SDT_ARMEH_SJLJ_Longjmp, 167 [SDNPHasChain, SDNPSideEffect]>; 168 169def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 170 [SDNPHasChain, SDNPSideEffect]>; 171def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 172 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 173 174def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 175 176def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 178 179def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 180 181def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>; 182def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>; 183 184//===----------------------------------------------------------------------===// 185// ARM Instruction Predicate Definitions. 186// 187def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 188 AssemblerPredicate<"HasV4TOps", "armv4t">; 189def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 190def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 191def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 192 AssemblerPredicate<"HasV5TEOps", "armv5te">; 193def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 194 AssemblerPredicate<"HasV6Ops", "armv6">; 195def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 196def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 197 AssemblerPredicate<"HasV6MOps", 198 "armv6m or armv6t2">; 199def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 201def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 202def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 203 AssemblerPredicate<"HasV7Ops", "armv7">; 204def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 205 AssemblerPredicate<"HasV8Ops", "armv8">; 206def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 208def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 209def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 210 AssemblerPredicate<"FeatureVFP2", "VFP2">; 211def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 212 AssemblerPredicate<"FeatureVFP3", "VFP3">; 213def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 214 AssemblerPredicate<"FeatureVFP4", "VFP4">; 215def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 216 AssemblerPredicate<"!FeatureVFPOnlySP", 217 "double precision VFP">; 218def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 219 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 220def HasNEON : Predicate<"Subtarget->hasNEON()">, 221 AssemblerPredicate<"FeatureNEON", "NEON">; 222def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 223 AssemblerPredicate<"FeatureCrypto", "crypto">; 224def HasCRC : Predicate<"Subtarget->hasCRC()">, 225 AssemblerPredicate<"FeatureCRC", "crc">; 226def HasFP16 : Predicate<"Subtarget->hasFP16()">, 227 AssemblerPredicate<"FeatureFP16","half-float">; 228def HasDivide : Predicate<"Subtarget->hasDivide()">, 229 AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">; 230def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 231 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 232def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 233 AssemblerPredicate<"FeatureT2XtPk", 234 "pack/extract">; 235def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 236 AssemblerPredicate<"FeatureDSPThumb2", 237 "thumb2-dsp">; 238def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 239 AssemblerPredicate<"FeatureDB", 240 "data-barriers">; 241def HasMP : Predicate<"Subtarget->hasMPExtension()">, 242 AssemblerPredicate<"FeatureMP", 243 "mp-extensions">; 244def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 245 AssemblerPredicate<"FeatureTrustZone", 246 "TrustZone">; 247def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 248def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 249def IsThumb : Predicate<"Subtarget->isThumb()">, 250 AssemblerPredicate<"ModeThumb", "thumb">; 251def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 252def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 253 AssemblerPredicate<"ModeThumb,FeatureThumb2", 254 "thumb2">; 255def IsMClass : Predicate<"Subtarget->isMClass()">, 256 AssemblerPredicate<"FeatureMClass", "armv*m">; 257def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 258 AssemblerPredicate<"!FeatureMClass", 259 "!armv*m">; 260def IsARM : Predicate<"!Subtarget->isThumb()">, 261 AssemblerPredicate<"!ModeThumb", "arm-mode">; 262def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 263def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 264def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 265def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 266 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 267def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 268 269// FIXME: Eventually this will be just "hasV6T2Ops". 270def UseMovt : Predicate<"Subtarget->useMovt()">; 271def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 272def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 273def UseMulOps : Predicate<"Subtarget->useMulOps()">; 274 275// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 276// But only select them if more precision in FP computation is allowed. 277// Do not use them for Darwin platforms. 278def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 279 " FPOpFusion::Fast) && " 280 "!Subtarget->isTargetDarwin()">; 281def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion ==" 282 " FPOpFusion::Fast &&" 283 " Subtarget->hasVFP4()) || " 284 "Subtarget->isTargetDarwin()">; 285 286// VGETLNi32 is microcoded on Swift - prefer VMOV. 287def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">; 288def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">; 289 290// VDUP.32 is microcoded on Swift - prefer VMOV. 291def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">; 292def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">; 293 294// Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as 295// this allows more effective execution domain optimization. See 296// setExecutionDomain(). 297def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">; 298def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">; 299 300def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">; 301def IsBE : Predicate<"getTargetLowering()->isBigEndian()">; 302 303//===----------------------------------------------------------------------===// 304// ARM Flag Definitions. 305 306class RegConstraint<string C> { 307 string Constraints = C; 308} 309 310//===----------------------------------------------------------------------===// 311// ARM specific transformation functions and pattern fragments. 312// 313 314// imm_neg_XFORM - Return the negation of an i32 immediate value. 315def imm_neg_XFORM : SDNodeXForm<imm, [{ 316 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 317}]>; 318 319// imm_not_XFORM - Return the complement of a i32 immediate value. 320def imm_not_XFORM : SDNodeXForm<imm, [{ 321 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 322}]>; 323 324/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 325def imm16_31 : ImmLeaf<i32, [{ 326 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 327}]>; 328 329def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 330def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 331 unsigned Value = -(unsigned)N->getZExtValue(); 332 return Value && ARM_AM::getSOImmVal(Value) != -1; 333 }], imm_neg_XFORM> { 334 let ParserMatchClass = so_imm_neg_asmoperand; 335} 336 337// Note: this pattern doesn't require an encoder method and such, as it's 338// only used on aliases (Pat<> and InstAlias<>). The actual encoding 339// is handled by the destination instructions, which use so_imm. 340def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 341def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 342 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 343 }], imm_not_XFORM> { 344 let ParserMatchClass = so_imm_not_asmoperand; 345} 346 347// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 348def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 349 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 350}]>; 351 352/// Split a 32-bit immediate into two 16 bit parts. 353def hi16 : SDNodeXForm<imm, [{ 354 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 355}]>; 356 357def lo16AllZero : PatLeaf<(i32 imm), [{ 358 // Returns true if all low 16-bits are 0. 359 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 360}], hi16>; 361 362class BinOpWithFlagFrag<dag res> : 363 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 364class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 365class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 366 367// An 'and' node with a single use. 368def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 369 return N->hasOneUse(); 370}]>; 371 372// An 'xor' node with a single use. 373def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 374 return N->hasOneUse(); 375}]>; 376 377// An 'fmul' node with a single use. 378def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 379 return N->hasOneUse(); 380}]>; 381 382// An 'fadd' node which checks for single non-hazardous use. 383def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 384 return hasNoVMLxHazardUse(N); 385}]>; 386 387// An 'fsub' node which checks for single non-hazardous use. 388def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 389 return hasNoVMLxHazardUse(N); 390}]>; 391 392//===----------------------------------------------------------------------===// 393// Operand Definitions. 394// 395 396// Immediate operands with a shared generic asm render method. 397class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 398 399// Branch target. 400// FIXME: rename brtarget to t2_brtarget 401def brtarget : Operand<OtherVT> { 402 let EncoderMethod = "getBranchTargetOpValue"; 403 let OperandType = "OPERAND_PCREL"; 404 let DecoderMethod = "DecodeT2BROperand"; 405} 406 407// FIXME: get rid of this one? 408def uncondbrtarget : Operand<OtherVT> { 409 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 410 let OperandType = "OPERAND_PCREL"; 411} 412 413// Branch target for ARM. Handles conditional/unconditional 414def br_target : Operand<OtherVT> { 415 let EncoderMethod = "getARMBranchTargetOpValue"; 416 let OperandType = "OPERAND_PCREL"; 417} 418 419// Call target. 420// FIXME: rename bltarget to t2_bl_target? 421def bltarget : Operand<i32> { 422 // Encoded the same as branch targets. 423 let EncoderMethod = "getBranchTargetOpValue"; 424 let OperandType = "OPERAND_PCREL"; 425} 426 427// Call target for ARM. Handles conditional/unconditional 428// FIXME: rename bl_target to t2_bltarget? 429def bl_target : Operand<i32> { 430 let EncoderMethod = "getARMBLTargetOpValue"; 431 let OperandType = "OPERAND_PCREL"; 432} 433 434def blx_target : Operand<i32> { 435 let EncoderMethod = "getARMBLXTargetOpValue"; 436 let OperandType = "OPERAND_PCREL"; 437} 438 439// A list of registers separated by comma. Used by load/store multiple. 440def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 441def reglist : Operand<i32> { 442 let EncoderMethod = "getRegisterListOpValue"; 443 let ParserMatchClass = RegListAsmOperand; 444 let PrintMethod = "printRegisterList"; 445 let DecoderMethod = "DecodeRegListOperand"; 446} 447 448def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 449 450def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 451def dpr_reglist : Operand<i32> { 452 let EncoderMethod = "getRegisterListOpValue"; 453 let ParserMatchClass = DPRRegListAsmOperand; 454 let PrintMethod = "printRegisterList"; 455 let DecoderMethod = "DecodeDPRRegListOperand"; 456} 457 458def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 459def spr_reglist : Operand<i32> { 460 let EncoderMethod = "getRegisterListOpValue"; 461 let ParserMatchClass = SPRRegListAsmOperand; 462 let PrintMethod = "printRegisterList"; 463 let DecoderMethod = "DecodeSPRRegListOperand"; 464} 465 466// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 467def cpinst_operand : Operand<i32> { 468 let PrintMethod = "printCPInstOperand"; 469} 470 471// Local PC labels. 472def pclabel : Operand<i32> { 473 let PrintMethod = "printPCLabel"; 474} 475 476// ADR instruction labels. 477def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 478def adrlabel : Operand<i32> { 479 let EncoderMethod = "getAdrLabelOpValue"; 480 let ParserMatchClass = AdrLabelAsmOperand; 481 let PrintMethod = "printAdrLabelOperand<0>"; 482} 483 484def neon_vcvt_imm32 : Operand<i32> { 485 let EncoderMethod = "getNEONVcvtImm32OpValue"; 486 let DecoderMethod = "DecodeVCVTImmOperand"; 487} 488 489// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 490def rot_imm_XFORM: SDNodeXForm<imm, [{ 491 switch (N->getZExtValue()){ 492 default: assert(0); 493 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 494 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 495 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 496 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 497 } 498}]>; 499def RotImmAsmOperand : AsmOperandClass { 500 let Name = "RotImm"; 501 let ParserMethod = "parseRotImm"; 502} 503def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 504 int32_t v = N->getZExtValue(); 505 return v == 8 || v == 16 || v == 24; }], 506 rot_imm_XFORM> { 507 let PrintMethod = "printRotImmOperand"; 508 let ParserMatchClass = RotImmAsmOperand; 509} 510 511// shift_imm: An integer that encodes a shift amount and the type of shift 512// (asr or lsl). The 6-bit immediate encodes as: 513// {5} 0 ==> lsl 514// 1 asr 515// {4-0} imm5 shift amount. 516// asr #32 encoded as imm5 == 0. 517def ShifterImmAsmOperand : AsmOperandClass { 518 let Name = "ShifterImm"; 519 let ParserMethod = "parseShifterImm"; 520} 521def shift_imm : Operand<i32> { 522 let PrintMethod = "printShiftImmOperand"; 523 let ParserMatchClass = ShifterImmAsmOperand; 524} 525 526// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 527def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 528def so_reg_reg : Operand<i32>, // reg reg imm 529 ComplexPattern<i32, 3, "SelectRegShifterOperand", 530 [shl, srl, sra, rotr]> { 531 let EncoderMethod = "getSORegRegOpValue"; 532 let PrintMethod = "printSORegRegOperand"; 533 let DecoderMethod = "DecodeSORegRegOperand"; 534 let ParserMatchClass = ShiftedRegAsmOperand; 535 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 536} 537 538def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 539def so_reg_imm : Operand<i32>, // reg imm 540 ComplexPattern<i32, 2, "SelectImmShifterOperand", 541 [shl, srl, sra, rotr]> { 542 let EncoderMethod = "getSORegImmOpValue"; 543 let PrintMethod = "printSORegImmOperand"; 544 let DecoderMethod = "DecodeSORegImmOperand"; 545 let ParserMatchClass = ShiftedImmAsmOperand; 546 let MIOperandInfo = (ops GPR, i32imm); 547} 548 549// FIXME: Does this need to be distinct from so_reg? 550def shift_so_reg_reg : Operand<i32>, // reg reg imm 551 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 552 [shl,srl,sra,rotr]> { 553 let EncoderMethod = "getSORegRegOpValue"; 554 let PrintMethod = "printSORegRegOperand"; 555 let DecoderMethod = "DecodeSORegRegOperand"; 556 let ParserMatchClass = ShiftedRegAsmOperand; 557 let MIOperandInfo = (ops GPR, GPR, i32imm); 558} 559 560// FIXME: Does this need to be distinct from so_reg? 561def shift_so_reg_imm : Operand<i32>, // reg reg imm 562 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 563 [shl,srl,sra,rotr]> { 564 let EncoderMethod = "getSORegImmOpValue"; 565 let PrintMethod = "printSORegImmOperand"; 566 let DecoderMethod = "DecodeSORegImmOperand"; 567 let ParserMatchClass = ShiftedImmAsmOperand; 568 let MIOperandInfo = (ops GPR, i32imm); 569} 570 571 572// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 573// 8-bit immediate rotated by an arbitrary number of bits. 574def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 575def so_imm : Operand<i32>, ImmLeaf<i32, [{ 576 return ARM_AM::getSOImmVal(Imm) != -1; 577 }]> { 578 let EncoderMethod = "getSOImmOpValue"; 579 let ParserMatchClass = SOImmAsmOperand; 580 let DecoderMethod = "DecodeSOImmOperand"; 581} 582 583// Break so_imm's up into two pieces. This handles immediates with up to 16 584// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 585// get the first/second pieces. 586def so_imm2part : PatLeaf<(imm), [{ 587 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 588}]>; 589 590/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 591/// 592def arm_i32imm : PatLeaf<(imm), [{ 593 if (Subtarget->hasV6T2Ops()) 594 return true; 595 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 596}]>; 597 598/// imm0_1 predicate - Immediate in the range [0,1]. 599def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 600def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 601 602/// imm0_3 predicate - Immediate in the range [0,3]. 603def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 604def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 605 606/// imm0_7 predicate - Immediate in the range [0,7]. 607def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 608def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 609 return Imm >= 0 && Imm < 8; 610}]> { 611 let ParserMatchClass = Imm0_7AsmOperand; 612} 613 614/// imm8 predicate - Immediate is exactly 8. 615def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 616def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 617 let ParserMatchClass = Imm8AsmOperand; 618} 619 620/// imm16 predicate - Immediate is exactly 16. 621def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 622def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 623 let ParserMatchClass = Imm16AsmOperand; 624} 625 626/// imm32 predicate - Immediate is exactly 32. 627def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 628def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 629 let ParserMatchClass = Imm32AsmOperand; 630} 631 632/// imm1_7 predicate - Immediate in the range [1,7]. 633def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 634def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 635 let ParserMatchClass = Imm1_7AsmOperand; 636} 637 638/// imm1_15 predicate - Immediate in the range [1,15]. 639def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 640def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 641 let ParserMatchClass = Imm1_15AsmOperand; 642} 643 644/// imm1_31 predicate - Immediate in the range [1,31]. 645def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 646def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 647 let ParserMatchClass = Imm1_31AsmOperand; 648} 649 650/// imm0_15 predicate - Immediate in the range [0,15]. 651def Imm0_15AsmOperand: ImmAsmOperand { 652 let Name = "Imm0_15"; 653 let DiagnosticType = "ImmRange0_15"; 654} 655def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 656 return Imm >= 0 && Imm < 16; 657}]> { 658 let ParserMatchClass = Imm0_15AsmOperand; 659} 660 661/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 662def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 663def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 664 return Imm >= 0 && Imm < 32; 665}]> { 666 let ParserMatchClass = Imm0_31AsmOperand; 667} 668 669/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 670def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 671def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 672 return Imm >= 0 && Imm < 32; 673}]> { 674 let ParserMatchClass = Imm0_32AsmOperand; 675} 676 677/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 678def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 679def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 680 return Imm >= 0 && Imm < 64; 681}]> { 682 let ParserMatchClass = Imm0_63AsmOperand; 683} 684 685/// imm0_239 predicate - Immediate in the range [0,239]. 686def Imm0_239AsmOperand : ImmAsmOperand { 687 let Name = "Imm0_239"; 688 let DiagnosticType = "ImmRange0_239"; 689} 690def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 691 let ParserMatchClass = Imm0_239AsmOperand; 692} 693 694/// imm0_255 predicate - Immediate in the range [0,255]. 695def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 696def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 697 let ParserMatchClass = Imm0_255AsmOperand; 698} 699 700/// imm0_65535 - An immediate is in the range [0.65535]. 701def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 702def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 703 return Imm >= 0 && Imm < 65536; 704}]> { 705 let ParserMatchClass = Imm0_65535AsmOperand; 706} 707 708// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 709def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 710 return -Imm >= 0 && -Imm < 65536; 711}]>; 712 713// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 714// a relocatable expression. 715// 716// FIXME: This really needs a Thumb version separate from the ARM version. 717// While the range is the same, and can thus use the same match class, 718// the encoding is different so it should have a different encoder method. 719def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 720def imm0_65535_expr : Operand<i32> { 721 let EncoderMethod = "getHiLo16ImmOpValue"; 722 let ParserMatchClass = Imm0_65535ExprAsmOperand; 723} 724 725def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; } 726def imm256_65535_expr : Operand<i32> { 727 let ParserMatchClass = Imm256_65535ExprAsmOperand; 728} 729 730/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 731def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 732def imm24b : Operand<i32>, ImmLeaf<i32, [{ 733 return Imm >= 0 && Imm <= 0xffffff; 734}]> { 735 let ParserMatchClass = Imm24bitAsmOperand; 736} 737 738 739/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 740/// e.g., 0xf000ffff 741def BitfieldAsmOperand : AsmOperandClass { 742 let Name = "Bitfield"; 743 let ParserMethod = "parseBitfield"; 744} 745 746def bf_inv_mask_imm : Operand<i32>, 747 PatLeaf<(imm), [{ 748 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 749}] > { 750 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 751 let PrintMethod = "printBitfieldInvMaskImmOperand"; 752 let DecoderMethod = "DecodeBitfieldMaskOperand"; 753 let ParserMatchClass = BitfieldAsmOperand; 754} 755 756def imm1_32_XFORM: SDNodeXForm<imm, [{ 757 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 758}]>; 759def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 760def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 761 uint64_t Imm = N->getZExtValue(); 762 return Imm > 0 && Imm <= 32; 763 }], 764 imm1_32_XFORM> { 765 let PrintMethod = "printImmPlusOneOperand"; 766 let ParserMatchClass = Imm1_32AsmOperand; 767} 768 769def imm1_16_XFORM: SDNodeXForm<imm, [{ 770 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 771}]>; 772def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 773def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 774 imm1_16_XFORM> { 775 let PrintMethod = "printImmPlusOneOperand"; 776 let ParserMatchClass = Imm1_16AsmOperand; 777} 778 779// Define ARM specific addressing modes. 780// addrmode_imm12 := reg +/- imm12 781// 782def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 783class AddrMode_Imm12 : Operand<i32>, 784 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 785 // 12-bit immediate operand. Note that instructions using this encode 786 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 787 // immediate values are as normal. 788 789 let EncoderMethod = "getAddrModeImm12OpValue"; 790 let DecoderMethod = "DecodeAddrModeImm12Operand"; 791 let ParserMatchClass = MemImm12OffsetAsmOperand; 792 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 793} 794 795def addrmode_imm12 : AddrMode_Imm12 { 796 let PrintMethod = "printAddrModeImm12Operand<false>"; 797} 798 799def addrmode_imm12_pre : AddrMode_Imm12 { 800 let PrintMethod = "printAddrModeImm12Operand<true>"; 801} 802 803// ldst_so_reg := reg +/- reg shop imm 804// 805def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 806def ldst_so_reg : Operand<i32>, 807 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 808 let EncoderMethod = "getLdStSORegOpValue"; 809 // FIXME: Simplify the printer 810 let PrintMethod = "printAddrMode2Operand"; 811 let DecoderMethod = "DecodeSORegMemOperand"; 812 let ParserMatchClass = MemRegOffsetAsmOperand; 813 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 814} 815 816// postidx_imm8 := +/- [0,255] 817// 818// 9 bit value: 819// {8} 1 is imm8 is non-negative. 0 otherwise. 820// {7-0} [0,255] imm8 value. 821def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 822def postidx_imm8 : Operand<i32> { 823 let PrintMethod = "printPostIdxImm8Operand"; 824 let ParserMatchClass = PostIdxImm8AsmOperand; 825 let MIOperandInfo = (ops i32imm); 826} 827 828// postidx_imm8s4 := +/- [0,1020] 829// 830// 9 bit value: 831// {8} 1 is imm8 is non-negative. 0 otherwise. 832// {7-0} [0,255] imm8 value, scaled by 4. 833def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 834def postidx_imm8s4 : Operand<i32> { 835 let PrintMethod = "printPostIdxImm8s4Operand"; 836 let ParserMatchClass = PostIdxImm8s4AsmOperand; 837 let MIOperandInfo = (ops i32imm); 838} 839 840 841// postidx_reg := +/- reg 842// 843def PostIdxRegAsmOperand : AsmOperandClass { 844 let Name = "PostIdxReg"; 845 let ParserMethod = "parsePostIdxReg"; 846} 847def postidx_reg : Operand<i32> { 848 let EncoderMethod = "getPostIdxRegOpValue"; 849 let DecoderMethod = "DecodePostIdxReg"; 850 let PrintMethod = "printPostIdxRegOperand"; 851 let ParserMatchClass = PostIdxRegAsmOperand; 852 let MIOperandInfo = (ops GPRnopc, i32imm); 853} 854 855 856// addrmode2 := reg +/- imm12 857// := reg +/- reg shop imm 858// 859// FIXME: addrmode2 should be refactored the rest of the way to always 860// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 861def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 862def addrmode2 : Operand<i32>, 863 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 864 let EncoderMethod = "getAddrMode2OpValue"; 865 let PrintMethod = "printAddrMode2Operand"; 866 let ParserMatchClass = AddrMode2AsmOperand; 867 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 868} 869 870def PostIdxRegShiftedAsmOperand : AsmOperandClass { 871 let Name = "PostIdxRegShifted"; 872 let ParserMethod = "parsePostIdxReg"; 873} 874def am2offset_reg : Operand<i32>, 875 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 876 [], [SDNPWantRoot]> { 877 let EncoderMethod = "getAddrMode2OffsetOpValue"; 878 let PrintMethod = "printAddrMode2OffsetOperand"; 879 // When using this for assembly, it's always as a post-index offset. 880 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 881 let MIOperandInfo = (ops GPRnopc, i32imm); 882} 883 884// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 885// the GPR is purely vestigal at this point. 886def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 887def am2offset_imm : Operand<i32>, 888 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 889 [], [SDNPWantRoot]> { 890 let EncoderMethod = "getAddrMode2OffsetOpValue"; 891 let PrintMethod = "printAddrMode2OffsetOperand"; 892 let ParserMatchClass = AM2OffsetImmAsmOperand; 893 let MIOperandInfo = (ops GPRnopc, i32imm); 894} 895 896 897// addrmode3 := reg +/- reg 898// addrmode3 := reg +/- imm8 899// 900// FIXME: split into imm vs. reg versions. 901def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 902class AddrMode3 : Operand<i32>, 903 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 904 let EncoderMethod = "getAddrMode3OpValue"; 905 let ParserMatchClass = AddrMode3AsmOperand; 906 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 907} 908 909def addrmode3 : AddrMode3 910{ 911 let PrintMethod = "printAddrMode3Operand<false>"; 912} 913 914def addrmode3_pre : AddrMode3 915{ 916 let PrintMethod = "printAddrMode3Operand<true>"; 917} 918 919// FIXME: split into imm vs. reg versions. 920// FIXME: parser method to handle +/- register. 921def AM3OffsetAsmOperand : AsmOperandClass { 922 let Name = "AM3Offset"; 923 let ParserMethod = "parseAM3Offset"; 924} 925def am3offset : Operand<i32>, 926 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 927 [], [SDNPWantRoot]> { 928 let EncoderMethod = "getAddrMode3OffsetOpValue"; 929 let PrintMethod = "printAddrMode3OffsetOperand"; 930 let ParserMatchClass = AM3OffsetAsmOperand; 931 let MIOperandInfo = (ops GPR, i32imm); 932} 933 934// ldstm_mode := {ia, ib, da, db} 935// 936def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 937 let EncoderMethod = "getLdStmModeOpValue"; 938 let PrintMethod = "printLdStmModeOperand"; 939} 940 941// addrmode5 := reg +/- imm8*4 942// 943def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 944class AddrMode5 : Operand<i32>, 945 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 946 let EncoderMethod = "getAddrMode5OpValue"; 947 let DecoderMethod = "DecodeAddrMode5Operand"; 948 let ParserMatchClass = AddrMode5AsmOperand; 949 let MIOperandInfo = (ops GPR:$base, i32imm); 950} 951 952def addrmode5 : AddrMode5 { 953 let PrintMethod = "printAddrMode5Operand<false>"; 954} 955 956def addrmode5_pre : AddrMode5 { 957 let PrintMethod = "printAddrMode5Operand<true>"; 958} 959 960// addrmode6 := reg with optional alignment 961// 962def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 963def addrmode6 : Operand<i32>, 964 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 965 let PrintMethod = "printAddrMode6Operand"; 966 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 967 let EncoderMethod = "getAddrMode6AddressOpValue"; 968 let DecoderMethod = "DecodeAddrMode6Operand"; 969 let ParserMatchClass = AddrMode6AsmOperand; 970} 971 972def am6offset : Operand<i32>, 973 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 974 [], [SDNPWantRoot]> { 975 let PrintMethod = "printAddrMode6OffsetOperand"; 976 let MIOperandInfo = (ops GPR); 977 let EncoderMethod = "getAddrMode6OffsetOpValue"; 978 let DecoderMethod = "DecodeGPRRegisterClass"; 979} 980 981// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 982// (single element from one lane) for size 32. 983def addrmode6oneL32 : Operand<i32>, 984 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 985 let PrintMethod = "printAddrMode6Operand"; 986 let MIOperandInfo = (ops GPR:$addr, i32imm); 987 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 988} 989 990// Special version of addrmode6 to handle alignment encoding for VLD-dup 991// instructions, specifically VLD4-dup. 992def addrmode6dup : Operand<i32>, 993 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 994 let PrintMethod = "printAddrMode6Operand"; 995 let MIOperandInfo = (ops GPR:$addr, i32imm); 996 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 997 // FIXME: This is close, but not quite right. The alignment specifier is 998 // different. 999 let ParserMatchClass = AddrMode6AsmOperand; 1000} 1001 1002// addrmodepc := pc + reg 1003// 1004def addrmodepc : Operand<i32>, 1005 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1006 let PrintMethod = "printAddrModePCOperand"; 1007 let MIOperandInfo = (ops GPR, i32imm); 1008} 1009 1010// addr_offset_none := reg 1011// 1012def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1013def addr_offset_none : Operand<i32>, 1014 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1015 let PrintMethod = "printAddrMode7Operand"; 1016 let DecoderMethod = "DecodeAddrMode7Operand"; 1017 let ParserMatchClass = MemNoOffsetAsmOperand; 1018 let MIOperandInfo = (ops GPR:$base); 1019} 1020 1021def nohash_imm : Operand<i32> { 1022 let PrintMethod = "printNoHashImmediate"; 1023} 1024 1025def CoprocNumAsmOperand : AsmOperandClass { 1026 let Name = "CoprocNum"; 1027 let ParserMethod = "parseCoprocNumOperand"; 1028} 1029def p_imm : Operand<i32> { 1030 let PrintMethod = "printPImmediate"; 1031 let ParserMatchClass = CoprocNumAsmOperand; 1032 let DecoderMethod = "DecodeCoprocessor"; 1033} 1034 1035def CoprocRegAsmOperand : AsmOperandClass { 1036 let Name = "CoprocReg"; 1037 let ParserMethod = "parseCoprocRegOperand"; 1038} 1039def c_imm : Operand<i32> { 1040 let PrintMethod = "printCImmediate"; 1041 let ParserMatchClass = CoprocRegAsmOperand; 1042} 1043def CoprocOptionAsmOperand : AsmOperandClass { 1044 let Name = "CoprocOption"; 1045 let ParserMethod = "parseCoprocOptionOperand"; 1046} 1047def coproc_option_imm : Operand<i32> { 1048 let PrintMethod = "printCoprocOptionImm"; 1049 let ParserMatchClass = CoprocOptionAsmOperand; 1050} 1051 1052//===----------------------------------------------------------------------===// 1053 1054include "ARMInstrFormats.td" 1055 1056//===----------------------------------------------------------------------===// 1057// Multiclass helpers... 1058// 1059 1060/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 1061/// binop that produces a value. 1062let TwoOperandAliasConstraint = "$Rn = $Rd" in 1063multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1064 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1065 PatFrag opnode, bit Commutable = 0> { 1066 // The register-immediate version is re-materializable. This is useful 1067 // in particular for taking the address of a local. 1068 let isReMaterializable = 1 in { 1069 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1070 iii, opc, "\t$Rd, $Rn, $imm", 1071 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>, 1072 Sched<[WriteALU, ReadALU]> { 1073 bits<4> Rd; 1074 bits<4> Rn; 1075 bits<12> imm; 1076 let Inst{25} = 1; 1077 let Inst{19-16} = Rn; 1078 let Inst{15-12} = Rd; 1079 let Inst{11-0} = imm; 1080 } 1081 } 1082 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1083 iir, opc, "\t$Rd, $Rn, $Rm", 1084 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1085 Sched<[WriteALU, ReadALU, ReadALU]> { 1086 bits<4> Rd; 1087 bits<4> Rn; 1088 bits<4> Rm; 1089 let Inst{25} = 0; 1090 let isCommutable = Commutable; 1091 let Inst{19-16} = Rn; 1092 let Inst{15-12} = Rd; 1093 let Inst{11-4} = 0b00000000; 1094 let Inst{3-0} = Rm; 1095 } 1096 1097 def rsi : AsI1<opcod, (outs GPR:$Rd), 1098 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1099 iis, opc, "\t$Rd, $Rn, $shift", 1100 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1101 Sched<[WriteALUsi, ReadALU]> { 1102 bits<4> Rd; 1103 bits<4> Rn; 1104 bits<12> shift; 1105 let Inst{25} = 0; 1106 let Inst{19-16} = Rn; 1107 let Inst{15-12} = Rd; 1108 let Inst{11-5} = shift{11-5}; 1109 let Inst{4} = 0; 1110 let Inst{3-0} = shift{3-0}; 1111 } 1112 1113 def rsr : AsI1<opcod, (outs GPR:$Rd), 1114 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1115 iis, opc, "\t$Rd, $Rn, $shift", 1116 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1117 Sched<[WriteALUsr, ReadALUsr]> { 1118 bits<4> Rd; 1119 bits<4> Rn; 1120 bits<12> shift; 1121 let Inst{25} = 0; 1122 let Inst{19-16} = Rn; 1123 let Inst{15-12} = Rd; 1124 let Inst{11-8} = shift{11-8}; 1125 let Inst{7} = 0; 1126 let Inst{6-5} = shift{6-5}; 1127 let Inst{4} = 1; 1128 let Inst{3-0} = shift{3-0}; 1129 } 1130} 1131 1132/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1133/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1134/// it is equivalent to the AsI1_bin_irs counterpart. 1135let TwoOperandAliasConstraint = "$Rn = $Rd" in 1136multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1137 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1138 PatFrag opnode, bit Commutable = 0> { 1139 // The register-immediate version is re-materializable. This is useful 1140 // in particular for taking the address of a local. 1141 let isReMaterializable = 1 in { 1142 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1143 iii, opc, "\t$Rd, $Rn, $imm", 1144 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>, 1145 Sched<[WriteALU, ReadALU]> { 1146 bits<4> Rd; 1147 bits<4> Rn; 1148 bits<12> imm; 1149 let Inst{25} = 1; 1150 let Inst{19-16} = Rn; 1151 let Inst{15-12} = Rd; 1152 let Inst{11-0} = imm; 1153 } 1154 } 1155 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1156 iir, opc, "\t$Rd, $Rn, $Rm", 1157 [/* pattern left blank */]>, 1158 Sched<[WriteALU, ReadALU, ReadALU]> { 1159 bits<4> Rd; 1160 bits<4> Rn; 1161 bits<4> Rm; 1162 let Inst{11-4} = 0b00000000; 1163 let Inst{25} = 0; 1164 let Inst{3-0} = Rm; 1165 let Inst{15-12} = Rd; 1166 let Inst{19-16} = Rn; 1167 } 1168 1169 def rsi : AsI1<opcod, (outs GPR:$Rd), 1170 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1171 iis, opc, "\t$Rd, $Rn, $shift", 1172 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1173 Sched<[WriteALUsi, ReadALU]> { 1174 bits<4> Rd; 1175 bits<4> Rn; 1176 bits<12> shift; 1177 let Inst{25} = 0; 1178 let Inst{19-16} = Rn; 1179 let Inst{15-12} = Rd; 1180 let Inst{11-5} = shift{11-5}; 1181 let Inst{4} = 0; 1182 let Inst{3-0} = shift{3-0}; 1183 } 1184 1185 def rsr : AsI1<opcod, (outs GPR:$Rd), 1186 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1187 iis, opc, "\t$Rd, $Rn, $shift", 1188 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1189 Sched<[WriteALUsr, ReadALUsr]> { 1190 bits<4> Rd; 1191 bits<4> Rn; 1192 bits<12> shift; 1193 let Inst{25} = 0; 1194 let Inst{19-16} = Rn; 1195 let Inst{15-12} = Rd; 1196 let Inst{11-8} = shift{11-8}; 1197 let Inst{7} = 0; 1198 let Inst{6-5} = shift{6-5}; 1199 let Inst{4} = 1; 1200 let Inst{3-0} = shift{3-0}; 1201 } 1202} 1203 1204/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1205/// 1206/// These opcodes will be converted to the real non-S opcodes by 1207/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1208let hasPostISelHook = 1, Defs = [CPSR] in { 1209multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1210 InstrItinClass iis, PatFrag opnode, 1211 bit Commutable = 0> { 1212 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1213 4, iii, 1214 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>, 1215 Sched<[WriteALU, ReadALU]>; 1216 1217 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1218 4, iir, 1219 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1220 Sched<[WriteALU, ReadALU, ReadALU]> { 1221 let isCommutable = Commutable; 1222 } 1223 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1224 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1225 4, iis, 1226 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1227 so_reg_imm:$shift))]>, 1228 Sched<[WriteALUsi, ReadALU]>; 1229 1230 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1231 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1232 4, iis, 1233 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1234 so_reg_reg:$shift))]>, 1235 Sched<[WriteALUSsr, ReadALUsr]>; 1236} 1237} 1238 1239/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1240/// operands are reversed. 1241let hasPostISelHook = 1, Defs = [CPSR] in { 1242multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1243 InstrItinClass iis, PatFrag opnode, 1244 bit Commutable = 0> { 1245 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1246 4, iii, 1247 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>, 1248 Sched<[WriteALU, ReadALU]>; 1249 1250 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1251 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1252 4, iis, 1253 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1254 GPR:$Rn))]>, 1255 Sched<[WriteALUsi, ReadALU]>; 1256 1257 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1258 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1259 4, iis, 1260 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1261 GPR:$Rn))]>, 1262 Sched<[WriteALUSsr, ReadALUsr]>; 1263} 1264} 1265 1266/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1267/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1268/// a explicit result, only implicitly set CPSR. 1269let isCompare = 1, Defs = [CPSR] in { 1270multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1271 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1272 PatFrag opnode, bit Commutable = 0> { 1273 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1274 opc, "\t$Rn, $imm", 1275 [(opnode GPR:$Rn, so_imm:$imm)]>, 1276 Sched<[WriteCMP, ReadALU]> { 1277 bits<4> Rn; 1278 bits<12> imm; 1279 let Inst{25} = 1; 1280 let Inst{20} = 1; 1281 let Inst{19-16} = Rn; 1282 let Inst{15-12} = 0b0000; 1283 let Inst{11-0} = imm; 1284 1285 let Unpredictable{15-12} = 0b1111; 1286 } 1287 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1288 opc, "\t$Rn, $Rm", 1289 [(opnode GPR:$Rn, GPR:$Rm)]>, 1290 Sched<[WriteCMP, ReadALU, ReadALU]> { 1291 bits<4> Rn; 1292 bits<4> Rm; 1293 let isCommutable = Commutable; 1294 let Inst{25} = 0; 1295 let Inst{20} = 1; 1296 let Inst{19-16} = Rn; 1297 let Inst{15-12} = 0b0000; 1298 let Inst{11-4} = 0b00000000; 1299 let Inst{3-0} = Rm; 1300 1301 let Unpredictable{15-12} = 0b1111; 1302 } 1303 def rsi : AI1<opcod, (outs), 1304 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1305 opc, "\t$Rn, $shift", 1306 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1307 Sched<[WriteCMPsi, ReadALU]> { 1308 bits<4> Rn; 1309 bits<12> shift; 1310 let Inst{25} = 0; 1311 let Inst{20} = 1; 1312 let Inst{19-16} = Rn; 1313 let Inst{15-12} = 0b0000; 1314 let Inst{11-5} = shift{11-5}; 1315 let Inst{4} = 0; 1316 let Inst{3-0} = shift{3-0}; 1317 1318 let Unpredictable{15-12} = 0b1111; 1319 } 1320 def rsr : AI1<opcod, (outs), 1321 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1322 opc, "\t$Rn, $shift", 1323 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1324 Sched<[WriteCMPsr, ReadALU]> { 1325 bits<4> Rn; 1326 bits<12> shift; 1327 let Inst{25} = 0; 1328 let Inst{20} = 1; 1329 let Inst{19-16} = Rn; 1330 let Inst{15-12} = 0b0000; 1331 let Inst{11-8} = shift{11-8}; 1332 let Inst{7} = 0; 1333 let Inst{6-5} = shift{6-5}; 1334 let Inst{4} = 1; 1335 let Inst{3-0} = shift{3-0}; 1336 1337 let Unpredictable{15-12} = 0b1111; 1338 } 1339 1340} 1341} 1342 1343/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1344/// register and one whose operand is a register rotated by 8/16/24. 1345/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1346class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1347 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1348 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1349 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1350 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1351 bits<4> Rd; 1352 bits<4> Rm; 1353 bits<2> rot; 1354 let Inst{19-16} = 0b1111; 1355 let Inst{15-12} = Rd; 1356 let Inst{11-10} = rot; 1357 let Inst{3-0} = Rm; 1358} 1359 1360class AI_ext_rrot_np<bits<8> opcod, string opc> 1361 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1362 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1363 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1364 bits<2> rot; 1365 let Inst{19-16} = 0b1111; 1366 let Inst{11-10} = rot; 1367 } 1368 1369/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1370/// register and one whose operand is a register rotated by 8/16/24. 1371class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1372 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1373 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1374 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1375 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1376 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1377 bits<4> Rd; 1378 bits<4> Rm; 1379 bits<4> Rn; 1380 bits<2> rot; 1381 let Inst{19-16} = Rn; 1382 let Inst{15-12} = Rd; 1383 let Inst{11-10} = rot; 1384 let Inst{9-4} = 0b000111; 1385 let Inst{3-0} = Rm; 1386} 1387 1388class AI_exta_rrot_np<bits<8> opcod, string opc> 1389 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1390 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1391 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1392 bits<4> Rn; 1393 bits<2> rot; 1394 let Inst{19-16} = Rn; 1395 let Inst{11-10} = rot; 1396} 1397 1398/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1399let TwoOperandAliasConstraint = "$Rn = $Rd" in 1400multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1401 bit Commutable = 0> { 1402 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1403 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1404 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1405 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1406 Requires<[IsARM]>, 1407 Sched<[WriteALU, ReadALU]> { 1408 bits<4> Rd; 1409 bits<4> Rn; 1410 bits<12> imm; 1411 let Inst{25} = 1; 1412 let Inst{15-12} = Rd; 1413 let Inst{19-16} = Rn; 1414 let Inst{11-0} = imm; 1415 } 1416 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1417 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1418 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1419 Requires<[IsARM]>, 1420 Sched<[WriteALU, ReadALU, ReadALU]> { 1421 bits<4> Rd; 1422 bits<4> Rn; 1423 bits<4> Rm; 1424 let Inst{11-4} = 0b00000000; 1425 let Inst{25} = 0; 1426 let isCommutable = Commutable; 1427 let Inst{3-0} = Rm; 1428 let Inst{15-12} = Rd; 1429 let Inst{19-16} = Rn; 1430 } 1431 def rsi : AsI1<opcod, (outs GPR:$Rd), 1432 (ins GPR:$Rn, so_reg_imm:$shift), 1433 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1434 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1435 Requires<[IsARM]>, 1436 Sched<[WriteALUsi, ReadALU]> { 1437 bits<4> Rd; 1438 bits<4> Rn; 1439 bits<12> shift; 1440 let Inst{25} = 0; 1441 let Inst{19-16} = Rn; 1442 let Inst{15-12} = Rd; 1443 let Inst{11-5} = shift{11-5}; 1444 let Inst{4} = 0; 1445 let Inst{3-0} = shift{3-0}; 1446 } 1447 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1448 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1449 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1450 [(set GPRnopc:$Rd, CPSR, 1451 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1452 Requires<[IsARM]>, 1453 Sched<[WriteALUsr, ReadALUsr]> { 1454 bits<4> Rd; 1455 bits<4> Rn; 1456 bits<12> shift; 1457 let Inst{25} = 0; 1458 let Inst{19-16} = Rn; 1459 let Inst{15-12} = Rd; 1460 let Inst{11-8} = shift{11-8}; 1461 let Inst{7} = 0; 1462 let Inst{6-5} = shift{6-5}; 1463 let Inst{4} = 1; 1464 let Inst{3-0} = shift{3-0}; 1465 } 1466 } 1467} 1468 1469/// AI1_rsc_irs - Define instructions and patterns for rsc 1470let TwoOperandAliasConstraint = "$Rn = $Rd" in 1471multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> { 1472 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1473 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1474 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1475 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1476 Requires<[IsARM]>, 1477 Sched<[WriteALU, ReadALU]> { 1478 bits<4> Rd; 1479 bits<4> Rn; 1480 bits<12> imm; 1481 let Inst{25} = 1; 1482 let Inst{15-12} = Rd; 1483 let Inst{19-16} = Rn; 1484 let Inst{11-0} = imm; 1485 } 1486 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1487 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1488 [/* pattern left blank */]>, 1489 Sched<[WriteALU, ReadALU, ReadALU]> { 1490 bits<4> Rd; 1491 bits<4> Rn; 1492 bits<4> Rm; 1493 let Inst{11-4} = 0b00000000; 1494 let Inst{25} = 0; 1495 let Inst{3-0} = Rm; 1496 let Inst{15-12} = Rd; 1497 let Inst{19-16} = Rn; 1498 } 1499 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1500 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1501 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1502 Requires<[IsARM]>, 1503 Sched<[WriteALUsi, ReadALU]> { 1504 bits<4> Rd; 1505 bits<4> Rn; 1506 bits<12> shift; 1507 let Inst{25} = 0; 1508 let Inst{19-16} = Rn; 1509 let Inst{15-12} = Rd; 1510 let Inst{11-5} = shift{11-5}; 1511 let Inst{4} = 0; 1512 let Inst{3-0} = shift{3-0}; 1513 } 1514 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1515 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1516 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1517 Requires<[IsARM]>, 1518 Sched<[WriteALUsr, ReadALUsr]> { 1519 bits<4> Rd; 1520 bits<4> Rn; 1521 bits<12> shift; 1522 let Inst{25} = 0; 1523 let Inst{19-16} = Rn; 1524 let Inst{15-12} = Rd; 1525 let Inst{11-8} = shift{11-8}; 1526 let Inst{7} = 0; 1527 let Inst{6-5} = shift{6-5}; 1528 let Inst{4} = 1; 1529 let Inst{3-0} = shift{3-0}; 1530 } 1531 } 1532} 1533 1534let canFoldAsLoad = 1, isReMaterializable = 1 in { 1535multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1536 InstrItinClass iir, PatFrag opnode> { 1537 // Note: We use the complex addrmode_imm12 rather than just an input 1538 // GPR and a constrained immediate so that we can use this to match 1539 // frame index references and avoid matching constant pool references. 1540 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1541 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1542 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1543 bits<4> Rt; 1544 bits<17> addr; 1545 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1546 let Inst{19-16} = addr{16-13}; // Rn 1547 let Inst{15-12} = Rt; 1548 let Inst{11-0} = addr{11-0}; // imm12 1549 } 1550 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1551 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1552 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1553 bits<4> Rt; 1554 bits<17> shift; 1555 let shift{4} = 0; // Inst{4} = 0 1556 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1557 let Inst{19-16} = shift{16-13}; // Rn 1558 let Inst{15-12} = Rt; 1559 let Inst{11-0} = shift{11-0}; 1560 } 1561} 1562} 1563 1564let canFoldAsLoad = 1, isReMaterializable = 1 in { 1565multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1566 InstrItinClass iir, PatFrag opnode> { 1567 // Note: We use the complex addrmode_imm12 rather than just an input 1568 // GPR and a constrained immediate so that we can use this to match 1569 // frame index references and avoid matching constant pool references. 1570 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1571 (ins addrmode_imm12:$addr), 1572 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1573 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1574 bits<4> Rt; 1575 bits<17> addr; 1576 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1577 let Inst{19-16} = addr{16-13}; // Rn 1578 let Inst{15-12} = Rt; 1579 let Inst{11-0} = addr{11-0}; // imm12 1580 } 1581 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1582 (ins ldst_so_reg:$shift), 1583 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1584 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1585 bits<4> Rt; 1586 bits<17> shift; 1587 let shift{4} = 0; // Inst{4} = 0 1588 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1589 let Inst{19-16} = shift{16-13}; // Rn 1590 let Inst{15-12} = Rt; 1591 let Inst{11-0} = shift{11-0}; 1592 } 1593} 1594} 1595 1596 1597multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1598 InstrItinClass iir, PatFrag opnode> { 1599 // Note: We use the complex addrmode_imm12 rather than just an input 1600 // GPR and a constrained immediate so that we can use this to match 1601 // frame index references and avoid matching constant pool references. 1602 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1603 (ins GPR:$Rt, addrmode_imm12:$addr), 1604 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1605 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1606 bits<4> Rt; 1607 bits<17> addr; 1608 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1609 let Inst{19-16} = addr{16-13}; // Rn 1610 let Inst{15-12} = Rt; 1611 let Inst{11-0} = addr{11-0}; // imm12 1612 } 1613 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1614 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1615 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1616 bits<4> Rt; 1617 bits<17> shift; 1618 let shift{4} = 0; // Inst{4} = 0 1619 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1620 let Inst{19-16} = shift{16-13}; // Rn 1621 let Inst{15-12} = Rt; 1622 let Inst{11-0} = shift{11-0}; 1623 } 1624} 1625 1626multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1627 InstrItinClass iir, PatFrag opnode> { 1628 // Note: We use the complex addrmode_imm12 rather than just an input 1629 // GPR and a constrained immediate so that we can use this to match 1630 // frame index references and avoid matching constant pool references. 1631 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1632 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1633 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1634 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1635 bits<4> Rt; 1636 bits<17> addr; 1637 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1638 let Inst{19-16} = addr{16-13}; // Rn 1639 let Inst{15-12} = Rt; 1640 let Inst{11-0} = addr{11-0}; // imm12 1641 } 1642 def rs : AI2ldst<0b011, 0, isByte, (outs), 1643 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1644 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1645 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1646 bits<4> Rt; 1647 bits<17> shift; 1648 let shift{4} = 0; // Inst{4} = 0 1649 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1650 let Inst{19-16} = shift{16-13}; // Rn 1651 let Inst{15-12} = Rt; 1652 let Inst{11-0} = shift{11-0}; 1653 } 1654} 1655 1656 1657//===----------------------------------------------------------------------===// 1658// Instructions 1659//===----------------------------------------------------------------------===// 1660 1661//===----------------------------------------------------------------------===// 1662// Miscellaneous Instructions. 1663// 1664 1665/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1666/// the function. The first operand is the ID# for this instruction, the second 1667/// is the index into the MachineConstantPool that this is, the third is the 1668/// size in bytes of this constant pool entry. 1669let neverHasSideEffects = 1, isNotDuplicable = 1 in 1670def CONSTPOOL_ENTRY : 1671PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1672 i32imm:$size), NoItinerary, []>; 1673 1674// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1675// from removing one half of the matched pairs. That breaks PEI, which assumes 1676// these will always be in pairs, and asserts if it finds otherwise. Better way? 1677let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1678def ADJCALLSTACKUP : 1679PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1680 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1681 1682def ADJCALLSTACKDOWN : 1683PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1684 [(ARMcallseq_start timm:$amt)]>; 1685} 1686 1687def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 1688 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> { 1689 bits<8> imm; 1690 let Inst{27-8} = 0b00110010000011110000; 1691 let Inst{7-0} = imm; 1692} 1693 1694def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1695def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1696def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1697def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1698def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>; 1699def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 1700 1701def : Pat<(int_arm_sevl), (HINT 5)>; 1702 1703def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1704 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1705 bits<4> Rd; 1706 bits<4> Rn; 1707 bits<4> Rm; 1708 let Inst{3-0} = Rm; 1709 let Inst{15-12} = Rd; 1710 let Inst{19-16} = Rn; 1711 let Inst{27-20} = 0b01101000; 1712 let Inst{7-4} = 0b1011; 1713 let Inst{11-8} = 0b1111; 1714 let Unpredictable{11-8} = 0b1111; 1715} 1716 1717// The 16-bit operand $val can be used by a debugger to store more information 1718// about the breakpoint. 1719def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1720 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1721 bits<16> val; 1722 let Inst{3-0} = val{3-0}; 1723 let Inst{19-8} = val{15-4}; 1724 let Inst{27-20} = 0b00010010; 1725 let Inst{31-28} = 0xe; // AL 1726 let Inst{7-4} = 0b0111; 1727} 1728 1729def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1730 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 1731 bits<16> val; 1732 let Inst{3-0} = val{3-0}; 1733 let Inst{19-8} = val{15-4}; 1734 let Inst{27-20} = 0b00010000; 1735 let Inst{31-28} = 0xe; // AL 1736 let Inst{7-4} = 0b0111; 1737} 1738 1739// Change Processor State 1740// FIXME: We should use InstAlias to handle the optional operands. 1741class CPS<dag iops, string asm_ops> 1742 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1743 []>, Requires<[IsARM]> { 1744 bits<2> imod; 1745 bits<3> iflags; 1746 bits<5> mode; 1747 bit M; 1748 1749 let Inst{31-28} = 0b1111; 1750 let Inst{27-20} = 0b00010000; 1751 let Inst{19-18} = imod; 1752 let Inst{17} = M; // Enabled if mode is set; 1753 let Inst{16-9} = 0b00000000; 1754 let Inst{8-6} = iflags; 1755 let Inst{5} = 0; 1756 let Inst{4-0} = mode; 1757} 1758 1759let DecoderMethod = "DecodeCPSInstruction" in { 1760let M = 1 in 1761 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1762 "$imod\t$iflags, $mode">; 1763let mode = 0, M = 0 in 1764 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1765 1766let imod = 0, iflags = 0, M = 1 in 1767 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1768} 1769 1770// Preload signals the memory system of possible future data/instruction access. 1771multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1772 1773 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, 1774 !strconcat(opc, "\t$addr"), 1775 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 1776 Sched<[WritePreLd]> { 1777 bits<4> Rt; 1778 bits<17> addr; 1779 let Inst{31-26} = 0b111101; 1780 let Inst{25} = 0; // 0 for immediate form 1781 let Inst{24} = data; 1782 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1783 let Inst{22} = read; 1784 let Inst{21-20} = 0b01; 1785 let Inst{19-16} = addr{16-13}; // Rn 1786 let Inst{15-12} = 0b1111; 1787 let Inst{11-0} = addr{11-0}; // imm12 1788 } 1789 1790 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1791 !strconcat(opc, "\t$shift"), 1792 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 1793 Sched<[WritePreLd]> { 1794 bits<17> shift; 1795 let Inst{31-26} = 0b111101; 1796 let Inst{25} = 1; // 1 for register form 1797 let Inst{24} = data; 1798 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1799 let Inst{22} = read; 1800 let Inst{21-20} = 0b01; 1801 let Inst{19-16} = shift{16-13}; // Rn 1802 let Inst{15-12} = 0b1111; 1803 let Inst{11-0} = shift{11-0}; 1804 let Inst{4} = 0; 1805 } 1806} 1807 1808defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1809defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1810defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1811 1812def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1813 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 1814 bits<1> end; 1815 let Inst{31-10} = 0b1111000100000001000000; 1816 let Inst{9} = end; 1817 let Inst{8-0} = 0; 1818} 1819 1820def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1821 []>, Requires<[IsARM, HasV7]> { 1822 bits<4> opt; 1823 let Inst{27-4} = 0b001100100000111100001111; 1824 let Inst{3-0} = opt; 1825} 1826 1827/* 1828 * A5.4 Permanently UNDEFINED instructions. 1829 * 1830 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 1831 * Other UDF encodings generate SIGILL. 1832 * 1833 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 1834 * Encoding A1: 1835 * 1110 0111 1111 iiii iiii iiii 1111 iiii 1836 * Encoding T1: 1837 * 1101 1110 iiii iiii 1838 * It uses the following encoding: 1839 * 1110 0111 1111 1110 1101 1110 1111 0000 1840 * - In ARM: UDF #60896; 1841 * - In Thumb: UDF #254 followed by a branch-to-self. 1842 */ 1843let isBarrier = 1, isTerminator = 1 in 1844def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 1845 "trap", [(trap)]>, 1846 Requires<[IsARM,UseNaClTrap]> { 1847 let Inst = 0xe7fedef0; 1848} 1849let isBarrier = 1, isTerminator = 1 in 1850def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 1851 "trap", [(trap)]>, 1852 Requires<[IsARM,DontUseNaClTrap]> { 1853 let Inst = 0xe7ffdefe; 1854} 1855 1856// Address computation and loads and stores in PIC mode. 1857let isNotDuplicable = 1 in { 1858def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 1859 4, IIC_iALUr, 1860 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 1861 Sched<[WriteALU, ReadALU]>; 1862 1863let AddedComplexity = 10 in { 1864def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1865 4, IIC_iLoad_r, 1866 [(set GPR:$dst, (load addrmodepc:$addr))]>; 1867 1868def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1869 4, IIC_iLoad_bh_r, 1870 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 1871 1872def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1873 4, IIC_iLoad_bh_r, 1874 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 1875 1876def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1877 4, IIC_iLoad_bh_r, 1878 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 1879 1880def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1881 4, IIC_iLoad_bh_r, 1882 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 1883} 1884let AddedComplexity = 10 in { 1885def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1886 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 1887 1888def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1889 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 1890 addrmodepc:$addr)]>; 1891 1892def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1893 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 1894} 1895} // isNotDuplicable = 1 1896 1897 1898// LEApcrel - Load a pc-relative address into a register without offending the 1899// assembler. 1900let neverHasSideEffects = 1, isReMaterializable = 1 in 1901// The 'adr' mnemonic encodes differently if the label is before or after 1902// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 1903// know until then which form of the instruction will be used. 1904def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 1905 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 1906 Sched<[WriteALU, ReadALU]> { 1907 bits<4> Rd; 1908 bits<14> label; 1909 let Inst{27-25} = 0b001; 1910 let Inst{24} = 0; 1911 let Inst{23-22} = label{13-12}; 1912 let Inst{21} = 0; 1913 let Inst{20} = 0; 1914 let Inst{19-16} = 0b1111; 1915 let Inst{15-12} = Rd; 1916 let Inst{11-0} = label{11-0}; 1917} 1918 1919let hasSideEffects = 1 in { 1920def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 1921 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1922 1923def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 1924 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1925 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1926} 1927 1928//===----------------------------------------------------------------------===// 1929// Control Flow Instructions. 1930// 1931 1932let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1933 // ARMV4T and above 1934 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1935 "bx", "\tlr", [(ARMretflag)]>, 1936 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1937 let Inst{27-0} = 0b0001001011111111111100011110; 1938 } 1939 1940 // ARMV4 only 1941 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1942 "mov", "\tpc, lr", [(ARMretflag)]>, 1943 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 1944 let Inst{27-0} = 0b0001101000001111000000001110; 1945 } 1946 1947 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 1948 // the user-space one). 1949 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 1950 4, IIC_Br, 1951 [(ARMintretflag imm:$offset)]>; 1952} 1953 1954// Indirect branches 1955let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1956 // ARMV4T and above 1957 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 1958 [(brind GPR:$dst)]>, 1959 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1960 bits<4> dst; 1961 let Inst{31-4} = 0b1110000100101111111111110001; 1962 let Inst{3-0} = dst; 1963 } 1964 1965 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 1966 "bx", "\t$dst", [/* pattern left blank */]>, 1967 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 1968 bits<4> dst; 1969 let Inst{27-4} = 0b000100101111111111110001; 1970 let Inst{3-0} = dst; 1971 } 1972} 1973 1974// SP is marked as a use to prevent stack-pointer assignments that appear 1975// immediately before calls from potentially appearing dead. 1976let isCall = 1, 1977 // FIXME: Do we really need a non-predicated version? If so, it should 1978 // at least be a pseudo instruction expanding to the predicated version 1979 // at MC lowering time. 1980 Defs = [LR], Uses = [SP] in { 1981 def BL : ABXI<0b1011, (outs), (ins bl_target:$func), 1982 IIC_Br, "bl\t$func", 1983 [(ARMcall tglobaladdr:$func)]>, 1984 Requires<[IsARM]>, Sched<[WriteBrL]> { 1985 let Inst{31-28} = 0b1110; 1986 bits<24> func; 1987 let Inst{23-0} = func; 1988 let DecoderMethod = "DecodeBranchImmInstruction"; 1989 } 1990 1991 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func), 1992 IIC_Br, "bl", "\t$func", 1993 [(ARMcall_pred tglobaladdr:$func)]>, 1994 Requires<[IsARM]>, Sched<[WriteBrL]> { 1995 bits<24> func; 1996 let Inst{23-0} = func; 1997 let DecoderMethod = "DecodeBranchImmInstruction"; 1998 } 1999 2000 // ARMv5T and above 2001 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2002 IIC_Br, "blx\t$func", 2003 [(ARMcall GPR:$func)]>, 2004 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2005 bits<4> func; 2006 let Inst{31-4} = 0b1110000100101111111111110011; 2007 let Inst{3-0} = func; 2008 } 2009 2010 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2011 IIC_Br, "blx", "\t$func", 2012 [(ARMcall_pred GPR:$func)]>, 2013 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2014 bits<4> func; 2015 let Inst{27-4} = 0b000100101111111111110011; 2016 let Inst{3-0} = func; 2017 } 2018 2019 // ARMv4T 2020 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2021 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2022 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2023 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2024 2025 // ARMv4 2026 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2027 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2028 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2029 2030 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2031 // return stack predictor. 2032 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func), 2033 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2034 Requires<[IsARM]>, Sched<[WriteBr]>; 2035} 2036 2037let isBranch = 1, isTerminator = 1 in { 2038 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2039 // a two-value operand where a dag node expects two operands. :( 2040 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 2041 IIC_Br, "b", "\t$target", 2042 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2043 Sched<[WriteBr]> { 2044 bits<24> target; 2045 let Inst{23-0} = target; 2046 let DecoderMethod = "DecodeBranchImmInstruction"; 2047 } 2048 2049 let isBarrier = 1 in { 2050 // B is "predicable" since it's just a Bcc with an 'always' condition. 2051 let isPredicable = 1 in 2052 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2053 // should be sufficient. 2054 // FIXME: Is B really a Barrier? That doesn't seem right. 2055 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 2056 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>, 2057 Sched<[WriteBr]>; 2058 2059 let isNotDuplicable = 1, isIndirectBranch = 1 in { 2060 def BR_JTr : ARMPseudoInst<(outs), 2061 (ins GPR:$target, i32imm:$jt, i32imm:$id), 2062 0, IIC_Br, 2063 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>, 2064 Sched<[WriteBr]>; 2065 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 2066 // into i12 and rs suffixed versions. 2067 def BR_JTm : ARMPseudoInst<(outs), 2068 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 2069 0, IIC_Br, 2070 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 2071 imm:$id)]>, Sched<[WriteBrTbl]>; 2072 def BR_JTadd : ARMPseudoInst<(outs), 2073 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2074 0, IIC_Br, 2075 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2076 imm:$id)]>, Sched<[WriteBrTbl]>; 2077 } // isNotDuplicable = 1, isIndirectBranch = 1 2078 } // isBarrier = 1 2079 2080} 2081 2082// BLX (immediate) 2083def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2084 "blx\t$target", []>, 2085 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2086 let Inst{31-25} = 0b1111101; 2087 bits<25> target; 2088 let Inst{23-0} = target{24-1}; 2089 let Inst{24} = target{0}; 2090} 2091 2092// Branch and Exchange Jazelle 2093def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2094 [/* pattern left blank */]>, Sched<[WriteBr]> { 2095 bits<4> func; 2096 let Inst{23-20} = 0b0010; 2097 let Inst{19-8} = 0xfff; 2098 let Inst{7-4} = 0b0010; 2099 let Inst{3-0} = func; 2100} 2101 2102// Tail calls. 2103 2104let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2105 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2106 Sched<[WriteBr]>; 2107 2108 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2109 Sched<[WriteBr]>; 2110 2111 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst), 2112 4, IIC_Br, [], 2113 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2114 Requires<[IsARM]>, Sched<[WriteBr]>; 2115 2116 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2117 4, IIC_Br, [], 2118 (BX GPR:$dst)>, Sched<[WriteBr]>, 2119 Requires<[IsARM]>; 2120} 2121 2122// Secure Monitor Call is a system instruction. 2123def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2124 []>, Requires<[IsARM, HasTrustZone]> { 2125 bits<4> opt; 2126 let Inst{23-4} = 0b01100000000000000111; 2127 let Inst{3-0} = opt; 2128} 2129 2130// Supervisor Call (Software Interrupt) 2131let isCall = 1, Uses = [SP] in { 2132def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2133 Sched<[WriteBr]> { 2134 bits<24> svc; 2135 let Inst{23-0} = svc; 2136} 2137} 2138 2139// Store Return State 2140class SRSI<bit wb, string asm> 2141 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2142 NoItinerary, asm, "", []> { 2143 bits<5> mode; 2144 let Inst{31-28} = 0b1111; 2145 let Inst{27-25} = 0b100; 2146 let Inst{22} = 1; 2147 let Inst{21} = wb; 2148 let Inst{20} = 0; 2149 let Inst{19-16} = 0b1101; // SP 2150 let Inst{15-5} = 0b00000101000; 2151 let Inst{4-0} = mode; 2152} 2153 2154def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2155 let Inst{24-23} = 0; 2156} 2157def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2158 let Inst{24-23} = 0; 2159} 2160def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2161 let Inst{24-23} = 0b10; 2162} 2163def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2164 let Inst{24-23} = 0b10; 2165} 2166def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2167 let Inst{24-23} = 0b01; 2168} 2169def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2170 let Inst{24-23} = 0b01; 2171} 2172def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2173 let Inst{24-23} = 0b11; 2174} 2175def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2176 let Inst{24-23} = 0b11; 2177} 2178 2179def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2180def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2181 2182def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2183def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2184 2185def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2186def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2187 2188def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2189def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2190 2191// Return From Exception 2192class RFEI<bit wb, string asm> 2193 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2194 NoItinerary, asm, "", []> { 2195 bits<4> Rn; 2196 let Inst{31-28} = 0b1111; 2197 let Inst{27-25} = 0b100; 2198 let Inst{22} = 0; 2199 let Inst{21} = wb; 2200 let Inst{20} = 1; 2201 let Inst{19-16} = Rn; 2202 let Inst{15-0} = 0xa00; 2203} 2204 2205def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2206 let Inst{24-23} = 0; 2207} 2208def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2209 let Inst{24-23} = 0; 2210} 2211def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2212 let Inst{24-23} = 0b10; 2213} 2214def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2215 let Inst{24-23} = 0b10; 2216} 2217def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2218 let Inst{24-23} = 0b01; 2219} 2220def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2221 let Inst{24-23} = 0b01; 2222} 2223def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2224 let Inst{24-23} = 0b11; 2225} 2226def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2227 let Inst{24-23} = 0b11; 2228} 2229 2230//===----------------------------------------------------------------------===// 2231// Load / Store Instructions. 2232// 2233 2234// Load 2235 2236 2237defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2238 UnOpFrag<(load node:$Src)>>; 2239defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2240 UnOpFrag<(zextloadi8 node:$Src)>>; 2241defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2242 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2243defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2244 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2245 2246// Special LDR for loads from non-pc-relative constpools. 2247let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2248 isReMaterializable = 1, isCodeGenOnly = 1 in 2249def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2250 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2251 []> { 2252 bits<4> Rt; 2253 bits<17> addr; 2254 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2255 let Inst{19-16} = 0b1111; 2256 let Inst{15-12} = Rt; 2257 let Inst{11-0} = addr{11-0}; // imm12 2258} 2259 2260// Loads with zero extension 2261def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2262 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2263 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2264 2265// Loads with sign extension 2266def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2267 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2268 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2269 2270def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2271 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2272 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2273 2274let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2275// Load doubleword 2276def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2), 2277 (ins addrmode3:$addr), LdMiscFrm, 2278 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr", 2279 []>, Requires<[IsARM, HasV5TE]>; 2280} 2281 2282def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2283 NoItinerary, "lda", "\t$Rt, $addr", []>; 2284def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2285 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2286def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2287 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2288 2289// Indexed loads 2290multiclass AI2_ldridx<bit isByte, string opc, 2291 InstrItinClass iii, InstrItinClass iir> { 2292 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2293 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2294 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2295 bits<17> addr; 2296 let Inst{25} = 0; 2297 let Inst{23} = addr{12}; 2298 let Inst{19-16} = addr{16-13}; 2299 let Inst{11-0} = addr{11-0}; 2300 let DecoderMethod = "DecodeLDRPreImm"; 2301 } 2302 2303 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2304 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2305 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2306 bits<17> addr; 2307 let Inst{25} = 1; 2308 let Inst{23} = addr{12}; 2309 let Inst{19-16} = addr{16-13}; 2310 let Inst{11-0} = addr{11-0}; 2311 let Inst{4} = 0; 2312 let DecoderMethod = "DecodeLDRPreReg"; 2313 } 2314 2315 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2316 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2317 IndexModePost, LdFrm, iir, 2318 opc, "\t$Rt, $addr, $offset", 2319 "$addr.base = $Rn_wb", []> { 2320 // {12} isAdd 2321 // {11-0} imm12/Rm 2322 bits<14> offset; 2323 bits<4> addr; 2324 let Inst{25} = 1; 2325 let Inst{23} = offset{12}; 2326 let Inst{19-16} = addr; 2327 let Inst{11-0} = offset{11-0}; 2328 let Inst{4} = 0; 2329 2330 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2331 } 2332 2333 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2334 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2335 IndexModePost, LdFrm, iii, 2336 opc, "\t$Rt, $addr, $offset", 2337 "$addr.base = $Rn_wb", []> { 2338 // {12} isAdd 2339 // {11-0} imm12/Rm 2340 bits<14> offset; 2341 bits<4> addr; 2342 let Inst{25} = 0; 2343 let Inst{23} = offset{12}; 2344 let Inst{19-16} = addr; 2345 let Inst{11-0} = offset{11-0}; 2346 2347 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2348 } 2349 2350} 2351 2352let mayLoad = 1, neverHasSideEffects = 1 in { 2353// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2354// IIC_iLoad_siu depending on whether it the offset register is shifted. 2355defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2356defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2357} 2358 2359multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2360 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2361 (ins addrmode3_pre:$addr), IndexModePre, 2362 LdMiscFrm, itin, 2363 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2364 bits<14> addr; 2365 let Inst{23} = addr{8}; // U bit 2366 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2367 let Inst{19-16} = addr{12-9}; // Rn 2368 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2369 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2370 let DecoderMethod = "DecodeAddrMode3Instruction"; 2371 } 2372 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2373 (ins addr_offset_none:$addr, am3offset:$offset), 2374 IndexModePost, LdMiscFrm, itin, 2375 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2376 []> { 2377 bits<10> offset; 2378 bits<4> addr; 2379 let Inst{23} = offset{8}; // U bit 2380 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2381 let Inst{19-16} = addr; 2382 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2383 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2384 let DecoderMethod = "DecodeAddrMode3Instruction"; 2385 } 2386} 2387 2388let mayLoad = 1, neverHasSideEffects = 1 in { 2389defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2390defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2391defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2392let hasExtraDefRegAllocReq = 1 in { 2393def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2394 (ins addrmode3_pre:$addr), IndexModePre, 2395 LdMiscFrm, IIC_iLoad_d_ru, 2396 "ldrd", "\t$Rt, $Rt2, $addr!", 2397 "$addr.base = $Rn_wb", []> { 2398 bits<14> addr; 2399 let Inst{23} = addr{8}; // U bit 2400 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2401 let Inst{19-16} = addr{12-9}; // Rn 2402 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2403 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2404 let DecoderMethod = "DecodeAddrMode3Instruction"; 2405} 2406def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2407 (ins addr_offset_none:$addr, am3offset:$offset), 2408 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2409 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2410 "$addr.base = $Rn_wb", []> { 2411 bits<10> offset; 2412 bits<4> addr; 2413 let Inst{23} = offset{8}; // U bit 2414 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2415 let Inst{19-16} = addr; 2416 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2417 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2418 let DecoderMethod = "DecodeAddrMode3Instruction"; 2419} 2420} // hasExtraDefRegAllocReq = 1 2421} // mayLoad = 1, neverHasSideEffects = 1 2422 2423// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2424let mayLoad = 1, neverHasSideEffects = 1 in { 2425def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2426 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2427 IndexModePost, LdFrm, IIC_iLoad_ru, 2428 "ldrt", "\t$Rt, $addr, $offset", 2429 "$addr.base = $Rn_wb", []> { 2430 // {12} isAdd 2431 // {11-0} imm12/Rm 2432 bits<14> offset; 2433 bits<4> addr; 2434 let Inst{25} = 1; 2435 let Inst{23} = offset{12}; 2436 let Inst{21} = 1; // overwrite 2437 let Inst{19-16} = addr; 2438 let Inst{11-5} = offset{11-5}; 2439 let Inst{4} = 0; 2440 let Inst{3-0} = offset{3-0}; 2441 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2442} 2443 2444def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2445 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2446 IndexModePost, LdFrm, IIC_iLoad_ru, 2447 "ldrt", "\t$Rt, $addr, $offset", 2448 "$addr.base = $Rn_wb", []> { 2449 // {12} isAdd 2450 // {11-0} imm12/Rm 2451 bits<14> offset; 2452 bits<4> addr; 2453 let Inst{25} = 0; 2454 let Inst{23} = offset{12}; 2455 let Inst{21} = 1; // overwrite 2456 let Inst{19-16} = addr; 2457 let Inst{11-0} = offset{11-0}; 2458 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2459} 2460 2461def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2462 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2463 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2464 "ldrbt", "\t$Rt, $addr, $offset", 2465 "$addr.base = $Rn_wb", []> { 2466 // {12} isAdd 2467 // {11-0} imm12/Rm 2468 bits<14> offset; 2469 bits<4> addr; 2470 let Inst{25} = 1; 2471 let Inst{23} = offset{12}; 2472 let Inst{21} = 1; // overwrite 2473 let Inst{19-16} = addr; 2474 let Inst{11-5} = offset{11-5}; 2475 let Inst{4} = 0; 2476 let Inst{3-0} = offset{3-0}; 2477 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2478} 2479 2480def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2481 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2482 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2483 "ldrbt", "\t$Rt, $addr, $offset", 2484 "$addr.base = $Rn_wb", []> { 2485 // {12} isAdd 2486 // {11-0} imm12/Rm 2487 bits<14> offset; 2488 bits<4> addr; 2489 let Inst{25} = 0; 2490 let Inst{23} = offset{12}; 2491 let Inst{21} = 1; // overwrite 2492 let Inst{19-16} = addr; 2493 let Inst{11-0} = offset{11-0}; 2494 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2495} 2496 2497multiclass AI3ldrT<bits<4> op, string opc> { 2498 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2499 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2500 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2501 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2502 bits<9> offset; 2503 let Inst{23} = offset{8}; 2504 let Inst{22} = 1; 2505 let Inst{11-8} = offset{7-4}; 2506 let Inst{3-0} = offset{3-0}; 2507 } 2508 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2509 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2510 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2511 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2512 bits<5> Rm; 2513 let Inst{23} = Rm{4}; 2514 let Inst{22} = 0; 2515 let Inst{11-8} = 0; 2516 let Unpredictable{11-8} = 0b1111; 2517 let Inst{3-0} = Rm{3-0}; 2518 let DecoderMethod = "DecodeLDR"; 2519 } 2520} 2521 2522defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2523defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2524defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2525} 2526 2527// Store 2528 2529// Stores with truncate 2530def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2531 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2532 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2533 2534// Store doubleword 2535let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 2536def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr), 2537 StMiscFrm, IIC_iStore_d_r, 2538 "strd", "\t$Rt, $src2, $addr", []>, 2539 Requires<[IsARM, HasV5TE]> { 2540 let Inst{21} = 0; 2541} 2542 2543// Indexed stores 2544multiclass AI2_stridx<bit isByte, string opc, 2545 InstrItinClass iii, InstrItinClass iir> { 2546 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2547 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2548 StFrm, iii, 2549 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2550 bits<17> addr; 2551 let Inst{25} = 0; 2552 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2553 let Inst{19-16} = addr{16-13}; // Rn 2554 let Inst{11-0} = addr{11-0}; // imm12 2555 let DecoderMethod = "DecodeSTRPreImm"; 2556 } 2557 2558 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2559 (ins GPR:$Rt, ldst_so_reg:$addr), 2560 IndexModePre, StFrm, iir, 2561 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2562 bits<17> addr; 2563 let Inst{25} = 1; 2564 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2565 let Inst{19-16} = addr{16-13}; // Rn 2566 let Inst{11-0} = addr{11-0}; 2567 let Inst{4} = 0; // Inst{4} = 0 2568 let DecoderMethod = "DecodeSTRPreReg"; 2569 } 2570 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2571 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2572 IndexModePost, StFrm, iir, 2573 opc, "\t$Rt, $addr, $offset", 2574 "$addr.base = $Rn_wb", []> { 2575 // {12} isAdd 2576 // {11-0} imm12/Rm 2577 bits<14> offset; 2578 bits<4> addr; 2579 let Inst{25} = 1; 2580 let Inst{23} = offset{12}; 2581 let Inst{19-16} = addr; 2582 let Inst{11-0} = offset{11-0}; 2583 let Inst{4} = 0; 2584 2585 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2586 } 2587 2588 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2589 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2590 IndexModePost, StFrm, iii, 2591 opc, "\t$Rt, $addr, $offset", 2592 "$addr.base = $Rn_wb", []> { 2593 // {12} isAdd 2594 // {11-0} imm12/Rm 2595 bits<14> offset; 2596 bits<4> addr; 2597 let Inst{25} = 0; 2598 let Inst{23} = offset{12}; 2599 let Inst{19-16} = addr; 2600 let Inst{11-0} = offset{11-0}; 2601 2602 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2603 } 2604} 2605 2606let mayStore = 1, neverHasSideEffects = 1 in { 2607// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2608// IIC_iStore_siu depending on whether it the offset register is shifted. 2609defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2610defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2611} 2612 2613def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2614 am2offset_reg:$offset), 2615 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2616 am2offset_reg:$offset)>; 2617def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2618 am2offset_imm:$offset), 2619 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2620 am2offset_imm:$offset)>; 2621def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2622 am2offset_reg:$offset), 2623 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2624 am2offset_reg:$offset)>; 2625def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2626 am2offset_imm:$offset), 2627 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2628 am2offset_imm:$offset)>; 2629 2630// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2631// put the patterns on the instruction definitions directly as ISel wants 2632// the address base and offset to be separate operands, not a single 2633// complex operand like we represent the instructions themselves. The 2634// pseudos map between the two. 2635let usesCustomInserter = 1, 2636 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2637def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2638 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2639 4, IIC_iStore_ru, 2640 [(set GPR:$Rn_wb, 2641 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2642def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2643 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2644 4, IIC_iStore_ru, 2645 [(set GPR:$Rn_wb, 2646 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2647def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2648 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2649 4, IIC_iStore_ru, 2650 [(set GPR:$Rn_wb, 2651 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2652def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2653 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2654 4, IIC_iStore_ru, 2655 [(set GPR:$Rn_wb, 2656 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2657def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2658 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2659 4, IIC_iStore_ru, 2660 [(set GPR:$Rn_wb, 2661 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2662} 2663 2664 2665 2666def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2667 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 2668 StMiscFrm, IIC_iStore_bh_ru, 2669 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2670 bits<14> addr; 2671 let Inst{23} = addr{8}; // U bit 2672 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2673 let Inst{19-16} = addr{12-9}; // Rn 2674 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2675 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2676 let DecoderMethod = "DecodeAddrMode3Instruction"; 2677} 2678 2679def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2680 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2681 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2682 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2683 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2684 addr_offset_none:$addr, 2685 am3offset:$offset))]> { 2686 bits<10> offset; 2687 bits<4> addr; 2688 let Inst{23} = offset{8}; // U bit 2689 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2690 let Inst{19-16} = addr; 2691 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2692 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2693 let DecoderMethod = "DecodeAddrMode3Instruction"; 2694} 2695 2696let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2697def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2698 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 2699 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2700 "strd", "\t$Rt, $Rt2, $addr!", 2701 "$addr.base = $Rn_wb", []> { 2702 bits<14> addr; 2703 let Inst{23} = addr{8}; // U bit 2704 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2705 let Inst{19-16} = addr{12-9}; // Rn 2706 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2707 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2708 let DecoderMethod = "DecodeAddrMode3Instruction"; 2709} 2710 2711def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2712 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2713 am3offset:$offset), 2714 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2715 "strd", "\t$Rt, $Rt2, $addr, $offset", 2716 "$addr.base = $Rn_wb", []> { 2717 bits<10> offset; 2718 bits<4> addr; 2719 let Inst{23} = offset{8}; // U bit 2720 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2721 let Inst{19-16} = addr; 2722 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2723 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2724 let DecoderMethod = "DecodeAddrMode3Instruction"; 2725} 2726} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2727 2728// STRT, STRBT, and STRHT 2729 2730def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2731 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2732 IndexModePost, StFrm, IIC_iStore_bh_ru, 2733 "strbt", "\t$Rt, $addr, $offset", 2734 "$addr.base = $Rn_wb", []> { 2735 // {12} isAdd 2736 // {11-0} imm12/Rm 2737 bits<14> offset; 2738 bits<4> addr; 2739 let Inst{25} = 1; 2740 let Inst{23} = offset{12}; 2741 let Inst{21} = 1; // overwrite 2742 let Inst{19-16} = addr; 2743 let Inst{11-5} = offset{11-5}; 2744 let Inst{4} = 0; 2745 let Inst{3-0} = offset{3-0}; 2746 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2747} 2748 2749def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2750 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2751 IndexModePost, StFrm, IIC_iStore_bh_ru, 2752 "strbt", "\t$Rt, $addr, $offset", 2753 "$addr.base = $Rn_wb", []> { 2754 // {12} isAdd 2755 // {11-0} imm12/Rm 2756 bits<14> offset; 2757 bits<4> addr; 2758 let Inst{25} = 0; 2759 let Inst{23} = offset{12}; 2760 let Inst{21} = 1; // overwrite 2761 let Inst{19-16} = addr; 2762 let Inst{11-0} = offset{11-0}; 2763 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2764} 2765 2766let mayStore = 1, neverHasSideEffects = 1 in { 2767def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2768 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2769 IndexModePost, StFrm, IIC_iStore_ru, 2770 "strt", "\t$Rt, $addr, $offset", 2771 "$addr.base = $Rn_wb", []> { 2772 // {12} isAdd 2773 // {11-0} imm12/Rm 2774 bits<14> offset; 2775 bits<4> addr; 2776 let Inst{25} = 1; 2777 let Inst{23} = offset{12}; 2778 let Inst{21} = 1; // overwrite 2779 let Inst{19-16} = addr; 2780 let Inst{11-5} = offset{11-5}; 2781 let Inst{4} = 0; 2782 let Inst{3-0} = offset{3-0}; 2783 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2784} 2785 2786def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2787 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2788 IndexModePost, StFrm, IIC_iStore_ru, 2789 "strt", "\t$Rt, $addr, $offset", 2790 "$addr.base = $Rn_wb", []> { 2791 // {12} isAdd 2792 // {11-0} imm12/Rm 2793 bits<14> offset; 2794 bits<4> addr; 2795 let Inst{25} = 0; 2796 let Inst{23} = offset{12}; 2797 let Inst{21} = 1; // overwrite 2798 let Inst{19-16} = addr; 2799 let Inst{11-0} = offset{11-0}; 2800 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2801} 2802} 2803 2804 2805multiclass AI3strT<bits<4> op, string opc> { 2806 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2807 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2808 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2809 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2810 bits<9> offset; 2811 let Inst{23} = offset{8}; 2812 let Inst{22} = 1; 2813 let Inst{11-8} = offset{7-4}; 2814 let Inst{3-0} = offset{3-0}; 2815 } 2816 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2817 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2818 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2819 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2820 bits<5> Rm; 2821 let Inst{23} = Rm{4}; 2822 let Inst{22} = 0; 2823 let Inst{11-8} = 0; 2824 let Inst{3-0} = Rm{3-0}; 2825 } 2826} 2827 2828 2829defm STRHT : AI3strT<0b1011, "strht">; 2830 2831def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2832 NoItinerary, "stl", "\t$Rt, $addr", []>; 2833def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2834 NoItinerary, "stlb", "\t$Rt, $addr", []>; 2835def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 2836 NoItinerary, "stlh", "\t$Rt, $addr", []>; 2837 2838//===----------------------------------------------------------------------===// 2839// Load / store multiple Instructions. 2840// 2841 2842multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 2843 InstrItinClass itin, InstrItinClass itin_upd> { 2844 // IA is the default, so no need for an explicit suffix on the 2845 // mnemonic here. Without it is the canonical spelling. 2846 def IA : 2847 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2848 IndexModeNone, f, itin, 2849 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 2850 let Inst{24-23} = 0b01; // Increment After 2851 let Inst{22} = P_bit; 2852 let Inst{21} = 0; // No writeback 2853 let Inst{20} = L_bit; 2854 } 2855 def IA_UPD : 2856 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2857 IndexModeUpd, f, itin_upd, 2858 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2859 let Inst{24-23} = 0b01; // Increment After 2860 let Inst{22} = P_bit; 2861 let Inst{21} = 1; // Writeback 2862 let Inst{20} = L_bit; 2863 2864 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2865 } 2866 def DA : 2867 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2868 IndexModeNone, f, itin, 2869 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 2870 let Inst{24-23} = 0b00; // Decrement After 2871 let Inst{22} = P_bit; 2872 let Inst{21} = 0; // No writeback 2873 let Inst{20} = L_bit; 2874 } 2875 def DA_UPD : 2876 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2877 IndexModeUpd, f, itin_upd, 2878 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2879 let Inst{24-23} = 0b00; // Decrement After 2880 let Inst{22} = P_bit; 2881 let Inst{21} = 1; // Writeback 2882 let Inst{20} = L_bit; 2883 2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2885 } 2886 def DB : 2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2888 IndexModeNone, f, itin, 2889 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 2890 let Inst{24-23} = 0b10; // Decrement Before 2891 let Inst{22} = P_bit; 2892 let Inst{21} = 0; // No writeback 2893 let Inst{20} = L_bit; 2894 } 2895 def DB_UPD : 2896 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2897 IndexModeUpd, f, itin_upd, 2898 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2899 let Inst{24-23} = 0b10; // Decrement Before 2900 let Inst{22} = P_bit; 2901 let Inst{21} = 1; // Writeback 2902 let Inst{20} = L_bit; 2903 2904 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2905 } 2906 def IB : 2907 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2908 IndexModeNone, f, itin, 2909 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 2910 let Inst{24-23} = 0b11; // Increment Before 2911 let Inst{22} = P_bit; 2912 let Inst{21} = 0; // No writeback 2913 let Inst{20} = L_bit; 2914 } 2915 def IB_UPD : 2916 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2917 IndexModeUpd, f, itin_upd, 2918 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2919 let Inst{24-23} = 0b11; // Increment Before 2920 let Inst{22} = P_bit; 2921 let Inst{21} = 1; // Writeback 2922 let Inst{20} = L_bit; 2923 2924 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2925 } 2926} 2927 2928let neverHasSideEffects = 1 in { 2929 2930let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2931defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 2932 IIC_iLoad_mu>; 2933 2934let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2935defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 2936 IIC_iStore_mu>; 2937 2938} // neverHasSideEffects 2939 2940// FIXME: remove when we have a way to marking a MI with these properties. 2941// FIXME: Should pc be an implicit operand like PICADD, etc? 2942let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2943 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 2944def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 2945 reglist:$regs, variable_ops), 2946 4, IIC_iLoad_mBr, [], 2947 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 2948 RegConstraint<"$Rn = $wb">; 2949 2950let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2951defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 2952 IIC_iLoad_mu>; 2953 2954let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2955defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 2956 IIC_iStore_mu>; 2957 2958 2959 2960//===----------------------------------------------------------------------===// 2961// Move Instructions. 2962// 2963 2964let neverHasSideEffects = 1 in 2965def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 2966 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 2967 bits<4> Rd; 2968 bits<4> Rm; 2969 2970 let Inst{19-16} = 0b0000; 2971 let Inst{11-4} = 0b00000000; 2972 let Inst{25} = 0; 2973 let Inst{3-0} = Rm; 2974 let Inst{15-12} = Rd; 2975} 2976 2977// A version for the smaller set of tail call registers. 2978let neverHasSideEffects = 1 in 2979def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 2980 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 2981 bits<4> Rd; 2982 bits<4> Rm; 2983 2984 let Inst{11-4} = 0b00000000; 2985 let Inst{25} = 0; 2986 let Inst{3-0} = Rm; 2987 let Inst{15-12} = Rd; 2988} 2989 2990def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 2991 DPSoRegRegFrm, IIC_iMOVsr, 2992 "mov", "\t$Rd, $src", 2993 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 2994 Sched<[WriteALU]> { 2995 bits<4> Rd; 2996 bits<12> src; 2997 let Inst{15-12} = Rd; 2998 let Inst{19-16} = 0b0000; 2999 let Inst{11-8} = src{11-8}; 3000 let Inst{7} = 0; 3001 let Inst{6-5} = src{6-5}; 3002 let Inst{4} = 1; 3003 let Inst{3-0} = src{3-0}; 3004 let Inst{25} = 0; 3005} 3006 3007def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3008 DPSoRegImmFrm, IIC_iMOVsr, 3009 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3010 UnaryDP, Sched<[WriteALU]> { 3011 bits<4> Rd; 3012 bits<12> src; 3013 let Inst{15-12} = Rd; 3014 let Inst{19-16} = 0b0000; 3015 let Inst{11-5} = src{11-5}; 3016 let Inst{4} = 0; 3017 let Inst{3-0} = src{3-0}; 3018 let Inst{25} = 0; 3019} 3020 3021let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3022def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 3023 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP, 3024 Sched<[WriteALU]> { 3025 bits<4> Rd; 3026 bits<12> imm; 3027 let Inst{25} = 1; 3028 let Inst{15-12} = Rd; 3029 let Inst{19-16} = 0b0000; 3030 let Inst{11-0} = imm; 3031} 3032 3033let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3034def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3035 DPFrm, IIC_iMOVi, 3036 "movw", "\t$Rd, $imm", 3037 [(set GPR:$Rd, imm0_65535:$imm)]>, 3038 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3039 bits<4> Rd; 3040 bits<16> imm; 3041 let Inst{15-12} = Rd; 3042 let Inst{11-0} = imm{11-0}; 3043 let Inst{19-16} = imm{15-12}; 3044 let Inst{20} = 0; 3045 let Inst{25} = 1; 3046 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3047} 3048 3049def : InstAlias<"mov${p} $Rd, $imm", 3050 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 3051 Requires<[IsARM]>; 3052 3053def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3054 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3055 Sched<[WriteALU]>; 3056 3057let Constraints = "$src = $Rd" in { 3058def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3059 (ins GPR:$src, imm0_65535_expr:$imm), 3060 DPFrm, IIC_iMOVi, 3061 "movt", "\t$Rd, $imm", 3062 [(set GPRnopc:$Rd, 3063 (or (and GPR:$src, 0xffff), 3064 lo16AllZero:$imm))]>, UnaryDP, 3065 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3066 bits<4> Rd; 3067 bits<16> imm; 3068 let Inst{15-12} = Rd; 3069 let Inst{11-0} = imm{11-0}; 3070 let Inst{19-16} = imm{15-12}; 3071 let Inst{20} = 0; 3072 let Inst{25} = 1; 3073 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3074} 3075 3076def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3077 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3078 Sched<[WriteALU]>; 3079 3080} // Constraints 3081 3082def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3083 Requires<[IsARM, HasV6T2]>; 3084 3085let Uses = [CPSR] in 3086def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3087 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3088 Requires<[IsARM]>, Sched<[WriteALU]>; 3089 3090// These aren't really mov instructions, but we have to define them this way 3091// due to flag operands. 3092 3093let Defs = [CPSR] in { 3094def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3095 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3096 Sched<[WriteALU]>, Requires<[IsARM]>; 3097def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3098 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3099 Sched<[WriteALU]>, Requires<[IsARM]>; 3100} 3101 3102//===----------------------------------------------------------------------===// 3103// Extend Instructions. 3104// 3105 3106// Sign extenders 3107 3108def SXTB : AI_ext_rrot<0b01101010, 3109 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3110def SXTH : AI_ext_rrot<0b01101011, 3111 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3112 3113def SXTAB : AI_exta_rrot<0b01101010, 3114 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3115def SXTAH : AI_exta_rrot<0b01101011, 3116 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3117 3118def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3119 3120def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3121 3122// Zero extenders 3123 3124let AddedComplexity = 16 in { 3125def UXTB : AI_ext_rrot<0b01101110, 3126 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3127def UXTH : AI_ext_rrot<0b01101111, 3128 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3129def UXTB16 : AI_ext_rrot<0b01101100, 3130 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3131 3132// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3133// The transformation should probably be done as a combiner action 3134// instead so we can include a check for masking back in the upper 3135// eight bits of the source into the lower eight bits of the result. 3136//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3137// (UXTB16r_rot GPR:$Src, 3)>; 3138def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3139 (UXTB16 GPR:$Src, 1)>; 3140 3141def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3142 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3143def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3144 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3145} 3146 3147// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3148def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3149 3150 3151def SBFX : I<(outs GPRnopc:$Rd), 3152 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3153 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3154 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3155 Requires<[IsARM, HasV6T2]> { 3156 bits<4> Rd; 3157 bits<4> Rn; 3158 bits<5> lsb; 3159 bits<5> width; 3160 let Inst{27-21} = 0b0111101; 3161 let Inst{6-4} = 0b101; 3162 let Inst{20-16} = width; 3163 let Inst{15-12} = Rd; 3164 let Inst{11-7} = lsb; 3165 let Inst{3-0} = Rn; 3166} 3167 3168def UBFX : I<(outs GPR:$Rd), 3169 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), 3170 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3171 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3172 Requires<[IsARM, HasV6T2]> { 3173 bits<4> Rd; 3174 bits<4> Rn; 3175 bits<5> lsb; 3176 bits<5> width; 3177 let Inst{27-21} = 0b0111111; 3178 let Inst{6-4} = 0b101; 3179 let Inst{20-16} = width; 3180 let Inst{15-12} = Rd; 3181 let Inst{11-7} = lsb; 3182 let Inst{3-0} = Rn; 3183} 3184 3185//===----------------------------------------------------------------------===// 3186// Arithmetic Instructions. 3187// 3188 3189defm ADD : AsI1_bin_irs<0b0100, "add", 3190 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3191 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 3192defm SUB : AsI1_bin_irs<0b0010, "sub", 3193 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3194 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3195 3196// ADD and SUB with 's' bit set. 3197// 3198// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3199// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3200// AdjustInstrPostInstrSelection where we determine whether or not to 3201// set the "s" bit based on CPSR liveness. 3202// 3203// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3204// support for an optional CPSR definition that corresponds to the DAG 3205// node's second value. We can then eliminate the implicit def of CPSR. 3206defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3207 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3208defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3209 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3210 3211defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3212 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 3213defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3214 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3215 3216defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3217 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3218 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 3219 3220// FIXME: Eliminate them if we can write def : Pat patterns which defines 3221// CPSR and the implicit def of CPSR is not needed. 3222defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3223 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3224 3225defm RSC : AI1_rsc_irs<0b0111, "rsc", 3226 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 3227 3228// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3229// The assume-no-carry-in form uses the negation of the input since add/sub 3230// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3231// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3232// details. 3233def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3234 (SUBri GPR:$src, so_imm_neg:$imm)>; 3235def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3236 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3237 3238def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3239 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3240 Requires<[IsARM, HasV6T2]>; 3241def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3242 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3243 Requires<[IsARM, HasV6T2]>; 3244 3245// The with-carry-in form matches bitwise not instead of the negation. 3246// Effectively, the inverse interpretation of the carry flag already accounts 3247// for part of the negation. 3248def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3249 (SBCri GPR:$src, so_imm_not:$imm)>; 3250def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3251 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>; 3252 3253// Note: These are implemented in C++ code, because they have to generate 3254// ADD/SUBrs instructions, which use a complex pattern that a xform function 3255// cannot produce. 3256// (mul X, 2^n+1) -> (add (X << n), X) 3257// (mul X, 2^n-1) -> (rsb X, (X << n)) 3258 3259// ARM Arithmetic Instruction 3260// GPR:$dst = GPR:$a op GPR:$b 3261class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3262 list<dag> pattern = [], 3263 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3264 string asm = "\t$Rd, $Rn, $Rm"> 3265 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3266 Sched<[WriteALU, ReadALU, ReadALU]> { 3267 bits<4> Rn; 3268 bits<4> Rd; 3269 bits<4> Rm; 3270 let Inst{27-20} = op27_20; 3271 let Inst{11-4} = op11_4; 3272 let Inst{19-16} = Rn; 3273 let Inst{15-12} = Rd; 3274 let Inst{3-0} = Rm; 3275 3276 let Unpredictable{11-8} = 0b1111; 3277} 3278 3279// Saturating add/subtract 3280 3281let DecoderMethod = "DecodeQADDInstruction" in 3282def QADD : AAI<0b00010000, 0b00000101, "qadd", 3283 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3284 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3285 3286def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3287 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3288 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3289def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3290 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3291 "\t$Rd, $Rm, $Rn">; 3292def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3293 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3294 "\t$Rd, $Rm, $Rn">; 3295 3296def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3297def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3298def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3299def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3300def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3301def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3302def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3303def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3304def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3305def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3306def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3307def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3308 3309// Signed/Unsigned add/subtract 3310 3311def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3312def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3313def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3314def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3315def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3316def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3317def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3318def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3319def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3320def USAX : AAI<0b01100101, 0b11110101, "usax">; 3321def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3322def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3323 3324// Signed/Unsigned halving add/subtract 3325 3326def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3327def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3328def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3329def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3330def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3331def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3332def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3333def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3334def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3335def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3336def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3337def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3338 3339// Unsigned Sum of Absolute Differences [and Accumulate]. 3340 3341def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3342 MulFrm /* for convenience */, NoItinerary, "usad8", 3343 "\t$Rd, $Rn, $Rm", []>, 3344 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3345 bits<4> Rd; 3346 bits<4> Rn; 3347 bits<4> Rm; 3348 let Inst{27-20} = 0b01111000; 3349 let Inst{15-12} = 0b1111; 3350 let Inst{7-4} = 0b0001; 3351 let Inst{19-16} = Rd; 3352 let Inst{11-8} = Rm; 3353 let Inst{3-0} = Rn; 3354} 3355def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3356 MulFrm /* for convenience */, NoItinerary, "usada8", 3357 "\t$Rd, $Rn, $Rm, $Ra", []>, 3358 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3359 bits<4> Rd; 3360 bits<4> Rn; 3361 bits<4> Rm; 3362 bits<4> Ra; 3363 let Inst{27-20} = 0b01111000; 3364 let Inst{7-4} = 0b0001; 3365 let Inst{19-16} = Rd; 3366 let Inst{15-12} = Ra; 3367 let Inst{11-8} = Rm; 3368 let Inst{3-0} = Rn; 3369} 3370 3371// Signed/Unsigned saturate 3372 3373def SSAT : AI<(outs GPRnopc:$Rd), 3374 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3375 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3376 bits<4> Rd; 3377 bits<5> sat_imm; 3378 bits<4> Rn; 3379 bits<8> sh; 3380 let Inst{27-21} = 0b0110101; 3381 let Inst{5-4} = 0b01; 3382 let Inst{20-16} = sat_imm; 3383 let Inst{15-12} = Rd; 3384 let Inst{11-7} = sh{4-0}; 3385 let Inst{6} = sh{5}; 3386 let Inst{3-0} = Rn; 3387} 3388 3389def SSAT16 : AI<(outs GPRnopc:$Rd), 3390 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3391 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3392 bits<4> Rd; 3393 bits<4> sat_imm; 3394 bits<4> Rn; 3395 let Inst{27-20} = 0b01101010; 3396 let Inst{11-4} = 0b11110011; 3397 let Inst{15-12} = Rd; 3398 let Inst{19-16} = sat_imm; 3399 let Inst{3-0} = Rn; 3400} 3401 3402def USAT : AI<(outs GPRnopc:$Rd), 3403 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3404 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3405 bits<4> Rd; 3406 bits<5> sat_imm; 3407 bits<4> Rn; 3408 bits<8> sh; 3409 let Inst{27-21} = 0b0110111; 3410 let Inst{5-4} = 0b01; 3411 let Inst{15-12} = Rd; 3412 let Inst{11-7} = sh{4-0}; 3413 let Inst{6} = sh{5}; 3414 let Inst{20-16} = sat_imm; 3415 let Inst{3-0} = Rn; 3416} 3417 3418def USAT16 : AI<(outs GPRnopc:$Rd), 3419 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3420 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3421 bits<4> Rd; 3422 bits<4> sat_imm; 3423 bits<4> Rn; 3424 let Inst{27-20} = 0b01101110; 3425 let Inst{11-4} = 0b11110011; 3426 let Inst{15-12} = Rd; 3427 let Inst{19-16} = sat_imm; 3428 let Inst{3-0} = Rn; 3429} 3430 3431def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3432 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3433def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3434 (USAT imm:$pos, GPRnopc:$a, 0)>; 3435 3436//===----------------------------------------------------------------------===// 3437// Bitwise Instructions. 3438// 3439 3440defm AND : AsI1_bin_irs<0b0000, "and", 3441 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3442 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 3443defm ORR : AsI1_bin_irs<0b1100, "orr", 3444 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3445 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 3446defm EOR : AsI1_bin_irs<0b0001, "eor", 3447 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3448 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 3449defm BIC : AsI1_bin_irs<0b1110, "bic", 3450 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3451 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3452 3453// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3454// like in the actual instruction encoding. The complexity of mapping the mask 3455// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3456// instruction description. 3457def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3458 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3459 "bfc", "\t$Rd, $imm", "$src = $Rd", 3460 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3461 Requires<[IsARM, HasV6T2]> { 3462 bits<4> Rd; 3463 bits<10> imm; 3464 let Inst{27-21} = 0b0111110; 3465 let Inst{6-0} = 0b0011111; 3466 let Inst{15-12} = Rd; 3467 let Inst{11-7} = imm{4-0}; // lsb 3468 let Inst{20-16} = imm{9-5}; // msb 3469} 3470 3471// A8.6.18 BFI - Bitfield insert (Encoding A1) 3472def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3473 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3474 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3475 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3476 bf_inv_mask_imm:$imm))]>, 3477 Requires<[IsARM, HasV6T2]> { 3478 bits<4> Rd; 3479 bits<4> Rn; 3480 bits<10> imm; 3481 let Inst{27-21} = 0b0111110; 3482 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3483 let Inst{15-12} = Rd; 3484 let Inst{11-7} = imm{4-0}; // lsb 3485 let Inst{20-16} = imm{9-5}; // width 3486 let Inst{3-0} = Rn; 3487} 3488 3489def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3490 "mvn", "\t$Rd, $Rm", 3491 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3492 bits<4> Rd; 3493 bits<4> Rm; 3494 let Inst{25} = 0; 3495 let Inst{19-16} = 0b0000; 3496 let Inst{11-4} = 0b00000000; 3497 let Inst{15-12} = Rd; 3498 let Inst{3-0} = Rm; 3499} 3500def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3501 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3502 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3503 Sched<[WriteALU]> { 3504 bits<4> Rd; 3505 bits<12> shift; 3506 let Inst{25} = 0; 3507 let Inst{19-16} = 0b0000; 3508 let Inst{15-12} = Rd; 3509 let Inst{11-5} = shift{11-5}; 3510 let Inst{4} = 0; 3511 let Inst{3-0} = shift{3-0}; 3512} 3513def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3514 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3515 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3516 Sched<[WriteALU]> { 3517 bits<4> Rd; 3518 bits<12> shift; 3519 let Inst{25} = 0; 3520 let Inst{19-16} = 0b0000; 3521 let Inst{15-12} = Rd; 3522 let Inst{11-8} = shift{11-8}; 3523 let Inst{7} = 0; 3524 let Inst{6-5} = shift{6-5}; 3525 let Inst{4} = 1; 3526 let Inst{3-0} = shift{3-0}; 3527} 3528let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3529def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3530 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3531 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 3532 bits<4> Rd; 3533 bits<12> imm; 3534 let Inst{25} = 1; 3535 let Inst{19-16} = 0b0000; 3536 let Inst{15-12} = Rd; 3537 let Inst{11-0} = imm; 3538} 3539 3540def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3541 (BICri GPR:$src, so_imm_not:$imm)>; 3542 3543//===----------------------------------------------------------------------===// 3544// Multiply Instructions. 3545// 3546class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3547 string opc, string asm, list<dag> pattern> 3548 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3549 bits<4> Rd; 3550 bits<4> Rm; 3551 bits<4> Rn; 3552 let Inst{19-16} = Rd; 3553 let Inst{11-8} = Rm; 3554 let Inst{3-0} = Rn; 3555} 3556class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3557 string opc, string asm, list<dag> pattern> 3558 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3559 bits<4> RdLo; 3560 bits<4> RdHi; 3561 bits<4> Rm; 3562 bits<4> Rn; 3563 let Inst{19-16} = RdHi; 3564 let Inst{15-12} = RdLo; 3565 let Inst{11-8} = Rm; 3566 let Inst{3-0} = Rn; 3567} 3568class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3569 string opc, string asm, list<dag> pattern> 3570 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3571 bits<4> RdLo; 3572 bits<4> RdHi; 3573 bits<4> Rm; 3574 bits<4> Rn; 3575 let Inst{19-16} = RdHi; 3576 let Inst{15-12} = RdLo; 3577 let Inst{11-8} = Rm; 3578 let Inst{3-0} = Rn; 3579} 3580 3581// FIXME: The v5 pseudos are only necessary for the additional Constraint 3582// property. Remove them when it's possible to add those properties 3583// on an individual MachineInstr, not just an instruction description. 3584let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 3585def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 3586 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3587 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3588 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3589 Requires<[IsARM, HasV6]> { 3590 let Inst{15-12} = 0b0000; 3591 let Unpredictable{15-12} = 0b1111; 3592} 3593 3594let Constraints = "@earlyclobber $Rd" in 3595def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3596 pred:$p, cc_out:$s), 3597 4, IIC_iMUL32, 3598 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3599 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3600 Requires<[IsARM, NoV6, UseMulOps]>; 3601} 3602 3603def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3604 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3605 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3606 Requires<[IsARM, HasV6, UseMulOps]> { 3607 bits<4> Ra; 3608 let Inst{15-12} = Ra; 3609} 3610 3611let Constraints = "@earlyclobber $Rd" in 3612def MLAv5: ARMPseudoExpand<(outs GPR:$Rd), 3613 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), 3614 4, IIC_iMAC32, 3615 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))], 3616 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>, 3617 Requires<[IsARM, NoV6]>; 3618 3619def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3620 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3621 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3622 Requires<[IsARM, HasV6T2, UseMulOps]> { 3623 bits<4> Rd; 3624 bits<4> Rm; 3625 bits<4> Rn; 3626 bits<4> Ra; 3627 let Inst{19-16} = Rd; 3628 let Inst{15-12} = Ra; 3629 let Inst{11-8} = Rm; 3630 let Inst{3-0} = Rn; 3631} 3632 3633// Extra precision multiplies with low / high results 3634let neverHasSideEffects = 1 in { 3635let isCommutable = 1 in { 3636def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3637 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3638 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3639 Requires<[IsARM, HasV6]>; 3640 3641def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3642 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3643 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3644 Requires<[IsARM, HasV6]>; 3645 3646let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3647def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3648 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3649 4, IIC_iMUL64, [], 3650 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3651 Requires<[IsARM, NoV6]>; 3652 3653def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3654 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3655 4, IIC_iMUL64, [], 3656 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3657 Requires<[IsARM, NoV6]>; 3658} 3659} 3660 3661// Multiply + accumulate 3662def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3663 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3664 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3665 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3666def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3667 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 3668 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3669 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>; 3670 3671def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3672 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3673 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3674 Requires<[IsARM, HasV6]> { 3675 bits<4> RdLo; 3676 bits<4> RdHi; 3677 bits<4> Rm; 3678 bits<4> Rn; 3679 let Inst{19-16} = RdHi; 3680 let Inst{15-12} = RdLo; 3681 let Inst{11-8} = Rm; 3682 let Inst{3-0} = Rn; 3683} 3684 3685let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in { 3686def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3687 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3688 4, IIC_iMAC64, [], 3689 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3690 pred:$p, cc_out:$s)>, 3691 Requires<[IsARM, NoV6]>; 3692def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3693 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 3694 4, IIC_iMAC64, [], 3695 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 3696 pred:$p, cc_out:$s)>, 3697 Requires<[IsARM, NoV6]>; 3698} 3699 3700let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3701def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3702 (ins GPR:$Rn, GPR:$Rm, pred:$p), 3703 4, IIC_iMAC64, [], 3704 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>, 3705 Requires<[IsARM, NoV6]>; 3706} 3707 3708} // neverHasSideEffects 3709 3710// Most significant word multiply 3711def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3712 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3713 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3714 Requires<[IsARM, HasV6]> { 3715 let Inst{15-12} = 0b1111; 3716} 3717 3718def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3719 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3720 Requires<[IsARM, HasV6]> { 3721 let Inst{15-12} = 0b1111; 3722} 3723 3724def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3725 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3726 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3727 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3728 Requires<[IsARM, HasV6, UseMulOps]>; 3729 3730def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3731 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3732 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3733 Requires<[IsARM, HasV6]>; 3734 3735def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3736 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3737 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 3738 Requires<[IsARM, HasV6, UseMulOps]>; 3739 3740def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3741 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3742 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3743 Requires<[IsARM, HasV6]>; 3744 3745multiclass AI_smul<string opc, PatFrag opnode> { 3746 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3747 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3748 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3749 (sext_inreg GPR:$Rm, i16)))]>, 3750 Requires<[IsARM, HasV5TE]>; 3751 3752 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3753 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3754 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3755 (sra GPR:$Rm, (i32 16))))]>, 3756 Requires<[IsARM, HasV5TE]>; 3757 3758 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3759 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3760 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3761 (sext_inreg GPR:$Rm, i16)))]>, 3762 Requires<[IsARM, HasV5TE]>; 3763 3764 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3765 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3766 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3767 (sra GPR:$Rm, (i32 16))))]>, 3768 Requires<[IsARM, HasV5TE]>; 3769 3770 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3771 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3772 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3773 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3774 Requires<[IsARM, HasV5TE]>; 3775 3776 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3777 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3778 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3779 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3780 Requires<[IsARM, HasV5TE]>; 3781} 3782 3783 3784multiclass AI_smla<string opc, PatFrag opnode> { 3785 let DecoderMethod = "DecodeSMLAInstruction" in { 3786 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3787 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3788 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3789 [(set GPRnopc:$Rd, (add GPR:$Ra, 3790 (opnode (sext_inreg GPRnopc:$Rn, i16), 3791 (sext_inreg GPRnopc:$Rm, i16))))]>, 3792 Requires<[IsARM, HasV5TE, UseMulOps]>; 3793 3794 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3795 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3796 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3797 [(set GPRnopc:$Rd, 3798 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3799 (sra GPRnopc:$Rm, (i32 16)))))]>, 3800 Requires<[IsARM, HasV5TE, UseMulOps]>; 3801 3802 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3803 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3804 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3805 [(set GPRnopc:$Rd, 3806 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3807 (sext_inreg GPRnopc:$Rm, i16))))]>, 3808 Requires<[IsARM, HasV5TE, UseMulOps]>; 3809 3810 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3811 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3812 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3813 [(set GPRnopc:$Rd, 3814 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3815 (sra GPRnopc:$Rm, (i32 16)))))]>, 3816 Requires<[IsARM, HasV5TE, UseMulOps]>; 3817 3818 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3819 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3820 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3821 [(set GPRnopc:$Rd, 3822 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3823 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3824 Requires<[IsARM, HasV5TE, UseMulOps]>; 3825 3826 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3827 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3828 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3829 [(set GPRnopc:$Rd, 3830 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3831 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3832 Requires<[IsARM, HasV5TE, UseMulOps]>; 3833 } 3834} 3835 3836defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3837defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3838 3839// Halfword multiply accumulate long: SMLAL<x><y>. 3840def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3841 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3842 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3843 Requires<[IsARM, HasV5TE]>; 3844 3845def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3846 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3847 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3848 Requires<[IsARM, HasV5TE]>; 3849 3850def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3851 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3852 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3853 Requires<[IsARM, HasV5TE]>; 3854 3855def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3856 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3857 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3858 Requires<[IsARM, HasV5TE]>; 3859 3860// Helper class for AI_smld. 3861class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 3862 InstrItinClass itin, string opc, string asm> 3863 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 3864 bits<4> Rn; 3865 bits<4> Rm; 3866 let Inst{27-23} = 0b01110; 3867 let Inst{22} = long; 3868 let Inst{21-20} = 0b00; 3869 let Inst{11-8} = Rm; 3870 let Inst{7} = 0; 3871 let Inst{6} = sub; 3872 let Inst{5} = swap; 3873 let Inst{4} = 1; 3874 let Inst{3-0} = Rn; 3875} 3876class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 3877 InstrItinClass itin, string opc, string asm> 3878 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3879 bits<4> Rd; 3880 let Inst{15-12} = 0b1111; 3881 let Inst{19-16} = Rd; 3882} 3883class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 3884 InstrItinClass itin, string opc, string asm> 3885 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3886 bits<4> Ra; 3887 bits<4> Rd; 3888 let Inst{19-16} = Rd; 3889 let Inst{15-12} = Ra; 3890} 3891class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 3892 InstrItinClass itin, string opc, string asm> 3893 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3894 bits<4> RdLo; 3895 bits<4> RdHi; 3896 let Inst{19-16} = RdHi; 3897 let Inst{15-12} = RdLo; 3898} 3899 3900multiclass AI_smld<bit sub, string opc> { 3901 3902 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 3903 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3904 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 3905 3906 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 3907 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3908 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 3909 3910 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3911 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3912 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 3913 3914 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3915 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3916 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 3917 3918} 3919 3920defm SMLA : AI_smld<0, "smla">; 3921defm SMLS : AI_smld<1, "smls">; 3922 3923multiclass AI_sdml<bit sub, string opc> { 3924 3925 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 3926 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 3927 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 3928 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 3929} 3930 3931defm SMUA : AI_sdml<0, "smua">; 3932defm SMUS : AI_sdml<1, "smus">; 3933 3934//===----------------------------------------------------------------------===// 3935// Division Instructions (ARMv7-A with virtualization extension) 3936// 3937def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3938 "sdiv", "\t$Rd, $Rn, $Rm", 3939 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 3940 Requires<[IsARM, HasDivideInARM]>; 3941 3942def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 3943 "udiv", "\t$Rd, $Rn, $Rm", 3944 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 3945 Requires<[IsARM, HasDivideInARM]>; 3946 3947//===----------------------------------------------------------------------===// 3948// Misc. Arithmetic Instructions. 3949// 3950 3951def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 3952 IIC_iUNAr, "clz", "\t$Rd, $Rm", 3953 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 3954 Sched<[WriteALU]>; 3955 3956def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3957 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 3958 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 3959 Requires<[IsARM, HasV6T2]>, 3960 Sched<[WriteALU]>; 3961 3962def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3963 IIC_iUNAr, "rev", "\t$Rd, $Rm", 3964 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 3965 Sched<[WriteALU]>; 3966 3967let AddedComplexity = 5 in 3968def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3969 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 3970 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 3971 Requires<[IsARM, HasV6]>, 3972 Sched<[WriteALU]>; 3973 3974let AddedComplexity = 5 in 3975def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3976 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 3977 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 3978 Requires<[IsARM, HasV6]>, 3979 Sched<[WriteALU]>; 3980 3981def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 3982 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 3983 (REVSH GPR:$Rm)>; 3984 3985def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 3986 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 3987 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 3988 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 3989 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 3990 0xFFFF0000)))]>, 3991 Requires<[IsARM, HasV6]>, 3992 Sched<[WriteALUsi, ReadALU]>; 3993 3994// Alternate cases for PKHBT where identities eliminate some nodes. 3995def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 3996 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 3997def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 3998 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 3999 4000// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4001// will match the pattern below. 4002def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4003 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4004 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4005 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4006 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4007 0xFFFF)))]>, 4008 Requires<[IsARM, HasV6]>, 4009 Sched<[WriteALUsi, ReadALU]>; 4010 4011// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4012// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4013// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4014// pkhtb src1, src2, asr (17..31). 4015def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4016 (srl GPRnopc:$src2, imm16:$sh)), 4017 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4018def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4019 (sra GPRnopc:$src2, imm16_31:$sh)), 4020 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4021def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4022 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4023 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4024 4025//===----------------------------------------------------------------------===// 4026// CRC Instructions 4027// 4028// Polynomials: 4029// + CRC32{B,H,W} 0x04C11DB7 4030// + CRC32C{B,H,W} 0x1EDC6F41 4031// 4032 4033class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4034 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4035 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4036 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4037 Requires<[IsARM, HasV8, HasCRC]> { 4038 bits<4> Rd; 4039 bits<4> Rn; 4040 bits<4> Rm; 4041 4042 let Inst{31-28} = 0b1110; 4043 let Inst{27-23} = 0b00010; 4044 let Inst{22-21} = sz; 4045 let Inst{20} = 0; 4046 let Inst{19-16} = Rn; 4047 let Inst{15-12} = Rd; 4048 let Inst{11-10} = 0b00; 4049 let Inst{9} = C; 4050 let Inst{8} = 0; 4051 let Inst{7-4} = 0b0100; 4052 let Inst{3-0} = Rm; 4053 4054 let Unpredictable{11-8} = 0b1101; 4055} 4056 4057def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4058def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4059def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4060def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4061def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4062def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4063 4064//===----------------------------------------------------------------------===// 4065// Comparison Instructions... 4066// 4067 4068defm CMP : AI1_cmp_irs<0b1010, "cmp", 4069 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 4070 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 4071 4072// ARMcmpZ can re-use the above instruction definitions. 4073def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 4074 (CMPri GPR:$src, so_imm:$imm)>; 4075def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4076 (CMPrr GPR:$src, GPR:$rhs)>; 4077def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4078 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4079def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4080 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4081 4082// CMN register-integer 4083let isCompare = 1, Defs = [CPSR] in { 4084def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi, 4085 "cmn", "\t$Rn, $imm", 4086 [(ARMcmn GPR:$Rn, so_imm:$imm)]>, 4087 Sched<[WriteCMP, ReadALU]> { 4088 bits<4> Rn; 4089 bits<12> imm; 4090 let Inst{25} = 1; 4091 let Inst{20} = 1; 4092 let Inst{19-16} = Rn; 4093 let Inst{15-12} = 0b0000; 4094 let Inst{11-0} = imm; 4095 4096 let Unpredictable{15-12} = 0b1111; 4097} 4098 4099// CMN register-register/shift 4100def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4101 "cmn", "\t$Rn, $Rm", 4102 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4103 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4104 bits<4> Rn; 4105 bits<4> Rm; 4106 let isCommutable = 1; 4107 let Inst{25} = 0; 4108 let Inst{20} = 1; 4109 let Inst{19-16} = Rn; 4110 let Inst{15-12} = 0b0000; 4111 let Inst{11-4} = 0b00000000; 4112 let Inst{3-0} = Rm; 4113 4114 let Unpredictable{15-12} = 0b1111; 4115} 4116 4117def CMNzrsi : AI1<0b1011, (outs), 4118 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4119 "cmn", "\t$Rn, $shift", 4120 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4121 GPR:$Rn, so_reg_imm:$shift)]>, 4122 Sched<[WriteCMPsi, ReadALU]> { 4123 bits<4> Rn; 4124 bits<12> shift; 4125 let Inst{25} = 0; 4126 let Inst{20} = 1; 4127 let Inst{19-16} = Rn; 4128 let Inst{15-12} = 0b0000; 4129 let Inst{11-5} = shift{11-5}; 4130 let Inst{4} = 0; 4131 let Inst{3-0} = shift{3-0}; 4132 4133 let Unpredictable{15-12} = 0b1111; 4134} 4135 4136def CMNzrsr : AI1<0b1011, (outs), 4137 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4138 "cmn", "\t$Rn, $shift", 4139 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4140 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4141 Sched<[WriteCMPsr, ReadALU]> { 4142 bits<4> Rn; 4143 bits<12> shift; 4144 let Inst{25} = 0; 4145 let Inst{20} = 1; 4146 let Inst{19-16} = Rn; 4147 let Inst{15-12} = 0b0000; 4148 let Inst{11-8} = shift{11-8}; 4149 let Inst{7} = 0; 4150 let Inst{6-5} = shift{6-5}; 4151 let Inst{4} = 1; 4152 let Inst{3-0} = shift{3-0}; 4153 4154 let Unpredictable{15-12} = 0b1111; 4155} 4156 4157} 4158 4159def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 4160 (CMNri GPR:$src, so_imm_neg:$imm)>; 4161 4162def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 4163 (CMNri GPR:$src, so_imm_neg:$imm)>; 4164 4165// Note that TST/TEQ don't set all the same flags that CMP does! 4166defm TST : AI1_cmp_irs<0b1000, "tst", 4167 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4168 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 4169defm TEQ : AI1_cmp_irs<0b1001, "teq", 4170 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4171 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4172 4173// Pseudo i64 compares for some floating point compares. 4174let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4175 Defs = [CPSR] in { 4176def BCCi64 : PseudoInst<(outs), 4177 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4178 IIC_Br, 4179 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4180 Sched<[WriteBr]>; 4181 4182def BCCZi64 : PseudoInst<(outs), 4183 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4184 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4185 Sched<[WriteBr]>; 4186} // usesCustomInserter 4187 4188 4189// Conditional moves 4190let neverHasSideEffects = 1 in { 4191 4192let isCommutable = 1, isSelect = 1 in 4193def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4194 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4195 4, IIC_iCMOVr, 4196 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4197 cmovpred:$p))]>, 4198 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4199 4200def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4201 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4202 4, IIC_iCMOVsr, 4203 [(set GPR:$Rd, 4204 (ARMcmov GPR:$false, so_reg_imm:$shift, 4205 cmovpred:$p))]>, 4206 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4207def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4208 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4209 4, IIC_iCMOVsr, 4210 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4211 cmovpred:$p))]>, 4212 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4213 4214 4215let isMoveImm = 1 in 4216def MOVCCi16 4217 : ARMPseudoInst<(outs GPR:$Rd), 4218 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4219 4, IIC_iMOVi, 4220 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4221 cmovpred:$p))]>, 4222 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4223 Sched<[WriteALU]>; 4224 4225let isMoveImm = 1 in 4226def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4227 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4228 4, IIC_iCMOVi, 4229 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, 4230 cmovpred:$p))]>, 4231 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4232 4233// Two instruction predicate mov immediate. 4234let isMoveImm = 1 in 4235def MOVCCi32imm 4236 : ARMPseudoInst<(outs GPR:$Rd), 4237 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4238 8, IIC_iCMOVix2, 4239 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4240 cmovpred:$p))]>, 4241 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4242 4243let isMoveImm = 1 in 4244def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4245 (ins GPR:$false, so_imm:$imm, cmovpred:$p), 4246 4, IIC_iCMOVi, 4247 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, 4248 cmovpred:$p))]>, 4249 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4250 4251} // neverHasSideEffects 4252 4253 4254//===----------------------------------------------------------------------===// 4255// Atomic operations intrinsics 4256// 4257 4258def MemBarrierOptOperand : AsmOperandClass { 4259 let Name = "MemBarrierOpt"; 4260 let ParserMethod = "parseMemBarrierOptOperand"; 4261} 4262def memb_opt : Operand<i32> { 4263 let PrintMethod = "printMemBOption"; 4264 let ParserMatchClass = MemBarrierOptOperand; 4265 let DecoderMethod = "DecodeMemBarrierOption"; 4266} 4267 4268def InstSyncBarrierOptOperand : AsmOperandClass { 4269 let Name = "InstSyncBarrierOpt"; 4270 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4271} 4272def instsyncb_opt : Operand<i32> { 4273 let PrintMethod = "printInstSyncBOption"; 4274 let ParserMatchClass = InstSyncBarrierOptOperand; 4275 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4276} 4277 4278// memory barriers protect the atomic sequences 4279let hasSideEffects = 1 in { 4280def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4281 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4282 Requires<[IsARM, HasDB]> { 4283 bits<4> opt; 4284 let Inst{31-4} = 0xf57ff05; 4285 let Inst{3-0} = opt; 4286} 4287} 4288 4289def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4290 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4291 Requires<[IsARM, HasDB]> { 4292 bits<4> opt; 4293 let Inst{31-4} = 0xf57ff04; 4294 let Inst{3-0} = opt; 4295} 4296 4297// ISB has only full system option 4298def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4299 "isb", "\t$opt", []>, 4300 Requires<[IsARM, HasDB]> { 4301 bits<4> opt; 4302 let Inst{31-4} = 0xf57ff06; 4303 let Inst{3-0} = opt; 4304} 4305 4306let usesCustomInserter = 1, Defs = [CPSR] in { 4307 4308// Pseudo instruction that combines movs + predicated rsbmi 4309// to implement integer ABS 4310 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4311 4312// Atomic pseudo-insts which will be lowered to ldrex/strex loops. 4313// (64-bit pseudos use a hand-written selection code). 4314 let mayLoad = 1, mayStore = 1 in { 4315 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 4316 (outs GPR:$dst), 4317 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4318 NoItinerary, []>; 4319 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 4320 (outs GPR:$dst), 4321 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4322 NoItinerary, []>; 4323 def ATOMIC_LOAD_AND_I8 : PseudoInst< 4324 (outs GPR:$dst), 4325 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4326 NoItinerary, []>; 4327 def ATOMIC_LOAD_OR_I8 : PseudoInst< 4328 (outs GPR:$dst), 4329 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4330 NoItinerary, []>; 4331 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 4332 (outs GPR:$dst), 4333 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4334 NoItinerary, []>; 4335 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 4336 (outs GPR:$dst), 4337 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4338 NoItinerary, []>; 4339 def ATOMIC_LOAD_MIN_I8 : PseudoInst< 4340 (outs GPR:$dst), 4341 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4342 NoItinerary, []>; 4343 def ATOMIC_LOAD_MAX_I8 : PseudoInst< 4344 (outs GPR:$dst), 4345 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4346 NoItinerary, []>; 4347 def ATOMIC_LOAD_UMIN_I8 : PseudoInst< 4348 (outs GPR:$dst), 4349 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4350 NoItinerary, []>; 4351 def ATOMIC_LOAD_UMAX_I8 : PseudoInst< 4352 (outs GPR:$dst), 4353 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4354 NoItinerary, []>; 4355 def ATOMIC_SWAP_I8 : PseudoInst< 4356 (outs GPR:$dst), 4357 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4358 NoItinerary, []>; 4359 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 4360 (outs GPR:$dst), 4361 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4362 NoItinerary, []>; 4363 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 4364 (outs GPR:$dst), 4365 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4366 NoItinerary, []>; 4367 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 4368 (outs GPR:$dst), 4369 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4370 NoItinerary, []>; 4371 def ATOMIC_LOAD_AND_I16 : PseudoInst< 4372 (outs GPR:$dst), 4373 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4374 NoItinerary, []>; 4375 def ATOMIC_LOAD_OR_I16 : PseudoInst< 4376 (outs GPR:$dst), 4377 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4378 NoItinerary, []>; 4379 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 4380 (outs GPR:$dst), 4381 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4382 NoItinerary, []>; 4383 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 4384 (outs GPR:$dst), 4385 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4386 NoItinerary, []>; 4387 def ATOMIC_LOAD_MIN_I16 : PseudoInst< 4388 (outs GPR:$dst), 4389 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4390 NoItinerary, []>; 4391 def ATOMIC_LOAD_MAX_I16 : PseudoInst< 4392 (outs GPR:$dst), 4393 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4394 NoItinerary, []>; 4395 def ATOMIC_LOAD_UMIN_I16 : PseudoInst< 4396 (outs GPR:$dst), 4397 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4398 NoItinerary, []>; 4399 def ATOMIC_LOAD_UMAX_I16 : PseudoInst< 4400 (outs GPR:$dst), 4401 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4402 NoItinerary, []>; 4403 def ATOMIC_SWAP_I16 : PseudoInst< 4404 (outs GPR:$dst), 4405 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4406 NoItinerary, []>; 4407 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 4408 (outs GPR:$dst), 4409 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4410 NoItinerary, []>; 4411 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 4412 (outs GPR:$dst), 4413 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4414 NoItinerary, []>; 4415 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 4416 (outs GPR:$dst), 4417 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4418 NoItinerary, []>; 4419 def ATOMIC_LOAD_AND_I32 : PseudoInst< 4420 (outs GPR:$dst), 4421 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4422 NoItinerary, []>; 4423 def ATOMIC_LOAD_OR_I32 : PseudoInst< 4424 (outs GPR:$dst), 4425 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4426 NoItinerary, []>; 4427 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 4428 (outs GPR:$dst), 4429 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4430 NoItinerary, []>; 4431 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 4432 (outs GPR:$dst), 4433 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering), 4434 NoItinerary, []>; 4435 def ATOMIC_LOAD_MIN_I32 : PseudoInst< 4436 (outs GPR:$dst), 4437 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4438 NoItinerary, []>; 4439 def ATOMIC_LOAD_MAX_I32 : PseudoInst< 4440 (outs GPR:$dst), 4441 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4442 NoItinerary, []>; 4443 def ATOMIC_LOAD_UMIN_I32 : PseudoInst< 4444 (outs GPR:$dst), 4445 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4446 NoItinerary, []>; 4447 def ATOMIC_LOAD_UMAX_I32 : PseudoInst< 4448 (outs GPR:$dst), 4449 (ins GPR:$ptr, GPR:$val, i32imm:$ordering), 4450 NoItinerary, []>; 4451 def ATOMIC_SWAP_I32 : PseudoInst< 4452 (outs GPR:$dst), 4453 (ins GPR:$ptr, GPR:$new, i32imm:$ordering), 4454 NoItinerary, []>; 4455 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 4456 (outs GPR:$dst), 4457 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering), 4458 NoItinerary, []>; 4459 def ATOMIC_LOAD_ADD_I64 : PseudoInst< 4460 (outs GPR:$dst1, GPR:$dst2), 4461 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4462 NoItinerary, []>; 4463 def ATOMIC_LOAD_SUB_I64 : PseudoInst< 4464 (outs GPR:$dst1, GPR:$dst2), 4465 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4466 NoItinerary, []>; 4467 def ATOMIC_LOAD_AND_I64 : PseudoInst< 4468 (outs GPR:$dst1, GPR:$dst2), 4469 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4470 NoItinerary, []>; 4471 def ATOMIC_LOAD_OR_I64 : PseudoInst< 4472 (outs GPR:$dst1, GPR:$dst2), 4473 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4474 NoItinerary, []>; 4475 def ATOMIC_LOAD_XOR_I64 : PseudoInst< 4476 (outs GPR:$dst1, GPR:$dst2), 4477 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4478 NoItinerary, []>; 4479 def ATOMIC_LOAD_NAND_I64 : PseudoInst< 4480 (outs GPR:$dst1, GPR:$dst2), 4481 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4482 NoItinerary, []>; 4483 def ATOMIC_LOAD_MIN_I64 : PseudoInst< 4484 (outs GPR:$dst1, GPR:$dst2), 4485 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4486 NoItinerary, []>; 4487 def ATOMIC_LOAD_MAX_I64 : PseudoInst< 4488 (outs GPR:$dst1, GPR:$dst2), 4489 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4490 NoItinerary, []>; 4491 def ATOMIC_LOAD_UMIN_I64 : PseudoInst< 4492 (outs GPR:$dst1, GPR:$dst2), 4493 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4494 NoItinerary, []>; 4495 def ATOMIC_LOAD_UMAX_I64 : PseudoInst< 4496 (outs GPR:$dst1, GPR:$dst2), 4497 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4498 NoItinerary, []>; 4499 def ATOMIC_SWAP_I64 : PseudoInst< 4500 (outs GPR:$dst1, GPR:$dst2), 4501 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4502 NoItinerary, []>; 4503 def ATOMIC_CMP_SWAP_I64 : PseudoInst< 4504 (outs GPR:$dst1, GPR:$dst2), 4505 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2, 4506 GPR:$set1, GPR:$set2, i32imm:$ordering), 4507 NoItinerary, []>; 4508 } 4509 let mayLoad = 1 in 4510 def ATOMIC_LOAD_I64 : PseudoInst< 4511 (outs GPR:$dst1, GPR:$dst2), 4512 (ins GPR:$addr, i32imm:$ordering), 4513 NoItinerary, []>; 4514 let mayStore = 1 in 4515 def ATOMIC_STORE_I64 : PseudoInst< 4516 (outs GPR:$dst1, GPR:$dst2), 4517 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering), 4518 NoItinerary, []>; 4519} 4520 4521let usesCustomInserter = 1 in { 4522 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4523 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4524 NoItinerary, 4525 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4526} 4527 4528def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4529 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4530}]>; 4531 4532def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4533 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4534}]>; 4535 4536def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4537 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4538}]>; 4539 4540def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4541 (int_arm_strex node:$val, node:$ptr), [{ 4542 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4543}]>; 4544 4545def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4546 (int_arm_strex node:$val, node:$ptr), [{ 4547 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4548}]>; 4549 4550def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4551 (int_arm_strex node:$val, node:$ptr), [{ 4552 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4553}]>; 4554 4555let mayLoad = 1 in { 4556def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4557 NoItinerary, "ldrexb", "\t$Rt, $addr", 4558 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4559def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4560 NoItinerary, "ldrexh", "\t$Rt, $addr", 4561 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4562def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4563 NoItinerary, "ldrex", "\t$Rt, $addr", 4564 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4565let hasExtraDefRegAllocReq = 1 in 4566def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4567 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 4568 let DecoderMethod = "DecodeDoubleRegLoad"; 4569} 4570 4571def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4572 NoItinerary, "ldaexb", "\t$Rt, $addr", []>; 4573def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4574 NoItinerary, "ldaexh", "\t$Rt, $addr", []>; 4575def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4576 NoItinerary, "ldaex", "\t$Rt, $addr", []>; 4577let hasExtraDefRegAllocReq = 1 in 4578def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 4579 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 4580 let DecoderMethod = "DecodeDoubleRegLoad"; 4581} 4582} 4583 4584let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4585def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4586 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 4587 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>; 4588def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4589 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 4590 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>; 4591def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4592 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 4593 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>; 4594let hasExtraSrcRegAllocReq = 1 in 4595def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4596 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4597 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 4598 let DecoderMethod = "DecodeDoubleRegStore"; 4599} 4600def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4601 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 4602 []>; 4603def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4604 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 4605 []>; 4606def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4607 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 4608 []>; 4609let hasExtraSrcRegAllocReq = 1 in 4610def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 4611 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 4612 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 4613 let DecoderMethod = "DecodeDoubleRegStore"; 4614} 4615} 4616 4617def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 4618 [(int_arm_clrex)]>, 4619 Requires<[IsARM, HasV7]> { 4620 let Inst{31-0} = 0b11110101011111111111000000011111; 4621} 4622 4623def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff), 4624 (LDREXB addr_offset_none:$addr)>; 4625def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), 4626 (LDREXH addr_offset_none:$addr)>; 4627def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 4628 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 4629def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 4630 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 4631 4632class acquiring_load<PatFrag base> 4633 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4634 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4635 return Ordering == Acquire || Ordering == SequentiallyConsistent; 4636}]>; 4637 4638def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 4639def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 4640def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 4641 4642class releasing_store<PatFrag base> 4643 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4644 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 4645 return Ordering == Release || Ordering == SequentiallyConsistent; 4646}]>; 4647 4648def atomic_store_release_8 : releasing_store<atomic_store_8>; 4649def atomic_store_release_16 : releasing_store<atomic_store_16>; 4650def atomic_store_release_32 : releasing_store<atomic_store_32>; 4651 4652let AddedComplexity = 8 in { 4653 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 4654 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 4655 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 4656 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 4657 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 4658 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 4659} 4660 4661// SWP/SWPB are deprecated in V6/V7. 4662let mayLoad = 1, mayStore = 1 in { 4663def SWP : AIswp<0, (outs GPRnopc:$Rt), 4664 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 4665 Requires<[PreV8]>; 4666def SWPB: AIswp<1, (outs GPRnopc:$Rt), 4667 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 4668 Requires<[PreV8]>; 4669} 4670 4671//===----------------------------------------------------------------------===// 4672// Coprocessor Instructions. 4673// 4674 4675def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4676 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4677 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4678 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4679 imm:$CRm, imm:$opc2)]>, 4680 Requires<[PreV8]> { 4681 bits<4> opc1; 4682 bits<4> CRn; 4683 bits<4> CRd; 4684 bits<4> cop; 4685 bits<3> opc2; 4686 bits<4> CRm; 4687 4688 let Inst{3-0} = CRm; 4689 let Inst{4} = 0; 4690 let Inst{7-5} = opc2; 4691 let Inst{11-8} = cop; 4692 let Inst{15-12} = CRd; 4693 let Inst{19-16} = CRn; 4694 let Inst{23-20} = opc1; 4695} 4696 4697def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4698 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4699 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4700 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4701 imm:$CRm, imm:$opc2)]>, 4702 Requires<[PreV8]> { 4703 let Inst{31-28} = 0b1111; 4704 bits<4> opc1; 4705 bits<4> CRn; 4706 bits<4> CRd; 4707 bits<4> cop; 4708 bits<3> opc2; 4709 bits<4> CRm; 4710 4711 let Inst{3-0} = CRm; 4712 let Inst{4} = 0; 4713 let Inst{7-5} = opc2; 4714 let Inst{11-8} = cop; 4715 let Inst{15-12} = CRd; 4716 let Inst{19-16} = CRn; 4717 let Inst{23-20} = opc1; 4718} 4719 4720class ACI<dag oops, dag iops, string opc, string asm, 4721 IndexMode im = IndexModeNone> 4722 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4723 opc, asm, "", []> { 4724 let Inst{27-25} = 0b110; 4725} 4726class ACInoP<dag oops, dag iops, string opc, string asm, 4727 IndexMode im = IndexModeNone> 4728 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4729 opc, asm, "", []> { 4730 let Inst{31-28} = 0b1111; 4731 let Inst{27-25} = 0b110; 4732} 4733multiclass LdStCop<bit load, bit Dbit, string asm> { 4734 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4735 asm, "\t$cop, $CRd, $addr"> { 4736 bits<13> addr; 4737 bits<4> cop; 4738 bits<4> CRd; 4739 let Inst{24} = 1; // P = 1 4740 let Inst{23} = addr{8}; 4741 let Inst{22} = Dbit; 4742 let Inst{21} = 0; // W = 0 4743 let Inst{20} = load; 4744 let Inst{19-16} = addr{12-9}; 4745 let Inst{15-12} = CRd; 4746 let Inst{11-8} = cop; 4747 let Inst{7-0} = addr{7-0}; 4748 let DecoderMethod = "DecodeCopMemInstruction"; 4749 } 4750 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4751 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4752 bits<13> addr; 4753 bits<4> cop; 4754 bits<4> CRd; 4755 let Inst{24} = 1; // P = 1 4756 let Inst{23} = addr{8}; 4757 let Inst{22} = Dbit; 4758 let Inst{21} = 1; // W = 1 4759 let Inst{20} = load; 4760 let Inst{19-16} = addr{12-9}; 4761 let Inst{15-12} = CRd; 4762 let Inst{11-8} = cop; 4763 let Inst{7-0} = addr{7-0}; 4764 let DecoderMethod = "DecodeCopMemInstruction"; 4765 } 4766 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4767 postidx_imm8s4:$offset), 4768 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4769 bits<9> offset; 4770 bits<4> addr; 4771 bits<4> cop; 4772 bits<4> CRd; 4773 let Inst{24} = 0; // P = 0 4774 let Inst{23} = offset{8}; 4775 let Inst{22} = Dbit; 4776 let Inst{21} = 1; // W = 1 4777 let Inst{20} = load; 4778 let Inst{19-16} = addr; 4779 let Inst{15-12} = CRd; 4780 let Inst{11-8} = cop; 4781 let Inst{7-0} = offset{7-0}; 4782 let DecoderMethod = "DecodeCopMemInstruction"; 4783 } 4784 def _OPTION : ACI<(outs), 4785 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4786 coproc_option_imm:$option), 4787 asm, "\t$cop, $CRd, $addr, $option"> { 4788 bits<8> option; 4789 bits<4> addr; 4790 bits<4> cop; 4791 bits<4> CRd; 4792 let Inst{24} = 0; // P = 0 4793 let Inst{23} = 1; // U = 1 4794 let Inst{22} = Dbit; 4795 let Inst{21} = 0; // W = 0 4796 let Inst{20} = load; 4797 let Inst{19-16} = addr; 4798 let Inst{15-12} = CRd; 4799 let Inst{11-8} = cop; 4800 let Inst{7-0} = option; 4801 let DecoderMethod = "DecodeCopMemInstruction"; 4802 } 4803} 4804multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4805 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4806 asm, "\t$cop, $CRd, $addr"> { 4807 bits<13> addr; 4808 bits<4> cop; 4809 bits<4> CRd; 4810 let Inst{24} = 1; // P = 1 4811 let Inst{23} = addr{8}; 4812 let Inst{22} = Dbit; 4813 let Inst{21} = 0; // W = 0 4814 let Inst{20} = load; 4815 let Inst{19-16} = addr{12-9}; 4816 let Inst{15-12} = CRd; 4817 let Inst{11-8} = cop; 4818 let Inst{7-0} = addr{7-0}; 4819 let DecoderMethod = "DecodeCopMemInstruction"; 4820 } 4821 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 4822 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4823 bits<13> addr; 4824 bits<4> cop; 4825 bits<4> CRd; 4826 let Inst{24} = 1; // P = 1 4827 let Inst{23} = addr{8}; 4828 let Inst{22} = Dbit; 4829 let Inst{21} = 1; // W = 1 4830 let Inst{20} = load; 4831 let Inst{19-16} = addr{12-9}; 4832 let Inst{15-12} = CRd; 4833 let Inst{11-8} = cop; 4834 let Inst{7-0} = addr{7-0}; 4835 let DecoderMethod = "DecodeCopMemInstruction"; 4836 } 4837 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4838 postidx_imm8s4:$offset), 4839 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4840 bits<9> offset; 4841 bits<4> addr; 4842 bits<4> cop; 4843 bits<4> CRd; 4844 let Inst{24} = 0; // P = 0 4845 let Inst{23} = offset{8}; 4846 let Inst{22} = Dbit; 4847 let Inst{21} = 1; // W = 1 4848 let Inst{20} = load; 4849 let Inst{19-16} = addr; 4850 let Inst{15-12} = CRd; 4851 let Inst{11-8} = cop; 4852 let Inst{7-0} = offset{7-0}; 4853 let DecoderMethod = "DecodeCopMemInstruction"; 4854 } 4855 def _OPTION : ACInoP<(outs), 4856 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4857 coproc_option_imm:$option), 4858 asm, "\t$cop, $CRd, $addr, $option"> { 4859 bits<8> option; 4860 bits<4> addr; 4861 bits<4> cop; 4862 bits<4> CRd; 4863 let Inst{24} = 0; // P = 0 4864 let Inst{23} = 1; // U = 1 4865 let Inst{22} = Dbit; 4866 let Inst{21} = 0; // W = 0 4867 let Inst{20} = load; 4868 let Inst{19-16} = addr; 4869 let Inst{15-12} = CRd; 4870 let Inst{11-8} = cop; 4871 let Inst{7-0} = option; 4872 let DecoderMethod = "DecodeCopMemInstruction"; 4873 } 4874} 4875 4876defm LDC : LdStCop <1, 0, "ldc">; 4877defm LDCL : LdStCop <1, 1, "ldcl">; 4878defm STC : LdStCop <0, 0, "stc">; 4879defm STCL : LdStCop <0, 1, "stcl">; 4880defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>; 4881defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>; 4882defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>; 4883defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>; 4884 4885//===----------------------------------------------------------------------===// 4886// Move between coprocessor and ARM core register. 4887// 4888 4889class MovRCopro<string opc, bit direction, dag oops, dag iops, 4890 list<dag> pattern> 4891 : ABI<0b1110, oops, iops, NoItinerary, opc, 4892 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4893 let Inst{20} = direction; 4894 let Inst{4} = 1; 4895 4896 bits<4> Rt; 4897 bits<4> cop; 4898 bits<3> opc1; 4899 bits<3> opc2; 4900 bits<4> CRm; 4901 bits<4> CRn; 4902 4903 let Inst{15-12} = Rt; 4904 let Inst{11-8} = cop; 4905 let Inst{23-21} = opc1; 4906 let Inst{7-5} = opc2; 4907 let Inst{3-0} = CRm; 4908 let Inst{19-16} = CRn; 4909} 4910 4911def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4912 (outs), 4913 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4914 c_imm:$CRm, imm0_7:$opc2), 4915 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4916 imm:$CRm, imm:$opc2)]>, 4917 ComplexDeprecationPredicate<"MCR">; 4918def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4919 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4920 c_imm:$CRm, 0, pred:$p)>; 4921def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4922 (outs GPRwithAPSR:$Rt), 4923 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4924 imm0_7:$opc2), []>; 4925def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4926 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4927 c_imm:$CRm, 0, pred:$p)>; 4928 4929def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4930 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4931 4932class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4933 list<dag> pattern> 4934 : ABXI<0b1110, oops, iops, NoItinerary, 4935 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4936 let Inst{31-24} = 0b11111110; 4937 let Inst{20} = direction; 4938 let Inst{4} = 1; 4939 4940 bits<4> Rt; 4941 bits<4> cop; 4942 bits<3> opc1; 4943 bits<3> opc2; 4944 bits<4> CRm; 4945 bits<4> CRn; 4946 4947 let Inst{15-12} = Rt; 4948 let Inst{11-8} = cop; 4949 let Inst{23-21} = opc1; 4950 let Inst{7-5} = opc2; 4951 let Inst{3-0} = CRm; 4952 let Inst{19-16} = CRn; 4953} 4954 4955def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4956 (outs), 4957 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4958 c_imm:$CRm, imm0_7:$opc2), 4959 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4960 imm:$CRm, imm:$opc2)]>, 4961 Requires<[PreV8]>; 4962def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm", 4963 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4964 c_imm:$CRm, 0)>; 4965def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4966 (outs GPRwithAPSR:$Rt), 4967 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4968 imm0_7:$opc2), []>, 4969 Requires<[PreV8]>; 4970def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm", 4971 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4972 c_imm:$CRm, 0)>; 4973 4974def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 4975 imm:$CRm, imm:$opc2), 4976 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4977 4978class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 4979 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4980 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), 4981 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4982 let Inst{23-21} = 0b010; 4983 let Inst{20} = direction; 4984 4985 bits<4> Rt; 4986 bits<4> Rt2; 4987 bits<4> cop; 4988 bits<4> opc1; 4989 bits<4> CRm; 4990 4991 let Inst{15-12} = Rt; 4992 let Inst{19-16} = Rt2; 4993 let Inst{11-8} = cop; 4994 let Inst{7-4} = opc1; 4995 let Inst{3-0} = CRm; 4996} 4997 4998def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 4999 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5000 GPRnopc:$Rt2, imm:$CRm)]>; 5001def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 5002 5003class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 5004 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5005 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, 5006 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5007 Requires<[PreV8]> { 5008 let Inst{31-28} = 0b1111; 5009 let Inst{23-21} = 0b010; 5010 let Inst{20} = direction; 5011 5012 bits<4> Rt; 5013 bits<4> Rt2; 5014 bits<4> cop; 5015 bits<4> opc1; 5016 bits<4> CRm; 5017 5018 let Inst{15-12} = Rt; 5019 let Inst{19-16} = Rt2; 5020 let Inst{11-8} = cop; 5021 let Inst{7-4} = opc1; 5022 let Inst{3-0} = CRm; 5023 5024 let DecoderMethod = "DecodeMRRC2"; 5025} 5026 5027def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5028 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5029 GPRnopc:$Rt2, imm:$CRm)]>; 5030def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 5031 5032//===----------------------------------------------------------------------===// 5033// Move between special register and ARM core register 5034// 5035 5036// Move to ARM core register from Special Register 5037def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5038 "mrs", "\t$Rd, apsr", []> { 5039 bits<4> Rd; 5040 let Inst{23-16} = 0b00001111; 5041 let Unpredictable{19-17} = 0b111; 5042 5043 let Inst{15-12} = Rd; 5044 5045 let Inst{11-0} = 0b000000000000; 5046 let Unpredictable{11-0} = 0b110100001111; 5047} 5048 5049def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, 5050 Requires<[IsARM]>; 5051 5052// The MRSsys instruction is the MRS instruction from the ARM ARM, 5053// section B9.3.9, with the R bit set to 1. 5054def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5055 "mrs", "\t$Rd, spsr", []> { 5056 bits<4> Rd; 5057 let Inst{23-16} = 0b01001111; 5058 let Unpredictable{19-16} = 0b1111; 5059 5060 let Inst{15-12} = Rd; 5061 5062 let Inst{11-0} = 0b000000000000; 5063 let Unpredictable{11-0} = 0b110100001111; 5064} 5065 5066// Move from ARM core register to Special Register 5067// 5068// No need to have both system and application versions, the encodings are the 5069// same and the assembly parser has no way to distinguish between them. The mask 5070// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 5071// the mask with the fields to be accessed in the special register. 5072def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5073 "msr", "\t$mask, $Rn", []> { 5074 bits<5> mask; 5075 bits<4> Rn; 5076 5077 let Inst{23} = 0; 5078 let Inst{22} = mask{4}; // R bit 5079 let Inst{21-20} = 0b10; 5080 let Inst{19-16} = mask{3-0}; 5081 let Inst{15-12} = 0b1111; 5082 let Inst{11-4} = 0b00000000; 5083 let Inst{3-0} = Rn; 5084} 5085 5086def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 5087 "msr", "\t$mask, $a", []> { 5088 bits<5> mask; 5089 bits<12> a; 5090 5091 let Inst{23} = 0; 5092 let Inst{22} = mask{4}; // R bit 5093 let Inst{21-20} = 0b10; 5094 let Inst{19-16} = mask{3-0}; 5095 let Inst{15-12} = 0b1111; 5096 let Inst{11-0} = a; 5097} 5098 5099//===----------------------------------------------------------------------===// 5100// TLS Instructions 5101// 5102 5103// __aeabi_read_tp preserves the registers r1-r3. 5104// This is a pseudo inst so that we can get the encoding right, 5105// complete with fixup for the aeabi_read_tp function. 5106let isCall = 1, 5107 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5108 def TPsoft : PseudoInst<(outs), (ins), IIC_Br, 5109 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>; 5110} 5111 5112//===----------------------------------------------------------------------===// 5113// SJLJ Exception handling intrinsics 5114// eh_sjlj_setjmp() is an instruction sequence to store the return 5115// address and save #0 in R0 for the non-longjmp case. 5116// Since by its nature we may be coming from some other function to get 5117// here, and we're using the stack frame for the containing function to 5118// save/restore registers, we can't keep anything live in regs across 5119// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5120// when we get here from a longjmp(). We force everything out of registers 5121// except for our own input by listing the relevant registers in Defs. By 5122// doing so, we also cause the prologue/epilogue code to actively preserve 5123// all of the callee-saved resgisters, which is exactly what we want. 5124// A constant value is passed in $val, and we use the location as a scratch. 5125// 5126// These are pseudo-instructions and are lowered to individual MC-insts, so 5127// no encoding information is necessary. 5128let Defs = 5129 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5130 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5131 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5132 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5133 NoItinerary, 5134 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5135 Requires<[IsARM, HasVFP2]>; 5136} 5137 5138let Defs = 5139 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5140 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5141 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5142 NoItinerary, 5143 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5144 Requires<[IsARM, NoVFP]>; 5145} 5146 5147// FIXME: Non-IOS version(s) 5148let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5149 Defs = [ R7, LR, SP ] in { 5150def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5151 NoItinerary, 5152 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5153 Requires<[IsARM, IsIOS]>; 5154} 5155 5156// eh.sjlj.dispatchsetup pseudo-instruction. 5157// This pseudo is used for both ARM and Thumb. Any differences are handled when 5158// the pseudo is expanded (which happens before any passes that need the 5159// instruction size). 5160let isBarrier = 1 in 5161def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5162 5163 5164//===----------------------------------------------------------------------===// 5165// Non-Instruction Patterns 5166// 5167 5168// ARMv4 indirect branch using (MOVr PC, dst) 5169let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5170 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5171 4, IIC_Br, [(brind GPR:$dst)], 5172 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5173 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5174 5175// Large immediate handling. 5176 5177// 32-bit immediate using two piece so_imms or movw + movt. 5178// This is a single pseudo instruction, the benefit is that it can be remat'd 5179// as a single unit instead of having to handle reg inputs. 5180// FIXME: Remove this when we can do generalized remat. 5181let isReMaterializable = 1, isMoveImm = 1 in 5182def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5183 [(set GPR:$dst, (arm_i32imm:$src))]>, 5184 Requires<[IsARM]>; 5185 5186// Pseudo instruction that combines movw + movt + add pc (if PIC). 5187// It also makes it possible to rematerialize the instructions. 5188// FIXME: Remove this when we can do generalized remat and when machine licm 5189// can properly the instructions. 5190let isReMaterializable = 1 in { 5191def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5192 IIC_iMOVix2addpc, 5193 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5194 Requires<[IsARM, UseMovt]>; 5195 5196def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5197 IIC_iMOVix2, 5198 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 5199 Requires<[IsARM, UseMovt]>; 5200 5201let AddedComplexity = 10 in 5202def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5203 IIC_iMOVix2ld, 5204 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5205 Requires<[IsARM, UseMovt]>; 5206} // isReMaterializable 5207 5208// ConstantPool, GlobalAddress, and JumpTable 5209def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, 5210 Requires<[IsARM, DontUseMovt]>; 5211def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5212def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5213 Requires<[IsARM, UseMovt]>; 5214def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 5215 (LEApcrelJT tjumptable:$dst, imm:$id)>; 5216 5217// TODO: add,sub,and, 3-instr forms? 5218 5219// Tail calls. These patterns also apply to Thumb mode. 5220def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5221def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5222def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5223 5224// Direct calls 5225def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5226def : ARMPat<(ARMcall_nolink texternalsym:$func), 5227 (BMOVPCB_CALL texternalsym:$func)>; 5228 5229// zextload i1 -> zextload i8 5230def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5231def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5232 5233// extload -> zextload 5234def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5235def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5236def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5237def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5238 5239def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5240 5241def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5242def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5243 5244// smul* and smla* 5245def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5246 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5247 (SMULBB GPR:$a, GPR:$b)>; 5248def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5249 (SMULBB GPR:$a, GPR:$b)>; 5250def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5251 (sra GPR:$b, (i32 16))), 5252 (SMULBT GPR:$a, GPR:$b)>; 5253def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 5254 (SMULBT GPR:$a, GPR:$b)>; 5255def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 5256 (sra (shl GPR:$b, (i32 16)), (i32 16))), 5257 (SMULTB GPR:$a, GPR:$b)>; 5258def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 5259 (SMULTB GPR:$a, GPR:$b)>; 5260def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5261 (i32 16)), 5262 (SMULWB GPR:$a, GPR:$b)>; 5263def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 5264 (SMULWB GPR:$a, GPR:$b)>; 5265 5266def : ARMV5MOPat<(add GPR:$acc, 5267 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5268 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5269 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5270def : ARMV5MOPat<(add GPR:$acc, 5271 (mul sext_16_node:$a, sext_16_node:$b)), 5272 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5273def : ARMV5MOPat<(add GPR:$acc, 5274 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 5275 (sra GPR:$b, (i32 16)))), 5276 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5277def : ARMV5MOPat<(add GPR:$acc, 5278 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 5279 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5280def : ARMV5MOPat<(add GPR:$acc, 5281 (mul (sra GPR:$a, (i32 16)), 5282 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 5283 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5284def : ARMV5MOPat<(add GPR:$acc, 5285 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 5286 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5287def : ARMV5MOPat<(add GPR:$acc, 5288 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 5289 (i32 16))), 5290 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5291def : ARMV5MOPat<(add GPR:$acc, 5292 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 5293 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5294 5295 5296// Pre-v7 uses MCR for synchronization barriers. 5297def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5298 Requires<[IsARM, HasV6]>; 5299 5300// SXT/UXT with no rotate 5301let AddedComplexity = 16 in { 5302def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5303def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5304def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5305def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5306 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5307def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5308 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5309} 5310 5311def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5312def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5313 5314def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5315 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5316def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5317 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5318 5319// Atomic load/store patterns 5320def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5321 (LDRBrs ldst_so_reg:$src)>; 5322def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5323 (LDRBi12 addrmode_imm12:$src)>; 5324def : ARMPat<(atomic_load_16 addrmode3:$src), 5325 (LDRH addrmode3:$src)>; 5326def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5327 (LDRrs ldst_so_reg:$src)>; 5328def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5329 (LDRi12 addrmode_imm12:$src)>; 5330def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5331 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5332def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5333 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5334def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5335 (STRH GPR:$val, addrmode3:$ptr)>; 5336def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5337 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5338def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5339 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5340 5341 5342//===----------------------------------------------------------------------===// 5343// Thumb Support 5344// 5345 5346include "ARMInstrThumb.td" 5347 5348//===----------------------------------------------------------------------===// 5349// Thumb2 Support 5350// 5351 5352include "ARMInstrThumb2.td" 5353 5354//===----------------------------------------------------------------------===// 5355// Floating Point Support 5356// 5357 5358include "ARMInstrVFP.td" 5359 5360//===----------------------------------------------------------------------===// 5361// Advanced SIMD (NEON) Support 5362// 5363 5364include "ARMInstrNEON.td" 5365 5366//===----------------------------------------------------------------------===// 5367// Assembler aliases 5368// 5369 5370// Memory barriers 5371def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 5372def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 5373def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 5374 5375// System instructions 5376def : MnemonicAlias<"swi", "svc">; 5377 5378// Load / Store Multiple 5379def : MnemonicAlias<"ldmfd", "ldm">; 5380def : MnemonicAlias<"ldmia", "ldm">; 5381def : MnemonicAlias<"ldmea", "ldmdb">; 5382def : MnemonicAlias<"stmfd", "stmdb">; 5383def : MnemonicAlias<"stmia", "stm">; 5384def : MnemonicAlias<"stmea", "stm">; 5385 5386// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 5387// shift amount is zero (i.e., unspecified). 5388def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5389 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5390 Requires<[IsARM, HasV6]>; 5391def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5392 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 5393 Requires<[IsARM, HasV6]>; 5394 5395// PUSH/POP aliases for STM/LDM 5396def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5397def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5398 5399// SSAT/USAT optional shift operand. 5400def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5401 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5402def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5403 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5404 5405 5406// Extend instruction optional rotate operand. 5407def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5408 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5409def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5410 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5411def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5412 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5413def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5414 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5415def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5416 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5417def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5418 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5419 5420def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5421 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5422def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5423 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5424def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5425 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5426def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5427 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5428def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5429 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5430def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5431 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5432 5433 5434// RFE aliases 5435def : MnemonicAlias<"rfefa", "rfeda">; 5436def : MnemonicAlias<"rfeea", "rfedb">; 5437def : MnemonicAlias<"rfefd", "rfeia">; 5438def : MnemonicAlias<"rfeed", "rfeib">; 5439def : MnemonicAlias<"rfe", "rfeia">; 5440 5441// SRS aliases 5442def : MnemonicAlias<"srsfa", "srsib">; 5443def : MnemonicAlias<"srsea", "srsia">; 5444def : MnemonicAlias<"srsfd", "srsdb">; 5445def : MnemonicAlias<"srsed", "srsda">; 5446def : MnemonicAlias<"srs", "srsia">; 5447 5448// QSAX == QSUBADDX 5449def : MnemonicAlias<"qsubaddx", "qsax">; 5450// SASX == SADDSUBX 5451def : MnemonicAlias<"saddsubx", "sasx">; 5452// SHASX == SHADDSUBX 5453def : MnemonicAlias<"shaddsubx", "shasx">; 5454// SHSAX == SHSUBADDX 5455def : MnemonicAlias<"shsubaddx", "shsax">; 5456// SSAX == SSUBADDX 5457def : MnemonicAlias<"ssubaddx", "ssax">; 5458// UASX == UADDSUBX 5459def : MnemonicAlias<"uaddsubx", "uasx">; 5460// UHASX == UHADDSUBX 5461def : MnemonicAlias<"uhaddsubx", "uhasx">; 5462// UHSAX == UHSUBADDX 5463def : MnemonicAlias<"uhsubaddx", "uhsax">; 5464// UQASX == UQADDSUBX 5465def : MnemonicAlias<"uqaddsubx", "uqasx">; 5466// UQSAX == UQSUBADDX 5467def : MnemonicAlias<"uqsubaddx", "uqsax">; 5468// USAX == USUBADDX 5469def : MnemonicAlias<"usubaddx", "usax">; 5470 5471// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5472// for isel. 5473def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5474 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5475def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5476 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5477// Same for AND <--> BIC 5478def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5479 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5480 pred:$p, cc_out:$s)>; 5481def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5482 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5483 pred:$p, cc_out:$s)>; 5484def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5485 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5486 pred:$p, cc_out:$s)>; 5487def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5488 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5489 pred:$p, cc_out:$s)>; 5490 5491// Likewise, "add Rd, so_imm_neg" -> sub 5492def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5493 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5494def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5495 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5496// Same for CMP <--> CMN via so_imm_neg 5497def : ARMInstAlias<"cmp${p} $Rd, $imm", 5498 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5499def : ARMInstAlias<"cmn${p} $Rd, $imm", 5500 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5501 5502// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5503// LSR, ROR, and RRX instructions. 5504// FIXME: We need C++ parser hooks to map the alias to the MOV 5505// encoding. It seems we should be able to do that sort of thing 5506// in tblgen, but it could get ugly. 5507let TwoOperandAliasConstraint = "$Rm = $Rd" in { 5508def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5509 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5510 cc_out:$s)>; 5511def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5512 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5513 cc_out:$s)>; 5514def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5515 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5516 cc_out:$s)>; 5517def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5518 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5519 cc_out:$s)>; 5520} 5521def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5522 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 5523let TwoOperandAliasConstraint = "$Rn = $Rd" in { 5524def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5525 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5526 cc_out:$s)>; 5527def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5528 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5529 cc_out:$s)>; 5530def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5531 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5532 cc_out:$s)>; 5533def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5534 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5535 cc_out:$s)>; 5536} 5537 5538// "neg" is and alias for "rsb rd, rn, #0" 5539def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5540 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5541 5542// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5543def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5544 Requires<[IsARM, NoV6]>; 5545 5546// UMULL/SMULL are available on all arches, but the instruction definitions 5547// need difference constraints pre-v6. Use these aliases for the assembly 5548// parsing on pre-v6. 5549def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5550 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5551 Requires<[IsARM, NoV6]>; 5552def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5553 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5554 Requires<[IsARM, NoV6]>; 5555 5556// 'it' blocks in ARM mode just validate the predicates. The IT itself 5557// is discarded. 5558def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 5559 ComplexDeprecationPredicate<"IT">; 5560