1234353Sdim//===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// This describes the calling conventions for ARM architecture. 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed 12193323Sed/// CCIfAlign - Match of the original alignment of the arg 13193323Sedclass CCIfAlign<string Align, CCAction A>: 14193323Sed CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>; 15193323Sed 16193323Sed//===----------------------------------------------------------------------===// 17193323Sed// ARM APCS Calling Convention 18193323Sed//===----------------------------------------------------------------------===// 19193323Seddef CC_ARM_APCS : CallingConv<[ 20193323Sed 21221345Sdim // Handles byval parameters. 22221345Sdim CCIfByVal<CCPassByVal<4, 4>>, 23221345Sdim 24234353Sdim CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25193323Sed 26194710Sed // Handle all vector types as either f64 or v2f64. 27194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 28194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 29193323Sed 30194710Sed // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 31194710Sed CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 32194710Sed 33193323Sed CCIfType<[f32], CCBitConvertToType<i32>>, 34193323Sed CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 35193323Sed 36193323Sed CCIfType<[i32], CCAssignToStack<4, 4>>, 37194710Sed CCIfType<[f64], CCAssignToStack<8, 4>>, 38194710Sed CCIfType<[v2f64], CCAssignToStack<16, 4>> 39193323Sed]>; 40193323Sed 41193323Seddef RetCC_ARM_APCS : CallingConv<[ 42234353Sdim CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 43193323Sed CCIfType<[f32], CCBitConvertToType<i32>>, 44193323Sed 45194710Sed // Handle all vector types as either f64 or v2f64. 46194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 47194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 48194710Sed 49194710Sed CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 50194710Sed 51193323Sed CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 52193323Sed CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 53193323Sed]>; 54193323Sed 55193323Sed//===----------------------------------------------------------------------===// 56218893Sdim// ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 57218893Sdim//===----------------------------------------------------------------------===// 58218893Sdimdef FastCC_ARM_APCS : CallingConv<[ 59218893Sdim // Handle all vector types as either f64 or v2f64. 60218893Sdim CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 61218893Sdim CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 62218893Sdim 63218893Sdim CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 64218893Sdim CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 65218893Sdim CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 66218893Sdim S9, S10, S11, S12, S13, S14, S15]>>, 67218893Sdim CCDelegateTo<CC_ARM_APCS> 68218893Sdim]>; 69218893Sdim 70218893Sdimdef RetFastCC_ARM_APCS : CallingConv<[ 71218893Sdim // Handle all vector types as either f64 or v2f64. 72218893Sdim CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 73218893Sdim CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 74218893Sdim 75218893Sdim CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 76218893Sdim CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 77218893Sdim CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 78218893Sdim S9, S10, S11, S12, S13, S14, S15]>>, 79218893Sdim CCDelegateTo<RetCC_ARM_APCS> 80218893Sdim]>; 81218893Sdim 82239462Sdim//===----------------------------------------------------------------------===// 83239462Sdim// ARM APCS Calling Convention for GHC 84239462Sdim//===----------------------------------------------------------------------===// 85218893Sdim 86239462Sdimdef CC_ARM_APCS_GHC : CallingConv<[ 87239462Sdim // Handle all vector types as either f64 or v2f64. 88239462Sdim CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 89239462Sdim CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 90239462Sdim 91239462Sdim CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 92239462Sdim CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 93239462Sdim CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 94239462Sdim 95239462Sdim // Promote i8/i16 arguments to i32. 96239462Sdim CCIfType<[i8, i16], CCPromoteToType<i32>>, 97239462Sdim 98239462Sdim // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 99239462Sdim CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 100239462Sdim]>; 101239462Sdim 102218893Sdim//===----------------------------------------------------------------------===// 103194178Sed// ARM AAPCS (EABI) Calling Convention, common parts 104193323Sed//===----------------------------------------------------------------------===// 105193323Sed 106194178Seddef CC_ARM_AAPCS_Common : CallingConv<[ 107194178Sed 108234353Sdim CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 109193323Sed 110193323Sed // i64/f64 is passed in even pairs of GPRs 111193323Sed // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 112193323Sed // (and the same is true for f64 if VFP is not enabled) 113193323Sed CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 114251662Sdim CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", 115193323Sed CCAssignToReg<[R0, R1, R2, R3]>>>, 116193323Sed 117212904Sdim CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, R3>>>, 118194178Sed CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 119194710Sed CCIfType<[f64], CCAssignToStack<8, 8>>, 120194710Sed CCIfType<[v2f64], CCAssignToStack<16, 8>> 121193323Sed]>; 122193323Sed 123194178Seddef RetCC_ARM_AAPCS_Common : CallingConv<[ 124234353Sdim CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 125194178Sed CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 126194178Sed CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 127194178Sed]>; 128194178Sed 129194178Sed//===----------------------------------------------------------------------===// 130194178Sed// ARM AAPCS (EABI) Calling Convention 131194178Sed//===----------------------------------------------------------------------===// 132194178Sed 133194178Seddef CC_ARM_AAPCS : CallingConv<[ 134239462Sdim // Handles byval parameters. 135239462Sdim CCIfByVal<CCPassByVal<4, 4>>, 136239462Sdim 137194710Sed // Handle all vector types as either f64 or v2f64. 138194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 139194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 140194710Sed 141194710Sed CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 142194178Sed CCIfType<[f32], CCBitConvertToType<i32>>, 143194178Sed CCDelegateTo<CC_ARM_AAPCS_Common> 144194178Sed]>; 145194178Sed 146193323Seddef RetCC_ARM_AAPCS : CallingConv<[ 147194710Sed // Handle all vector types as either f64 or v2f64. 148194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 149194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 150194710Sed 151194710Sed CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 152193323Sed CCIfType<[f32], CCBitConvertToType<i32>>, 153194178Sed CCDelegateTo<RetCC_ARM_AAPCS_Common> 154194178Sed]>; 155193323Sed 156194178Sed//===----------------------------------------------------------------------===// 157194178Sed// ARM AAPCS-VFP (EABI) Calling Convention 158218893Sdim// Also used for FastCC (when VFP2 or later is available) 159194178Sed//===----------------------------------------------------------------------===// 160194178Sed 161194178Seddef CC_ARM_AAPCS_VFP : CallingConv<[ 162239462Sdim // Handles byval parameters. 163239462Sdim CCIfByVal<CCPassByVal<4, 4>>, 164239462Sdim 165194710Sed // Handle all vector types as either f64 or v2f64. 166194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 167194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 168194710Sed 169198090Srdivacky CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 170194178Sed CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 171194178Sed CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 172194178Sed S9, S10, S11, S12, S13, S14, S15]>>, 173194178Sed CCDelegateTo<CC_ARM_AAPCS_Common> 174193323Sed]>; 175193323Sed 176194178Seddef RetCC_ARM_AAPCS_VFP : CallingConv<[ 177194710Sed // Handle all vector types as either f64 or v2f64. 178194710Sed CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 179194710Sed CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 180194710Sed 181198090Srdivacky CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 182194178Sed CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 183194178Sed CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 184194178Sed S9, S10, S11, S12, S13, S14, S15]>>, 185194178Sed CCDelegateTo<RetCC_ARM_AAPCS_Common> 186194178Sed]>; 187234353Sdim 188234353Sdim//===----------------------------------------------------------------------===// 189234353Sdim// Callee-saved register lists. 190234353Sdim//===----------------------------------------------------------------------===// 191234353Sdim 192243830Sdimdef CSR_NoRegs : CalleeSavedRegs<(add)>; 193243830Sdim 194234353Sdimdef CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 195234353Sdim (sequence "D%u", 15, 8))>; 196234353Sdim 197251662Sdim// Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' 198251662Sdim// and the pointer return value are both passed in R0 in these cases, this can 199251662Sdim// be partially modelled by treating R0 as a callee-saved register 200251662Sdim// Only the resulting RegMask is used; the SaveList is ignored 201251662Sdimdef CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, 202251662Sdim R5, R4, (sequence "D%u", 15, 8), 203251662Sdim R0)>; 204251662Sdim 205234353Sdim// iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 206234353Sdim// Also save R7-R4 first to match the stack frame fixed spill areas. 207234353Sdimdef CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 208239462Sdim 209251662Sdimdef CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 210263508Sdim (sub CSR_AAPCS_ThisReturn, R9))>; 211251662Sdim 212263508Sdim// The "interrupt" attribute is used to generate code that is acceptable in 213263508Sdim// exception-handlers of various kinds. It makes us use a different return 214263508Sdim// instruction (handled elsewhere) and affects which registers we must return to 215263508Sdim// our "caller" in the same state as we receive them. 216263508Sdim 217263508Sdim// For most interrupts, all registers except SP and LR are shared with 218263508Sdim// user-space. We mark LR to be saved anyway, since this is what the ARM backend 219263508Sdim// generally does rather than tracking its liveness as a normal register. 220263508Sdimdef CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; 221263508Sdim 222263508Sdim// The fast interrupt handlers have more private state and get their own copies 223263508Sdim// of R8-R12, in addition to SP and LR. As before, mark LR for saving too. 224263508Sdim 225263508Sdim// FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and 226263508Sdim// current frame lowering expects to encounter it while processing callee-saved 227263508Sdim// registers. 228263508Sdimdef CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; 229263508Sdim 230263508Sdim 231