ARMBaseRegisterInfo.cpp revision 263508
1193645Ssimon//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2193645Ssimon// 3193645Ssimon// The LLVM Compiler Infrastructure 4296465Sdelphij// 5193645Ssimon// This file is distributed under the University of Illinois Open Source 6193645Ssimon// License. See LICENSE.TXT for details. 7193645Ssimon// 8193645Ssimon//===----------------------------------------------------------------------===// 9296465Sdelphij// 10193645Ssimon// This file contains the base ARM implementation of TargetRegisterInfo class. 11193645Ssimon// 12193645Ssimon//===----------------------------------------------------------------------===// 13296465Sdelphij 14296465Sdelphij#include "ARMBaseRegisterInfo.h" 15296465Sdelphij#include "ARM.h" 16296465Sdelphij#include "ARMBaseInstrInfo.h" 17296465Sdelphij#include "ARMFrameLowering.h" 18296465Sdelphij#include "ARMMachineFunctionInfo.h" 19296465Sdelphij#include "ARMSubtarget.h" 20193645Ssimon#include "MCTargetDesc/ARMAddressingModes.h" 21296465Sdelphij#include "llvm/ADT/BitVector.h" 22193645Ssimon#include "llvm/ADT/SmallVector.h" 23193645Ssimon#include "llvm/CodeGen/MachineConstantPool.h" 24296465Sdelphij#include "llvm/CodeGen/MachineFrameInfo.h" 25296465Sdelphij#include "llvm/CodeGen/MachineFunction.h" 26296465Sdelphij#include "llvm/CodeGen/MachineInstrBuilder.h" 27296465Sdelphij#include "llvm/CodeGen/MachineRegisterInfo.h" 28296465Sdelphij#include "llvm/CodeGen/RegisterScavenging.h" 29296465Sdelphij#include "llvm/CodeGen/VirtRegMap.h" 30296465Sdelphij#include "llvm/IR/Constants.h" 31296465Sdelphij#include "llvm/IR/DerivedTypes.h" 32296465Sdelphij#include "llvm/IR/Function.h" 33296465Sdelphij#include "llvm/IR/LLVMContext.h" 34296465Sdelphij#include "llvm/Support/Debug.h" 35296465Sdelphij#include "llvm/Support/ErrorHandling.h" 36296465Sdelphij#include "llvm/Support/raw_ostream.h" 37296465Sdelphij#include "llvm/Target/TargetFrameLowering.h" 38296465Sdelphij#include "llvm/Target/TargetMachine.h" 39296465Sdelphij#include "llvm/Target/TargetOptions.h" 40296465Sdelphij 41193645Ssimon#define GET_REGINFO_TARGET_DESC 42205128Ssimon#include "ARMGenRegisterInfo.inc" 43296465Sdelphij 44193645Ssimonusing namespace llvm; 45193645Ssimon 46193645SsimonARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 47193645Ssimon : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), 48296465Sdelphij FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 49296465Sdelphij BasePtr(ARM::R6) { 50296465Sdelphij} 51296465Sdelphij 52296465Sdelphijconst uint16_t* 53296465SdelphijARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 54193645Ssimon const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 55296465Sdelphij ? CSR_iOS_SaveList 56296465Sdelphij : CSR_AAPCS_SaveList; 57296465Sdelphij 58296465Sdelphij if (!MF) return RegList; 59296465Sdelphij 60193645Ssimon const Function *F = MF->getFunction(); 61296465Sdelphij if (F->getCallingConv() == CallingConv::GHC) { 62193645Ssimon // GHC set of callee saved regs is empty as all those regs are 63205128Ssimon // used for passing STG regs around 64296465Sdelphij return CSR_NoRegs_SaveList; 65193645Ssimon } else if (F->hasFnAttribute("interrupt")) { 66193645Ssimon if (STI.isMClass()) { 67193645Ssimon // M-class CPUs have hardware which saves the registers needed to allow a 68296465Sdelphij // function conforming to the AAPCS to function as a handler. 69193645Ssimon return CSR_AAPCS_SaveList; 70296465Sdelphij } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 71296465Sdelphij // Fast interrupt mode gives the handler a private copy of R8-R14, so less 72296465Sdelphij // need to be saved to restore user-mode state. 73296465Sdelphij return CSR_FIQ_SaveList; 74296465Sdelphij } else { 75296465Sdelphij // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 76296465Sdelphij // exception handling. 77296465Sdelphij return CSR_GenericInt_SaveList; 78296465Sdelphij } 79193645Ssimon } 80296465Sdelphij 81193645Ssimon return RegList; 82296465Sdelphij} 83296465Sdelphij 84296465Sdelphijconst uint32_t* 85296465SdelphijARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 86296465Sdelphij if (CC == CallingConv::GHC) 87296465Sdelphij // This is academic becase all GHC calls are (supposed to be) tail calls 88193645Ssimon return CSR_NoRegs_RegMask; 89296465Sdelphij return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 90296465Sdelphij ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 91296465Sdelphij} 92296465Sdelphij 93296465Sdelphijconst uint32_t* 94296465SdelphijARMBaseRegisterInfo::getNoPreservedMask() const { 95296465Sdelphij return CSR_NoRegs_RegMask; 96296465Sdelphij} 97296465Sdelphij 98296465Sdelphijconst uint32_t* 99296465SdelphijARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 100296465Sdelphij // This should return a register mask that is the same as that returned by 101296465Sdelphij // getCallPreservedMask but that additionally preserves the register used for 102296465Sdelphij // the first i32 argument (which must also be the register used to return a 103296465Sdelphij // single i32 return value) 104193645Ssimon // 105296465Sdelphij // In case that the calling convention does not use the same register for 106193645Ssimon // both or otherwise does not want to enable this optimization, the function 107205128Ssimon // should return NULL 108296465Sdelphij if (CC == CallingConv::GHC) 109193645Ssimon // This is academic becase all GHC calls are (supposed to be) tail calls 110193645Ssimon return NULL; 111193645Ssimon return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 112193645Ssimon ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 113193645Ssimon} 114193645Ssimon 115296465SdelphijBitVector ARMBaseRegisterInfo:: 116296465SdelphijgetReservedRegs(const MachineFunction &MF) const { 117193645Ssimon const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 118193645Ssimon 119296465Sdelphij // FIXME: avoid re-calculating this every time. 120296465Sdelphij BitVector Reserved(getNumRegs()); 121296465Sdelphij Reserved.set(ARM::SP); 122296465Sdelphij Reserved.set(ARM::PC); 123296465Sdelphij Reserved.set(ARM::FPSCR); 124296465Sdelphij Reserved.set(ARM::APSR_NZCV); 125296465Sdelphij if (TFI->hasFP(MF)) 126296465Sdelphij Reserved.set(FramePtr); 127296465Sdelphij if (hasBasePointer(MF)) 128296465Sdelphij Reserved.set(BasePtr); 129296465Sdelphij // Some targets reserve R9. 130296465Sdelphij if (STI.isR9Reserved()) 131296465Sdelphij Reserved.set(ARM::R9); 132296465Sdelphij // Reserve D16-D31 if the subtarget doesn't support them. 133296465Sdelphij if (!STI.hasVFP3() || STI.hasD16()) { 134296465Sdelphij assert(ARM::D31 == ARM::D16 + 15); 135296465Sdelphij for (unsigned i = 0; i != 16; ++i) 136296465Sdelphij Reserved.set(ARM::D16 + i); 137296465Sdelphij } 138296465Sdelphij const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 139296465Sdelphij for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 140296465Sdelphij for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 141296465Sdelphij if (Reserved.test(*SI)) Reserved.set(*I); 142296465Sdelphij 143296465Sdelphij return Reserved; 144296465Sdelphij} 145296465Sdelphij 146296465Sdelphijconst TargetRegisterClass* 147296465SdelphijARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 148296465Sdelphij const { 149296465Sdelphij const TargetRegisterClass *Super = RC; 150296465Sdelphij TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 151296465Sdelphij do { 152296465Sdelphij switch (Super->getID()) { 153193645Ssimon case ARM::GPRRegClassID: 154296465Sdelphij case ARM::SPRRegClassID: 155296465Sdelphij case ARM::DPRRegClassID: 156296465Sdelphij case ARM::QPRRegClassID: 157296465Sdelphij case ARM::QQPRRegClassID: 158296465Sdelphij case ARM::QQQQPRRegClassID: 159296465Sdelphij case ARM::GPRPairRegClassID: 160296465Sdelphij return Super; 161296465Sdelphij } 162296465Sdelphij Super = *I++; 163296465Sdelphij } while (Super); 164296465Sdelphij return RC; 165296465Sdelphij} 166296465Sdelphij 167193645Ssimonconst TargetRegisterClass * 168296465SdelphijARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 169193645Ssimon const { 170296465Sdelphij return &ARM::GPRRegClass; 171296465Sdelphij} 172296465Sdelphij 173296465Sdelphijconst TargetRegisterClass * 174193645SsimonARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 175193645Ssimon if (RC == &ARM::CCRRegClass) 176193645Ssimon return 0; // Can't copy CCR registers. 177296465Sdelphij return RC; 178296465Sdelphij} 179193645Ssimon 180193645Ssimonunsigned 181296465SdelphijARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 182193645Ssimon MachineFunction &MF) const { 183296465Sdelphij const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 184193645Ssimon 185296465Sdelphij switch (RC->getID()) { 186193645Ssimon default: 187296465Sdelphij return 0; 188193645Ssimon case ARM::tGPRRegClassID: 189193645Ssimon return TFI->hasFP(MF) ? 4 : 5; 190296465Sdelphij case ARM::GPRRegClassID: { 191296465Sdelphij unsigned FP = TFI->hasFP(MF) ? 1 : 0; 192296465Sdelphij return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 193296465Sdelphij } 194296465Sdelphij case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 195193645Ssimon case ARM::DPRRegClassID: 196193645Ssimon return 32 - 10; 197193645Ssimon } 198296465Sdelphij} 199193645Ssimon 200205128Ssimon// Get the other register in a GPRPair. 201296465Sdelphijstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 202193645Ssimon for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 203193645Ssimon if (ARM::GPRPairRegClass.contains(*Supers)) 204193645Ssimon return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 205193645Ssimon return 0; 206193645Ssimon} 207193645Ssimon 208296465Sdelphij// Resolve the RegPairEven / RegPairOdd register allocator hints. 209193645Ssimonvoid 210193645SsimonARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 211193645Ssimon ArrayRef<MCPhysReg> Order, 212193645Ssimon SmallVectorImpl<MCPhysReg> &Hints, 213296465Sdelphij const MachineFunction &MF, 214296465Sdelphij const VirtRegMap *VRM) const { 215296465Sdelphij const MachineRegisterInfo &MRI = MF.getRegInfo(); 216296465Sdelphij std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 217296465Sdelphij 218296465Sdelphij unsigned Odd; 219296465Sdelphij switch (Hint.first) { 220296465Sdelphij case ARMRI::RegPairEven: 221296465Sdelphij Odd = 0; 222296465Sdelphij break; 223296465Sdelphij case ARMRI::RegPairOdd: 224296465Sdelphij Odd = 1; 225296465Sdelphij break; 226296465Sdelphij default: 227296465Sdelphij TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 228296465Sdelphij return; 229296465Sdelphij } 230296465Sdelphij 231296465Sdelphij // This register should preferably be even (Odd == 0) or odd (Odd == 1). 232296465Sdelphij // Check if the other part of the pair has already been assigned, and provide 233296465Sdelphij // the paired register as the first hint. 234296465Sdelphij unsigned PairedPhys = 0; 235296465Sdelphij if (VRM && VRM->hasPhys(Hint.second)) { 236296465Sdelphij PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 237296465Sdelphij if (PairedPhys && MRI.isReserved(PairedPhys)) 238296465Sdelphij PairedPhys = 0; 239296465Sdelphij } 240296465Sdelphij 241296465Sdelphij // First prefer the paired physreg. 242296465Sdelphij if (PairedPhys && 243296465Sdelphij std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 244296465Sdelphij Hints.push_back(PairedPhys); 245296465Sdelphij 246296465Sdelphij // Then prefer even or odd registers. 247296465Sdelphij for (unsigned I = 0, E = Order.size(); I != E; ++I) { 248296465Sdelphij unsigned Reg = Order[I]; 249296465Sdelphij if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 250296465Sdelphij continue; 251296465Sdelphij // Don't provide hints that are paired to a reserved register. 252296465Sdelphij unsigned Paired = getPairedGPR(Reg, !Odd, this); 253296465Sdelphij if (!Paired || MRI.isReserved(Paired)) 254296465Sdelphij continue; 255296465Sdelphij Hints.push_back(Reg); 256296465Sdelphij } 257296465Sdelphij} 258296465Sdelphij 259296465Sdelphijvoid 260296465SdelphijARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 261296465Sdelphij MachineFunction &MF) const { 262296465Sdelphij MachineRegisterInfo *MRI = &MF.getRegInfo(); 263296465Sdelphij std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 264296465Sdelphij if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 265296465Sdelphij Hint.first == (unsigned)ARMRI::RegPairEven) && 266296465Sdelphij TargetRegisterInfo::isVirtualRegister(Hint.second)) { 267296465Sdelphij // If 'Reg' is one of the even / odd register pair and it's now changed 268193645Ssimon // (e.g. coalesced) into a different register. The other register of the 269296465Sdelphij // pair allocation hint must be updated to reflect the relationship 270296465Sdelphij // change. 271296465Sdelphij unsigned OtherReg = Hint.second; 272296465Sdelphij Hint = MRI->getRegAllocationHint(OtherReg); 273296465Sdelphij if (Hint.second == Reg) 274296465Sdelphij // Make sure the pair has not already divorced. 275296465Sdelphij MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 276296465Sdelphij } 277296465Sdelphij} 278193645Ssimon 279205128Ssimonbool 280296465SdelphijARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 281193645Ssimon // CortexA9 has a Write-after-write hazard for NEON registers. 282193645Ssimon if (!STI.isLikeA9()) 283193645Ssimon return false; 284296465Sdelphij 285193645Ssimon switch (RC->getID()) { 286296465Sdelphij case ARM::DPRRegClassID: 287296465Sdelphij case ARM::DPR_8RegClassID: 288296465Sdelphij case ARM::DPR_VFP2RegClassID: 289296465Sdelphij case ARM::QPRRegClassID: 290296465Sdelphij case ARM::QPR_8RegClassID: 291296465Sdelphij case ARM::QPR_VFP2RegClassID: 292296465Sdelphij case ARM::SPRRegClassID: 293296465Sdelphij case ARM::SPR_8RegClassID: 294296465Sdelphij // Avoid reusing S, D, and Q registers. 295296465Sdelphij // Don't increase register pressure for QQ and QQQQ. 296193645Ssimon return true; 297296465Sdelphij default: 298296465Sdelphij return false; 299296465Sdelphij } 300296465Sdelphij} 301296465Sdelphij 302296465Sdelphijbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 303296465Sdelphij const MachineFrameInfo *MFI = MF.getFrameInfo(); 304296465Sdelphij const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 305296465Sdelphij const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 306296465Sdelphij 307296465Sdelphij // When outgoing call frames are so large that we adjust the stack pointer 308193645Ssimon // around the call, we can no longer use the stack pointer to reach the 309296465Sdelphij // emergency spill slot. 310296465Sdelphij if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 311296465Sdelphij return true; 312296465Sdelphij 313296465Sdelphij // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 314193645Ssimon // negative range for ldr/str (255), and thumb1 is positive offsets only. 315296465Sdelphij // It's going to be better to use the SP or Base Pointer instead. When there 316296465Sdelphij // are variable sized objects, we can't reference off of the SP, so we 317296465Sdelphij // reserve a Base Pointer. 318296465Sdelphij if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 319296465Sdelphij // Conservatively estimate whether the negative offset from the frame 320193645Ssimon // pointer will be sufficient to reach. If a function has a smallish 321296465Sdelphij // frame, it's less likely to have lots of spills and callee saved 322193645Ssimon // space, so it's all more likely to be within range of the frame pointer. 323205128Ssimon // If it's wrong, the scavenger will still enable access to work, it just 324296465Sdelphij // won't be optimal. 325193645Ssimon if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 326193645Ssimon return false; 327193645Ssimon return true; 328296465Sdelphij } 329296465Sdelphij 330193645Ssimon return false; 331296465Sdelphij} 332296465Sdelphij 333296465Sdelphijbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 334296465Sdelphij const MachineRegisterInfo *MRI = &MF.getRegInfo(); 335296465Sdelphij const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 336296465Sdelphij // We can't realign the stack if: 337296465Sdelphij // 1. Dynamic stack realignment is explicitly disabled, 338296465Sdelphij // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 339296465Sdelphij // 3. There are VLAs in the function and the base pointer is disabled. 340296465Sdelphij if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 341296465Sdelphij return false; 342296465Sdelphij if (AFI->isThumb1OnlyFunction()) 343296465Sdelphij return false; 344296465Sdelphij // Stack realignment requires a frame pointer. If we already started 345296465Sdelphij // register allocation with frame pointer elimination, it is too late now. 346296465Sdelphij if (!MRI->canReserveReg(FramePtr)) 347296465Sdelphij return false; 348296465Sdelphij // We may also need a base pointer if there are dynamic allocas or stack 349296465Sdelphij // pointer adjustments around calls. 350296465Sdelphij if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 351296465Sdelphij return true; 352296465Sdelphij // A base pointer is required and allowed. Check that it isn't too late to 353296465Sdelphij // reserve it. 354296465Sdelphij return MRI->canReserveReg(BasePtr); 355296465Sdelphij} 356296465Sdelphij 357296465Sdelphijbool ARMBaseRegisterInfo:: 358296465SdelphijneedsStackRealignment(const MachineFunction &MF) const { 359296465Sdelphij const MachineFrameInfo *MFI = MF.getFrameInfo(); 360193645Ssimon const Function *F = MF.getFunction(); 361296465Sdelphij unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 362296465Sdelphij bool requiresRealignment = 363193645Ssimon ((MFI->getMaxAlignment() > StackAlign) || 364296465Sdelphij F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 365296465Sdelphij Attribute::StackAlignment)); 366296465Sdelphij 367296465Sdelphij return requiresRealignment && canRealignStack(MF); 368296465Sdelphij} 369296465Sdelphij 370296465Sdelphijbool ARMBaseRegisterInfo:: 371193645SsimoncannotEliminateFrame(const MachineFunction &MF) const { 372296465Sdelphij const MachineFrameInfo *MFI = MF.getFrameInfo(); 373296465Sdelphij if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 374296465Sdelphij return true; 375193645Ssimon return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 376296465Sdelphij || needsStackRealignment(MF); 377296465Sdelphij} 378193645Ssimon 379296465Sdelphijunsigned 380296465SdelphijARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 381296465Sdelphij const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 382296465Sdelphij 383296465Sdelphij if (TFI->hasFP(MF)) 384296465Sdelphij return FramePtr; 385193645Ssimon return ARM::SP; 386296465Sdelphij} 387296465Sdelphij 388296465Sdelphij/// emitLoadConstPool - Emits a load from constpool to materialize the 389193645Ssimon/// specified immediate. 390205128Ssimonvoid ARMBaseRegisterInfo:: 391296465SdelphijemitLoadConstPool(MachineBasicBlock &MBB, 392296465Sdelphij MachineBasicBlock::iterator &MBBI, 393193645Ssimon DebugLoc dl, 394193645Ssimon unsigned DestReg, unsigned SubIdx, int Val, 395193645Ssimon ARMCC::CondCodes Pred, 396193645Ssimon unsigned PredReg, unsigned MIFlags) const { 397296465Sdelphij MachineFunction &MF = *MBB.getParent(); 398193645Ssimon const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 399193645Ssimon MachineConstantPool *ConstantPool = MF.getConstantPool(); 400193645Ssimon const Constant *C = 401193645Ssimon ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 402193645Ssimon unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 403296465Sdelphij 404296465Sdelphij BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 405296465Sdelphij .addReg(DestReg, getDefRegState(true), SubIdx) 406296465Sdelphij .addConstantPoolIndex(Idx) 407296465Sdelphij .addImm(0).addImm(Pred).addReg(PredReg) 408296465Sdelphij .setMIFlags(MIFlags); 409296465Sdelphij} 410296465Sdelphij 411296465Sdelphijbool ARMBaseRegisterInfo:: 412296465SdelphijrequiresRegisterScavenging(const MachineFunction &MF) const { 413296465Sdelphij return true; 414296465Sdelphij} 415296465Sdelphij 416296465Sdelphijbool ARMBaseRegisterInfo:: 417296465SdelphijtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 418296465Sdelphij return true; 419193645Ssimon} 420296465Sdelphij 421296465Sdelphijbool ARMBaseRegisterInfo:: 422296465SdelphijrequiresFrameIndexScavenging(const MachineFunction &MF) const { 423296465Sdelphij return true; 424296465Sdelphij} 425296465Sdelphij 426296465Sdelphijbool ARMBaseRegisterInfo:: 427296465SdelphijrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 428296465Sdelphij return true; 429296465Sdelphij} 430296465Sdelphij 431296465Sdelphijint64_t ARMBaseRegisterInfo:: 432296465SdelphijgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 433296465Sdelphij const MCInstrDesc &Desc = MI->getDesc(); 434296465Sdelphij unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 435296465Sdelphij int64_t InstrOffs = 0; 436296465Sdelphij int Scale = 1; 437296465Sdelphij unsigned ImmIdx = 0; 438296465Sdelphij switch (AddrMode) { 439296465Sdelphij case ARMII::AddrModeT2_i8: 440296465Sdelphij case ARMII::AddrModeT2_i12: 441296465Sdelphij case ARMII::AddrMode_i12: 442193645Ssimon InstrOffs = MI->getOperand(Idx+1).getImm(); 443296465Sdelphij Scale = 1; 444296465Sdelphij break; 445296465Sdelphij case ARMII::AddrMode5: { 446296465Sdelphij // VFP address mode. 447296465Sdelphij const MachineOperand &OffOp = MI->getOperand(Idx+1); 448296465Sdelphij InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 449296465Sdelphij if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 450296465Sdelphij InstrOffs = -InstrOffs; 451296465Sdelphij Scale = 4; 452296465Sdelphij break; 453296465Sdelphij } 454296465Sdelphij case ARMII::AddrMode2: { 455296465Sdelphij ImmIdx = Idx+2; 456193645Ssimon InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 457296465Sdelphij if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 458193645Ssimon InstrOffs = -InstrOffs; 459296465Sdelphij break; 460296465Sdelphij } 461296465Sdelphij case ARMII::AddrMode3: { 462296465Sdelphij ImmIdx = Idx+2; 463296465Sdelphij InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 464296465Sdelphij if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 465296465Sdelphij InstrOffs = -InstrOffs; 466296465Sdelphij break; 467296465Sdelphij } 468296465Sdelphij case ARMII::AddrModeT1_s: { 469296465Sdelphij ImmIdx = Idx+1; 470296465Sdelphij InstrOffs = MI->getOperand(ImmIdx).getImm(); 471296465Sdelphij Scale = 4; 472296465Sdelphij break; 473296465Sdelphij } 474296465Sdelphij default: 475296465Sdelphij llvm_unreachable("Unsupported addressing mode!"); 476296465Sdelphij } 477296465Sdelphij 478296465Sdelphij return InstrOffs * Scale; 479296465Sdelphij} 480296465Sdelphij 481296465Sdelphij/// needsFrameBaseReg - Returns true if the instruction's frame index 482296465Sdelphij/// reference would be better served by a base register other than FP 483296465Sdelphij/// or SP. Used by LocalStackFrameAllocation to determine which frame index 484296465Sdelphij/// references it should create new base registers for. 485296465Sdelphijbool ARMBaseRegisterInfo:: 486296465SdelphijneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 487296465Sdelphij for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 488193645Ssimon assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 489193645Ssimon } 490296465Sdelphij 491193645Ssimon // It's the load/store FI references that cause issues, as it can be difficult 492193645Ssimon // to materialize the offset if it won't fit in the literal field. Estimate 493 // based on the size of the local frame and some conservative assumptions 494 // about the rest of the stack frame (note, this is pre-regalloc, so 495 // we don't know everything for certain yet) whether this offset is likely 496 // to be out of range of the immediate. Return true if so. 497 498 // We only generate virtual base registers for loads and stores, so 499 // return false for everything else. 500 unsigned Opc = MI->getOpcode(); 501 switch (Opc) { 502 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 503 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 504 case ARM::t2LDRi12: case ARM::t2LDRi8: 505 case ARM::t2STRi12: case ARM::t2STRi8: 506 case ARM::VLDRS: case ARM::VLDRD: 507 case ARM::VSTRS: case ARM::VSTRD: 508 case ARM::tSTRspi: case ARM::tLDRspi: 509 break; 510 default: 511 return false; 512 } 513 514 // Without a virtual base register, if the function has variable sized 515 // objects, all fixed-size local references will be via the frame pointer, 516 // Approximate the offset and see if it's legal for the instruction. 517 // Note that the incoming offset is based on the SP value at function entry, 518 // so it'll be negative. 519 MachineFunction &MF = *MI->getParent()->getParent(); 520 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 521 MachineFrameInfo *MFI = MF.getFrameInfo(); 522 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 523 524 // Estimate an offset from the frame pointer. 525 // Conservatively assume all callee-saved registers get pushed. R4-R6 526 // will be earlier than the FP, so we ignore those. 527 // R7, LR 528 int64_t FPOffset = Offset - 8; 529 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 530 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 531 FPOffset -= 80; 532 // Estimate an offset from the stack pointer. 533 // The incoming offset is relating to the SP at the start of the function, 534 // but when we access the local it'll be relative to the SP after local 535 // allocation, so adjust our SP-relative offset by that allocation size. 536 Offset = -Offset; 537 Offset += MFI->getLocalFrameSize(); 538 // Assume that we'll have at least some spill slots allocated. 539 // FIXME: This is a total SWAG number. We should run some statistics 540 // and pick a real one. 541 Offset += 128; // 128 bytes of spill slots 542 543 // If there is a frame pointer, try using it. 544 // The FP is only available if there is no dynamic realignment. We 545 // don't know for sure yet whether we'll need that, so we guess based 546 // on whether there are any local variables that would trigger it. 547 unsigned StackAlign = TFI->getStackAlignment(); 548 if (TFI->hasFP(MF) && 549 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 550 if (isFrameOffsetLegal(MI, FPOffset)) 551 return false; 552 } 553 // If we can reference via the stack pointer, try that. 554 // FIXME: This (and the code that resolves the references) can be improved 555 // to only disallow SP relative references in the live range of 556 // the VLA(s). In practice, it's unclear how much difference that 557 // would make, but it may be worth doing. 558 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 559 return false; 560 561 // The offset likely isn't legal, we want to allocate a virtual base register. 562 return true; 563} 564 565/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 566/// be a pointer to FrameIdx at the beginning of the basic block. 567void ARMBaseRegisterInfo:: 568materializeFrameBaseRegister(MachineBasicBlock *MBB, 569 unsigned BaseReg, int FrameIdx, 570 int64_t Offset) const { 571 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 572 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 573 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 574 575 MachineBasicBlock::iterator Ins = MBB->begin(); 576 DebugLoc DL; // Defaults to "unknown" 577 if (Ins != MBB->end()) 578 DL = Ins->getDebugLoc(); 579 580 const MachineFunction &MF = *MBB->getParent(); 581 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 582 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 583 const MCInstrDesc &MCID = TII.get(ADDriOpc); 584 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 585 586 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 587 .addFrameIndex(FrameIdx).addImm(Offset)); 588 589 if (!AFI->isThumb1OnlyFunction()) 590 AddDefaultCC(MIB); 591} 592 593void 594ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 595 unsigned BaseReg, int64_t Offset) const { 596 MachineInstr &MI = *I; 597 MachineBasicBlock &MBB = *MI.getParent(); 598 MachineFunction &MF = *MBB.getParent(); 599 const ARMBaseInstrInfo &TII = 600 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 601 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 602 int Off = Offset; // ARM doesn't need the general 64-bit offsets 603 unsigned i = 0; 604 605 assert(!AFI->isThumb1OnlyFunction() && 606 "This resolveFrameIndex does not support Thumb1!"); 607 608 while (!MI.getOperand(i).isFI()) { 609 ++i; 610 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 611 } 612 bool Done = false; 613 if (!AFI->isThumbFunction()) 614 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 615 else { 616 assert(AFI->isThumb2Function()); 617 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 618 } 619 assert (Done && "Unable to resolve frame index!"); 620 (void)Done; 621} 622 623bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 624 int64_t Offset) const { 625 const MCInstrDesc &Desc = MI->getDesc(); 626 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 627 unsigned i = 0; 628 629 while (!MI->getOperand(i).isFI()) { 630 ++i; 631 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 632 } 633 634 // AddrMode4 and AddrMode6 cannot handle any offset. 635 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 636 return Offset == 0; 637 638 unsigned NumBits = 0; 639 unsigned Scale = 1; 640 bool isSigned = true; 641 switch (AddrMode) { 642 case ARMII::AddrModeT2_i8: 643 case ARMII::AddrModeT2_i12: 644 // i8 supports only negative, and i12 supports only positive, so 645 // based on Offset sign, consider the appropriate instruction 646 Scale = 1; 647 if (Offset < 0) { 648 NumBits = 8; 649 Offset = -Offset; 650 } else { 651 NumBits = 12; 652 } 653 break; 654 case ARMII::AddrMode5: 655 // VFP address mode. 656 NumBits = 8; 657 Scale = 4; 658 break; 659 case ARMII::AddrMode_i12: 660 case ARMII::AddrMode2: 661 NumBits = 12; 662 break; 663 case ARMII::AddrMode3: 664 NumBits = 8; 665 break; 666 case ARMII::AddrModeT1_s: 667 NumBits = 5; 668 Scale = 4; 669 isSigned = false; 670 break; 671 default: 672 llvm_unreachable("Unsupported addressing mode!"); 673 } 674 675 Offset += getFrameIndexInstrOffset(MI, i); 676 // Make sure the offset is encodable for instructions that scale the 677 // immediate. 678 if ((Offset & (Scale-1)) != 0) 679 return false; 680 681 if (isSigned && Offset < 0) 682 Offset = -Offset; 683 684 unsigned Mask = (1 << NumBits) - 1; 685 if ((unsigned)Offset <= Mask * Scale) 686 return true; 687 688 return false; 689} 690 691void 692ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 693 int SPAdj, unsigned FIOperandNum, 694 RegScavenger *RS) const { 695 MachineInstr &MI = *II; 696 MachineBasicBlock &MBB = *MI.getParent(); 697 MachineFunction &MF = *MBB.getParent(); 698 const ARMBaseInstrInfo &TII = 699 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 700 const ARMFrameLowering *TFI = 701 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 702 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 703 assert(!AFI->isThumb1OnlyFunction() && 704 "This eliminateFrameIndex does not support Thumb1!"); 705 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 706 unsigned FrameReg; 707 708 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 709 710 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 711 // call frame setup/destroy instructions have already been eliminated. That 712 // means the stack pointer cannot be used to access the emergency spill slot 713 // when !hasReservedCallFrame(). 714#ifndef NDEBUG 715 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 716 assert(TFI->hasReservedCallFrame(MF) && 717 "Cannot use SP to access the emergency spill slot in " 718 "functions without a reserved call frame"); 719 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 720 "Cannot use SP to access the emergency spill slot in " 721 "functions with variable sized frame objects"); 722 } 723#endif // NDEBUG 724 725 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 726 727 // Modify MI as necessary to handle as much of 'Offset' as possible 728 bool Done = false; 729 if (!AFI->isThumbFunction()) 730 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 731 else { 732 assert(AFI->isThumb2Function()); 733 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 734 } 735 if (Done) 736 return; 737 738 // If we get here, the immediate doesn't fit into the instruction. We folded 739 // as much as possible above, handle the rest, providing a register that is 740 // SP+LargeImm. 741 assert((Offset || 742 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 743 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 744 "This code isn't needed if offset already handled!"); 745 746 unsigned ScratchReg = 0; 747 int PIdx = MI.findFirstPredOperandIdx(); 748 ARMCC::CondCodes Pred = (PIdx == -1) 749 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 750 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 751 if (Offset == 0) 752 // Must be addrmode4/6. 753 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 754 else { 755 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 756 if (!AFI->isThumbFunction()) 757 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 758 Offset, Pred, PredReg, TII); 759 else { 760 assert(AFI->isThumb2Function()); 761 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 762 Offset, Pred, PredReg, TII); 763 } 764 // Update the original instruction to use the scratch register. 765 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 766 } 767} 768