1234353Sdim//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed// Target-independent interfaces which we are implementing 15193323Sed//===----------------------------------------------------------------------===// 16193323Sed 17193323Sedinclude "llvm/Target/Target.td" 18193323Sed 19224145Sdim//===----------------------------------------------------------------------===// 20224145Sdim// ARM Subtarget state. 21224145Sdim// 22218893Sdim 23224145Sdimdef ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", 24224145Sdim "Thumb mode">; 25224145Sdim 26193323Sed//===----------------------------------------------------------------------===// 27193323Sed// ARM Subtarget features. 28193323Sed// 29193323Sed 30224145Sdimdef FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", 31193323Sed "Enable VFP2 instructions">; 32224145Sdimdef FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true", 33224145Sdim "Enable VFP3 instructions", 34224145Sdim [FeatureVFP2]>; 35224145Sdimdef FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 36224145Sdim "Enable NEON instructions", 37224145Sdim [FeatureVFP3]>; 38224145Sdimdef FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", 39193323Sed "Enable Thumb2 instructions">; 40212904Sdimdef FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", 41263508Sdim "Does not support ARM mode execution", 42263508Sdim [ModeThumb]>; 43205218Srdivackydef FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 44205218Srdivacky "Enable half-precision floating point">; 45243830Sdimdef FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", 46243830Sdim "Enable VFP4 instructions", 47243830Sdim [FeatureVFP3, FeatureFP16]>; 48263508Sdimdef FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", 49263508Sdim "true", "Enable ARMv8 FP", 50263508Sdim [FeatureVFP4]>; 51218893Sdimdef FeatureD16 : SubtargetFeature<"d16", "HasD16", "true", 52218893Sdim "Restrict VFP3 to 16 double registers">; 53208599Srdivackydef FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", 54208599Srdivacky "Enable divide instructions">; 55243830Sdimdef FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", 56243830Sdim "HasHardwareDivideInARM", "true", 57243830Sdim "Enable divide instructions in ARM mode">; 58212904Sdimdef FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", 59208599Srdivacky "Enable Thumb2 extract and pack instructions">; 60212904Sdimdef FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", 61212904Sdim "Has data barrier (dmb / dsb) instructions">; 62210299Seddef FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", 63210299Sed "FP compare + branch is slow">; 64212904Sdimdef FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true", 65212904Sdim "Floating point unit supports single precision only">; 66263508Sdimdef FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 67263508Sdim "Enable support for Performance Monitor extensions">; 68251662Sdimdef FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", 69251662Sdim "Enable support for TrustZone security extensions">; 70263508Sdimdef FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 71263508Sdim "Enable support for Cryptography extensions", 72263508Sdim [FeatureNEON]>; 73263508Sdimdef FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 74263508Sdim "Enable support for CRC instructions">; 75193323Sed 76218893Sdim// Some processors have FP multiply-accumulate instructions that don't 77218893Sdim// play nicely with other VFP / NEON instructions, and it's generally better 78206083Srdivacky// to just not use them. 79218893Sdimdef FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", 80218893Sdim "Disable VFP / NEON MAC instructions">; 81221345Sdim 82221345Sdim// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. 83221345Sdimdef FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", 84221345Sdim "HasVMLxForwarding", "true", 85221345Sdim "Has multiplier accumulator forwarding">; 86221345Sdim 87206083Srdivacky// Some processors benefit from using NEON instructions for scalar 88206083Srdivacky// single-precision FP operations. 89206083Srdivackydef FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 90206083Srdivacky "true", 91206083Srdivacky "Use NEON for single precision FP">; 92206083Srdivacky 93212904Sdim// Disable 32-bit to 16-bit narrowing for experimentation. 94212904Sdimdef FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", 95212904Sdim "Prefer 32-bit Thumb instrs">; 96206083Srdivacky 97221345Sdim/// Some instructions update CPSR partially, which can add false dependency for 98221345Sdim/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is 99221345Sdim/// mapped to a separate physical register. Avoid partial CPSR update for these 100221345Sdim/// processors. 101221345Sdimdef FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", 102221345Sdim "AvoidCPSRPartialUpdate", "true", 103221345Sdim "Avoid CPSR partial update for OOO execution">; 104221345Sdim 105249423Sdimdef FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", 106249423Sdim "AvoidMOVsShifterOperand", "true", 107249423Sdim "Avoid movs instructions with shifter operand">; 108249423Sdim 109234353Sdim// Some processors perform return stack prediction. CodeGen should avoid issue 110234353Sdim// "normal" call instructions to callees which do not return. 111234353Sdimdef FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true", 112234353Sdim "Has return address stack">; 113234353Sdim 114224145Sdim/// Some M architectures don't have the DSP extension (v7E-M vs. v7M) 115224145Sdimdef FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true", 116226633Sdim "Supports v7 DSP instructions in Thumb2">; 117224145Sdim 118218893Sdim// Multiprocessing extension. 119218893Sdimdef FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", 120218893Sdim "Supports Multiprocessing extension">; 121212904Sdim 122263508Sdim// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). 123263508Sdimdef FeatureVirtualization : SubtargetFeature<"virtualization", 124263508Sdim "HasVirtualization", "true", 125263508Sdim "Supports Virtualization extension", 126263508Sdim [FeatureHWDiv, FeatureHWDivARM]>; 127263508Sdim 128263508Sdim// M-series ISA 129263508Sdimdef FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", 130226633Sdim "Is microcontroller profile ('M' series)">; 131226633Sdim 132263508Sdim// R-series ISA 133263508Sdimdef FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", 134263508Sdim "Is realtime profile ('R' series)">; 135263508Sdim 136263508Sdim// A-series ISA 137263508Sdimdef FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", 138263508Sdim "Is application profile ('A' series)">; 139263508Sdim 140249423Sdim// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. 141249423Sdim// See ARMInstrInfo.td for details. 142249423Sdimdef FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", 143249423Sdim "NaCl trap">; 144249423Sdim 145224145Sdim// ARM ISAs. 146224145Sdimdef HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", 147224145Sdim "Support ARM v4T instructions">; 148224145Sdimdef HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", 149224145Sdim "Support ARM v5T instructions", 150224145Sdim [HasV4TOps]>; 151224145Sdimdef HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", 152224145Sdim "Support ARM v5TE, v5TEj, and v5TExp instructions", 153224145Sdim [HasV5TOps]>; 154224145Sdimdef HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", 155224145Sdim "Support ARM v6 instructions", 156224145Sdim [HasV5TEOps]>; 157263508Sdimdef HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", 158263508Sdim "Support ARM v6M instructions", 159263508Sdim [HasV6Ops]>; 160224145Sdimdef HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", 161224145Sdim "Support ARM v6t2 instructions", 162263508Sdim [HasV6MOps, FeatureThumb2]>; 163224145Sdimdef HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", 164224145Sdim "Support ARM v7 instructions", 165263508Sdim [HasV6T2Ops, FeaturePerfMon]>; 166263508Sdimdef HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", 167263508Sdim "Support ARM v8 instructions", 168263508Sdim [HasV7Ops, FeatureVirtualization, 169263508Sdim FeatureMP]>; 170212904Sdim 171193323Sed//===----------------------------------------------------------------------===// 172193323Sed// ARM Processors supported. 173193323Sed// 174193323Sed 175194612Sedinclude "ARMSchedule.td" 176193323Sed 177218893Sdim// ARM processor families. 178249423Sdimdef ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", 179249423Sdim "Cortex-A5 ARM processors", 180249423Sdim [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, 181251662Sdim FeatureVMLxForwarding, FeatureT2XtPk, 182251662Sdim FeatureTrustZone]>; 183218893Sdimdef ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", 184218893Sdim "Cortex-A8 ARM processors", 185249423Sdim [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, 186251662Sdim FeatureVMLxForwarding, FeatureT2XtPk, 187251662Sdim FeatureTrustZone]>; 188218893Sdimdef ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", 189218893Sdim "Cortex-A9 ARM processors", 190221345Sdim [FeatureVMLxForwarding, 191221345Sdim FeatureT2XtPk, FeatureFP16, 192251662Sdim FeatureAvoidPartialCPSR, 193251662Sdim FeatureTrustZone]>; 194243830Sdimdef ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", 195243830Sdim "Swift ARM processors", 196243830Sdim [FeatureNEONForFP, FeatureT2XtPk, 197243830Sdim FeatureVFP4, FeatureMP, FeatureHWDiv, 198243830Sdim FeatureHWDivARM, FeatureAvoidPartialCPSR, 199249423Sdim FeatureAvoidMOVsShOp, 200251662Sdim FeatureHasSlowFPVMLx, FeatureTrustZone]>; 201218893Sdim 202243830Sdim// FIXME: It has not been determined if A15 has these features. 203243830Sdimdef ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", 204243830Sdim "Cortex-A15 ARM processors", 205263508Sdim [FeatureT2XtPk, FeatureVFP4, 206263508Sdim FeatureMP, FeatureHWDiv, FeatureHWDivARM, 207251662Sdim FeatureAvoidPartialCPSR, 208263508Sdim FeatureTrustZone, FeatureVirtualization]>; 209263508Sdim 210263508Sdimdef ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 211263508Sdim "Cortex-A53 ARM processors", 212263508Sdim [FeatureHWDiv, FeatureHWDivARM, 213263508Sdim FeatureTrustZone, FeatureT2XtPk, 214263508Sdim FeatureCrypto, FeatureCRC]>; 215263508Sdim 216263508Sdimdef ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 217263508Sdim "Cortex-A57 ARM processors", 218263508Sdim [FeatureHWDiv, FeatureHWDivARM, 219263508Sdim FeatureTrustZone, FeatureT2XtPk, 220263508Sdim FeatureCrypto, FeatureCRC]>; 221263508Sdim 222249423Sdimdef ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", 223249423Sdim "Cortex-R5 ARM processors", 224263508Sdim [FeatureSlowFPBrcc, 225263508Sdim FeatureHWDiv, FeatureHWDivARM, 226249423Sdim FeatureHasSlowFPVMLx, 227249423Sdim FeatureAvoidPartialCPSR, 228249423Sdim FeatureT2XtPk]>; 229243830Sdim 230194612Sedclass ProcNoItin<string Name, list<SubtargetFeature> Features> 231239462Sdim : Processor<Name, NoItineraries, Features>; 232194612Sed 233193323Sed// V4 Processors. 234194612Seddef : ProcNoItin<"generic", []>; 235194612Seddef : ProcNoItin<"arm8", []>; 236194612Seddef : ProcNoItin<"arm810", []>; 237194612Seddef : ProcNoItin<"strongarm", []>; 238194612Seddef : ProcNoItin<"strongarm110", []>; 239194612Seddef : ProcNoItin<"strongarm1100", []>; 240194612Seddef : ProcNoItin<"strongarm1110", []>; 241193323Sed 242193323Sed// V4T Processors. 243224145Sdimdef : ProcNoItin<"arm7tdmi", [HasV4TOps]>; 244224145Sdimdef : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>; 245224145Sdimdef : ProcNoItin<"arm710t", [HasV4TOps]>; 246224145Sdimdef : ProcNoItin<"arm720t", [HasV4TOps]>; 247224145Sdimdef : ProcNoItin<"arm9", [HasV4TOps]>; 248224145Sdimdef : ProcNoItin<"arm9tdmi", [HasV4TOps]>; 249224145Sdimdef : ProcNoItin<"arm920", [HasV4TOps]>; 250224145Sdimdef : ProcNoItin<"arm920t", [HasV4TOps]>; 251224145Sdimdef : ProcNoItin<"arm922t", [HasV4TOps]>; 252224145Sdimdef : ProcNoItin<"arm940t", [HasV4TOps]>; 253224145Sdimdef : ProcNoItin<"ep9312", [HasV4TOps]>; 254193323Sed 255193323Sed// V5T Processors. 256224145Sdimdef : ProcNoItin<"arm10tdmi", [HasV5TOps]>; 257224145Sdimdef : ProcNoItin<"arm1020t", [HasV5TOps]>; 258193323Sed 259193323Sed// V5TE Processors. 260224145Sdimdef : ProcNoItin<"arm9e", [HasV5TEOps]>; 261224145Sdimdef : ProcNoItin<"arm926ej-s", [HasV5TEOps]>; 262224145Sdimdef : ProcNoItin<"arm946e-s", [HasV5TEOps]>; 263224145Sdimdef : ProcNoItin<"arm966e-s", [HasV5TEOps]>; 264224145Sdimdef : ProcNoItin<"arm968e-s", [HasV5TEOps]>; 265224145Sdimdef : ProcNoItin<"arm10e", [HasV5TEOps]>; 266224145Sdimdef : ProcNoItin<"arm1020e", [HasV5TEOps]>; 267224145Sdimdef : ProcNoItin<"arm1022e", [HasV5TEOps]>; 268224145Sdimdef : ProcNoItin<"xscale", [HasV5TEOps]>; 269224145Sdimdef : ProcNoItin<"iwmmxt", [HasV5TEOps]>; 270193323Sed 271193323Sed// V6 Processors. 272224145Sdimdef : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>; 273224145Sdimdef : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 274218893Sdim FeatureHasSlowFPVMLx]>; 275224145Sdimdef : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>; 276224145Sdimdef : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 277218893Sdim FeatureHasSlowFPVMLx]>; 278224145Sdimdef : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>; 279224145Sdimdef : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, 280218893Sdim FeatureHasSlowFPVMLx]>; 281193323Sed 282212904Sdim// V6M Processors. 283263508Sdimdef : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, 284226633Sdim FeatureDB, FeatureMClass]>; 285212904Sdim 286194178Sed// V6T2 Processors. 287226633Sdimdef : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops, 288226633Sdim FeatureDSPThumb2]>; 289224145Sdimdef : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2, 290226633Sdim FeatureHasSlowFPVMLx, 291226633Sdim FeatureDSPThumb2]>; 292193323Sed 293224145Sdim// V7a Processors. 294249423Sdim// FIXME: A5 has currently the same Schedule model as A8 295249423Sdimdef : ProcessorModel<"cortex-a5", CortexA8Model, 296249423Sdim [ProcA5, HasV7Ops, FeatureNEON, FeatureDB, 297249423Sdim FeatureVFP4, FeatureDSPThumb2, 298263508Sdim FeatureHasRAS, FeatureAClass]>; 299239462Sdimdef : ProcessorModel<"cortex-a8", CortexA8Model, 300224145Sdim [ProcA8, HasV7Ops, FeatureNEON, FeatureDB, 301263508Sdim FeatureDSPThumb2, FeatureHasRAS, 302263508Sdim FeatureAClass]>; 303239462Sdimdef : ProcessorModel<"cortex-a9", CortexA9Model, 304224145Sdim [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 305263508Sdim FeatureDSPThumb2, FeatureHasRAS, 306263508Sdim FeatureAClass]>; 307239462Sdimdef : ProcessorModel<"cortex-a9-mp", CortexA9Model, 308224145Sdim [ProcA9, HasV7Ops, FeatureNEON, FeatureDB, 309234353Sdim FeatureDSPThumb2, FeatureMP, 310263508Sdim FeatureHasRAS, FeatureAClass]>; 311243830Sdim// FIXME: A15 has currently the same ProcessorModel as A9. 312243830Sdimdef : ProcessorModel<"cortex-a15", CortexA9Model, 313243830Sdim [ProcA15, HasV7Ops, FeatureNEON, FeatureDB, 314263508Sdim FeatureDSPThumb2, FeatureHasRAS, 315263508Sdim FeatureAClass]>; 316249423Sdim// FIXME: R5 has currently the same ProcessorModel as A8. 317249423Sdimdef : ProcessorModel<"cortex-r5", CortexA8Model, 318249423Sdim [ProcR5, HasV7Ops, FeatureDB, 319249423Sdim FeatureVFP3, FeatureDSPThumb2, 320263508Sdim FeatureHasRAS, FeatureVFPOnlySP, 321263508Sdim FeatureD16, FeatureRClass]>; 322193323Sed 323212904Sdim// V7M Processors. 324224145Sdimdef : ProcNoItin<"cortex-m3", [HasV7Ops, 325224145Sdim FeatureThumb2, FeatureNoARM, FeatureDB, 326226633Sdim FeatureHWDiv, FeatureMClass]>; 327212904Sdim 328224145Sdim// V7EM Processors. 329224145Sdimdef : ProcNoItin<"cortex-m4", [HasV7Ops, 330224145Sdim FeatureThumb2, FeatureNoARM, FeatureDB, 331224145Sdim FeatureHWDiv, FeatureDSPThumb2, 332239462Sdim FeatureT2XtPk, FeatureVFP4, 333263508Sdim FeatureVFPOnlySP, FeatureD16, 334263508Sdim FeatureMClass]>; 335224145Sdim 336243830Sdim// Swift uArch Processors. 337243830Sdimdef : ProcessorModel<"swift", SwiftModel, 338243830Sdim [ProcSwift, HasV7Ops, FeatureNEON, 339243830Sdim FeatureDB, FeatureDSPThumb2, 340263508Sdim FeatureHasRAS, FeatureAClass]>; 341243830Sdim 342263508Sdim// V8 Processors 343263508Sdimdef : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, 344263508Sdim FeatureDB, FeatureFPARMv8, 345263508Sdim FeatureNEON, FeatureDSPThumb2]>; 346263508Sdimdef : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass, 347263508Sdim FeatureDB, FeatureFPARMv8, 348263508Sdim FeatureNEON, FeatureDSPThumb2]>; 349263508Sdim 350193323Sed//===----------------------------------------------------------------------===// 351193323Sed// Register File Description 352193323Sed//===----------------------------------------------------------------------===// 353193323Sed 354193323Sedinclude "ARMRegisterInfo.td" 355193323Sed 356193323Sedinclude "ARMCallingConv.td" 357193323Sed 358193323Sed//===----------------------------------------------------------------------===// 359193323Sed// Instruction Descriptions 360193323Sed//===----------------------------------------------------------------------===// 361193323Sed 362193323Sedinclude "ARMInstrInfo.td" 363193323Sed 364206274Srdivackydef ARMInstrInfo : InstrInfo; 365193323Sed 366218893Sdim 367193323Sed//===----------------------------------------------------------------------===// 368218893Sdim// Assembly printer 369218893Sdim//===----------------------------------------------------------------------===// 370218893Sdim// ARM Uses the MC printer for asm output, so make sure the TableGen 371218893Sdim// AsmWriter bits get associated with the correct class. 372218893Sdimdef ARMAsmWriter : AsmWriter { 373218893Sdim string AsmWriterClassName = "InstPrinter"; 374218893Sdim bit isMCAsmWriter = 1; 375218893Sdim} 376218893Sdim 377218893Sdim//===----------------------------------------------------------------------===// 378193323Sed// Declare the target which we are implementing 379193323Sed//===----------------------------------------------------------------------===// 380193323Sed 381193323Seddef ARM : Target { 382193323Sed // Pull in Instruction Info: 383193323Sed let InstructionSet = ARMInstrInfo; 384218893Sdim 385218893Sdim let AssemblyWriters = [ARMAsmWriter]; 386193323Sed} 387