AArch64InstrInfo.td revision 263508
1249259Sdim//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file describes the AArch64 scalar instructions in TableGen format. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14263508Sdim//===----------------------------------------------------------------------===// 15263508Sdim// ARM Instruction Predicate Definitions. 16263508Sdim// 17263508Sdimdef HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 18263508Sdim AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; 19263508Sdimdef HasNEON : Predicate<"Subtarget->hasNEON()">, 20263508Sdim AssemblerPredicate<"FeatureNEON", "neon">; 21263508Sdimdef HasCrypto : Predicate<"Subtarget->hasCrypto()">, 22263508Sdim AssemblerPredicate<"FeatureCrypto","crypto">; 23263508Sdim 24263508Sdim// Use fused MAC if more precision in FP computation is allowed. 25263508Sdimdef UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 26263508Sdim " FPOpFusion::Fast)">; 27249259Sdiminclude "AArch64InstrFormats.td" 28249259Sdim 29249259Sdim//===----------------------------------------------------------------------===// 30249259Sdim// Target-specific ISD nodes and profiles 31249259Sdim//===----------------------------------------------------------------------===// 32249259Sdim 33249259Sdimdef SDT_A64ret : SDTypeProfile<0, 0, []>; 34249259Sdimdef A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain, 35249259Sdim SDNPOptInGlue, 36249259Sdim SDNPVariadic]>; 37249259Sdim 38249259Sdim// (ins NZCV, Condition, Dest) 39249259Sdimdef SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>; 40249259Sdimdef A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>; 41249259Sdim 42249259Sdim// (outs Result), (ins NZCV, IfTrue, IfFalse, Condition) 43249259Sdimdef SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>, 44249259Sdim SDTCisSameAs<0, 2>, 45249259Sdim SDTCisSameAs<2, 3>]>; 46249259Sdimdef A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>; 47249259Sdim 48249259Sdim// (outs NZCV), (ins LHS, RHS, Condition) 49249259Sdimdef SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 50249259Sdim SDTCisSameAs<1, 2>]>; 51249259Sdimdef A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>; 52249259Sdim 53249259Sdim 54249259Sdim// (outs GPR64), (ins) 55249259Sdimdef A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 56249259Sdim 57249259Sdim// A64 compares don't care about the cond really (they set all flags) so a 58249259Sdim// simple binary operator is useful. 59249259Sdimdef A64cmp : PatFrag<(ops node:$lhs, node:$rhs), 60249259Sdim (A64setcc node:$lhs, node:$rhs, cond)>; 61249259Sdim 62249259Sdim 63249259Sdim// When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN 64249259Sdim// instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C 65249259Sdim// and V flags can be set differently by this operation. It comes down to 66249259Sdim// whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are 67249259Sdim// then everything is fine. If not then the optimization is wrong. Thus general 68249259Sdim// comparisons are only valid if op2 != 0. 69249259Sdim 70249259Sdim// So, finally, the only LLVM-native comparisons that don't mention C and V are 71249259Sdim// SETEQ and SETNE. They're the only ones we can safely use CMN for in the 72249259Sdim// absence of information about op2. 73249259Sdimdef equality_cond : PatLeaf<(cond), [{ 74249259Sdim return N->get() == ISD::SETEQ || N->get() == ISD::SETNE; 75249259Sdim}]>; 76249259Sdim 77249259Sdimdef A64cmn : PatFrag<(ops node:$lhs, node:$rhs), 78249259Sdim (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>; 79249259Sdim 80249259Sdim// There are two layers of indirection here, driven by the following 81249259Sdim// considerations. 82249259Sdim// + TableGen does not know CodeModel or Reloc so that decision should be 83249259Sdim// made for a variable/address at ISelLowering. 84249259Sdim// + The output of ISelLowering should be selectable (hence the Wrapper, 85249259Sdim// rather than a bare target opcode) 86251662Sdimdef SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 87251662Sdim SDTCisSameAs<0, 2>, 88251662Sdim SDTCisSameAs<0, 3>, 89251662Sdim SDTCisSameAs<0, 4>, 90251662Sdim SDTCisPtrTy<0>]>; 91249259Sdim 92251662Sdimdef A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>; 93249259Sdim 94251662Sdimdef SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 95251662Sdim SDTCisSameAs<1, 2>, 96251662Sdim SDTCisVT<3, i32>, 97251662Sdim SDTCisPtrTy<0>]>; 98249259Sdim 99251662Sdimdef A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>; 100251662Sdim 101251662Sdim 102249259Sdimdef SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 103249259Sdimdef A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad, 104249259Sdim [SDNPHasChain]>; 105249259Sdim 106249259Sdim 107249259Sdim// (A64BFI LHS, RHS, LSB, Width) 108249259Sdimdef SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 109249259Sdim SDTCisSameAs<1, 2>, 110249259Sdim SDTCisVT<3, i64>, 111249259Sdim SDTCisVT<4, i64>]>; 112249259Sdim 113249259Sdimdef A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>; 114249259Sdim 115249259Sdim// (A64EXTR HiReg, LoReg, LSB) 116249259Sdimdef SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 117249259Sdim SDTCisVT<3, i64>]>; 118249259Sdimdef A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>; 119249259Sdim 120249259Sdim// (A64[SU]BFX Field, ImmR, ImmS). 121249259Sdim// 122249259Sdim// Note that ImmR and ImmS are already encoded for the actual instructions. The 123249259Sdim// more natural LSB and Width mix together to form ImmR and ImmS, something 124249259Sdim// which TableGen can't handle. 125249259Sdimdef SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 126249259Sdimdef A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>; 127249259Sdim 128249259Sdimdef A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>; 129249259Sdim 130263508Sdimclass BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 131263508Sdim 132249259Sdim//===----------------------------------------------------------------------===// 133249259Sdim// Call sequence pseudo-instructions 134249259Sdim//===----------------------------------------------------------------------===// 135249259Sdim 136249259Sdim 137249259Sdimdef SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 138249259Sdimdef AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call, 139249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 140249259Sdim 141249259Sdimdef AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call, 142249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143249259Sdim 144249259Sdim// The TLSDESCCALL node is a variant call which goes to an indirectly calculated 145249259Sdim// destination but needs a relocation against a fixed symbol. As such it has two 146249259Sdim// certain operands: the callee and the relocated variable. 147249259Sdim// 148249259Sdim// The TLS ABI only allows it to be selected to a BLR instructin (with 149249259Sdim// appropriate relocation). 150249259Sdimdef SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 151249259Sdim 152249259Sdimdef A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall, 153249259Sdim [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 154249259Sdim SDNPVariadic]>; 155249259Sdim 156249259Sdim 157249259Sdimdef SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>; 158249259Sdimdef AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart, 159249259Sdim [SDNPHasChain, SDNPOutGlue]>; 160249259Sdim 161249259Sdimdef SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>; 162249259Sdimdef AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd, 163249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 164249259Sdim 165249259Sdim 166249259Sdim 167249259Sdim// These pseudo-instructions have special semantics by virtue of being passed to 168249259Sdim// the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by 169249259Sdim// LowerCall to (in our case) tell the back-end about stack adjustments for 170249259Sdim// arguments passed on the stack. Here we select those markers to 171249259Sdim// pseudo-instructions which explicitly set the stack, and finally in the 172249259Sdim// RegisterInfo we convert them to a true stack adjustment. 173249259Sdimlet Defs = [XSP], Uses = [XSP] in { 174249259Sdim def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt), 175249259Sdim [(AArch64callseq_start timm:$amt)]>; 176249259Sdim 177249259Sdim def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2), 178249259Sdim [(AArch64callseq_end timm:$amt1, timm:$amt2)]>; 179249259Sdim} 180249259Sdim 181249259Sdim//===----------------------------------------------------------------------===// 182249259Sdim// Atomic operation pseudo-instructions 183249259Sdim//===----------------------------------------------------------------------===// 184249259Sdim 185251662Sdim// These get selected from C++ code as a pretty much direct translation from the 186251662Sdim// generic DAG nodes. The one exception is the AtomicOrdering is added as an 187251662Sdim// operand so that the eventual lowering can make use of it and choose 188251662Sdim// acquire/release operations when required. 189251662Sdim 190251662Sdimlet usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in { 191251662Sdimmulticlass AtomicSizes { 192251662Sdim def _I8 : PseudoInst<(outs GPR32:$dst), 193251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 194251662Sdim def _I16 : PseudoInst<(outs GPR32:$dst), 195251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 196251662Sdim def _I32 : PseudoInst<(outs GPR32:$dst), 197251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 198251662Sdim def _I64 : PseudoInst<(outs GPR64:$dst), 199251662Sdim (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>; 200249259Sdim} 201249259Sdim} 202249259Sdim 203251662Sdimdefm ATOMIC_LOAD_ADD : AtomicSizes; 204251662Sdimdefm ATOMIC_LOAD_SUB : AtomicSizes; 205251662Sdimdefm ATOMIC_LOAD_AND : AtomicSizes; 206251662Sdimdefm ATOMIC_LOAD_OR : AtomicSizes; 207251662Sdimdefm ATOMIC_LOAD_XOR : AtomicSizes; 208251662Sdimdefm ATOMIC_LOAD_NAND : AtomicSizes; 209251662Sdimdefm ATOMIC_SWAP : AtomicSizes; 210249259Sdimlet Defs = [NZCV] in { 211249259Sdim // These operations need a CMP to calculate the correct value 212251662Sdim defm ATOMIC_LOAD_MIN : AtomicSizes; 213251662Sdim defm ATOMIC_LOAD_MAX : AtomicSizes; 214251662Sdim defm ATOMIC_LOAD_UMIN : AtomicSizes; 215251662Sdim defm ATOMIC_LOAD_UMAX : AtomicSizes; 216249259Sdim} 217249259Sdim 218251662Sdimclass AtomicCmpSwap<RegisterClass GPRData> 219251662Sdim : PseudoInst<(outs GPRData:$dst), 220251662Sdim (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new, 221251662Sdim i32imm:$ordering), []> { 222251662Sdim let usesCustomInserter = 1; 223251662Sdim let hasCtrlDep = 1; 224251662Sdim let mayLoad = 1; 225251662Sdim let mayStore = 1; 226251662Sdim let Defs = [NZCV]; 227249259Sdim} 228249259Sdim 229251662Sdimdef ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>; 230251662Sdimdef ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>; 231251662Sdimdef ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>; 232251662Sdimdef ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>; 233251662Sdim 234249259Sdim//===----------------------------------------------------------------------===// 235249259Sdim// Add-subtract (extended register) instructions 236249259Sdim//===----------------------------------------------------------------------===// 237249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP 238249259Sdim 239249259Sdim// The RHS of these operations is conceptually a sign/zero-extended 240249259Sdim// register, optionally shifted left by 1-4. The extension can be a 241249259Sdim// NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but 242249259Sdim// must be specified with one exception: 243249259Sdim 244249259Sdim// If one of the registers is sp/wsp then LSL is an alias for UXTW in 245249259Sdim// 32-bit instructions and UXTX in 64-bit versions, the shift amount 246249259Sdim// is not optional in that case (but can explicitly be 0), and the 247249259Sdim// entire suffix can be skipped (e.g. "add sp, x3, x2"). 248249259Sdim 249249259Sdimmulticlass extend_operands<string PREFIX, string Diag> { 250249259Sdim def _asmoperand : AsmOperandClass { 251249259Sdim let Name = PREFIX; 252249259Sdim let RenderMethod = "addRegExtendOperands"; 253249259Sdim let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">"; 254249259Sdim let DiagnosticType = "AddSubRegExtend" # Diag; 255249259Sdim } 256249259Sdim 257249259Sdim def _operand : Operand<i64>, 258249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> { 259249259Sdim let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">"; 260249259Sdim let DecoderMethod = "DecodeRegExtendOperand"; 261249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand"); 262249259Sdim } 263249259Sdim} 264249259Sdim 265249259Sdimdefm UXTB : extend_operands<"UXTB", "Small">; 266249259Sdimdefm UXTH : extend_operands<"UXTH", "Small">; 267249259Sdimdefm UXTW : extend_operands<"UXTW", "Small">; 268249259Sdimdefm UXTX : extend_operands<"UXTX", "Large">; 269249259Sdimdefm SXTB : extend_operands<"SXTB", "Small">; 270249259Sdimdefm SXTH : extend_operands<"SXTH", "Small">; 271249259Sdimdefm SXTW : extend_operands<"SXTW", "Small">; 272249259Sdimdefm SXTX : extend_operands<"SXTX", "Large">; 273249259Sdim 274249259Sdimdef LSL_extasmoperand : AsmOperandClass { 275249259Sdim let Name = "RegExtendLSL"; 276249259Sdim let RenderMethod = "addRegExtendOperands"; 277249259Sdim let DiagnosticType = "AddSubRegExtendLarge"; 278249259Sdim} 279249259Sdim 280249259Sdimdef LSL_extoperand : Operand<i64> { 281249259Sdim let ParserMatchClass = LSL_extasmoperand; 282249259Sdim} 283249259Sdim 284249259Sdim 285249259Sdim// The patterns for various sign-extensions are a little ugly and 286249259Sdim// non-uniform because everything has already been promoted to the 287249259Sdim// legal i64 and i32 types. We'll wrap the various variants up in a 288249259Sdim// class for use later. 289249259Sdimclass extend_types { 290249259Sdim dag uxtb; dag uxth; dag uxtw; dag uxtx; 291249259Sdim dag sxtb; dag sxth; dag sxtw; dag sxtx; 292249259Sdim ValueType ty; 293249259Sdim RegisterClass GPR; 294249259Sdim} 295249259Sdim 296249259Sdimdef extends_to_i64 : extend_types { 297249259Sdim let uxtb = (and (anyext i32:$Rm), 255); 298249259Sdim let uxth = (and (anyext i32:$Rm), 65535); 299249259Sdim let uxtw = (zext i32:$Rm); 300249259Sdim let uxtx = (i64 $Rm); 301249259Sdim 302249259Sdim let sxtb = (sext_inreg (anyext i32:$Rm), i8); 303249259Sdim let sxth = (sext_inreg (anyext i32:$Rm), i16); 304249259Sdim let sxtw = (sext i32:$Rm); 305249259Sdim let sxtx = (i64 $Rm); 306249259Sdim 307249259Sdim let ty = i64; 308249259Sdim let GPR = GPR64xsp; 309249259Sdim} 310249259Sdim 311249259Sdim 312249259Sdimdef extends_to_i32 : extend_types { 313249259Sdim let uxtb = (and i32:$Rm, 255); 314249259Sdim let uxth = (and i32:$Rm, 65535); 315249259Sdim let uxtw = (i32 i32:$Rm); 316249259Sdim let uxtx = (i32 i32:$Rm); 317249259Sdim 318249259Sdim let sxtb = (sext_inreg i32:$Rm, i8); 319249259Sdim let sxth = (sext_inreg i32:$Rm, i16); 320249259Sdim let sxtw = (i32 i32:$Rm); 321249259Sdim let sxtx = (i32 i32:$Rm); 322249259Sdim 323249259Sdim let ty = i32; 324249259Sdim let GPR = GPR32wsp; 325249259Sdim} 326249259Sdim 327249259Sdim// Now, six of the extensions supported are easy and uniform: if the source size 328249259Sdim// is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate 329249259Sdim// those instructions in one block. 330249259Sdim 331249259Sdim// The uxtx/sxtx could potentially be merged in, but three facts dissuaded me: 332249259Sdim// + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would 333249259Sdim// be impossible. 334249259Sdim// + Patterns are very different as well. 335249259Sdim// + Passing different registers would be ugly (more fields in extend_types 336249259Sdim// would probably be the best option). 337249259Sdimmulticlass addsub_exts<bit sf, bit op, bit S, string asmop, 338249259Sdim SDPatternOperator opfrag, 339249259Sdim dag outs, extend_types exts> { 340249259Sdim def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000, 341249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3), 342249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 343249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))], 344249259Sdim NoItinerary>; 345249259Sdim def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001, 346249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3), 347249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 348249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))], 349249259Sdim NoItinerary>; 350249259Sdim def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010, 351249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3), 352249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 353249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))], 354249259Sdim NoItinerary>; 355249259Sdim 356249259Sdim def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100, 357249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3), 358249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 359249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))], 360249259Sdim NoItinerary>; 361249259Sdim def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101, 362249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3), 363249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 364249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))], 365249259Sdim NoItinerary>; 366249259Sdim def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110, 367249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3), 368249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 369249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))], 370249259Sdim NoItinerary>; 371249259Sdim} 372249259Sdim 373249259Sdim// These two could be merge in with the above, but their patterns aren't really 374249259Sdim// necessary and the naming-scheme would necessarily break: 375249259Sdimmulticlass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, 376249259Sdim dag outs> { 377249259Sdim def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011, 378249259Sdim outs, 379249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3), 380249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 381249259Sdim [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))], 382249259Sdim NoItinerary>; 383249259Sdim 384249259Sdim def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111, 385249259Sdim outs, 386249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3), 387249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 388249259Sdim [/* No Pattern: same as uxtx */], 389249259Sdim NoItinerary>; 390249259Sdim} 391249259Sdim 392249259Sdimmulticlass addsub_wxtx<bit op, bit S, string asmop, dag outs> { 393249259Sdim def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011, 394249259Sdim outs, 395249259Sdim (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3), 396249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 397249259Sdim [/* No pattern: probably same as uxtw */], 398249259Sdim NoItinerary>; 399249259Sdim 400249259Sdim def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111, 401249259Sdim outs, 402249259Sdim (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3), 403249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 404249259Sdim [/* No Pattern: probably same as uxtw */], 405249259Sdim NoItinerary>; 406249259Sdim} 407249259Sdim 408249259Sdimclass SetRD<RegisterClass RC, SDPatternOperator op> 409249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>; 410249259Sdimclass SetNZCV<SDPatternOperator op> 411249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>; 412249259Sdim 413249259Sdimdefm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 414249259Sdim (outs GPR64xsp:$Rd), extends_to_i64>, 415249259Sdim addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 416249259Sdim (outs GPR64xsp:$Rd)>; 417249259Sdimdefm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>, 418249259Sdim (outs GPR32wsp:$Rd), extends_to_i32>, 419249259Sdim addsub_wxtx< 0b0, 0b0, "add\t$Rd, ", 420249259Sdim (outs GPR32wsp:$Rd)>; 421249259Sdimdefm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 422249259Sdim (outs GPR64xsp:$Rd), extends_to_i64>, 423249259Sdim addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 424249259Sdim (outs GPR64xsp:$Rd)>; 425249259Sdimdefm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>, 426249259Sdim (outs GPR32wsp:$Rd), extends_to_i32>, 427249259Sdim addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ", 428249259Sdim (outs GPR32wsp:$Rd)>; 429249259Sdim 430249259Sdimlet Defs = [NZCV] in { 431249259Sdimdefm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 432249259Sdim (outs GPR64:$Rd), extends_to_i64>, 433249259Sdim addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 434249259Sdim (outs GPR64:$Rd)>; 435249259Sdimdefm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>, 436249259Sdim (outs GPR32:$Rd), extends_to_i32>, 437249259Sdim addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ", 438249259Sdim (outs GPR32:$Rd)>; 439249259Sdimdefm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 440249259Sdim (outs GPR64:$Rd), extends_to_i64>, 441249259Sdim addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 442249259Sdim (outs GPR64:$Rd)>; 443249259Sdimdefm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>, 444249259Sdim (outs GPR32:$Rd), extends_to_i32>, 445249259Sdim addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ", 446249259Sdim (outs GPR32:$Rd)>; 447249259Sdim 448249259Sdim 449249259Sdimlet Rd = 0b11111, isCompare = 1 in { 450249259Sdimdefm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 451249259Sdim (outs), extends_to_i64>, 452249259Sdim addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>; 453249259Sdimdefm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 454249259Sdim (outs), extends_to_i32>, 455249259Sdim addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>; 456249259Sdimdefm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 457249259Sdim (outs), extends_to_i64>, 458249259Sdim addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>; 459249259Sdimdefm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 460249259Sdim (outs), extends_to_i32>, 461249259Sdim addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>; 462249259Sdim} 463249259Sdim} 464249259Sdim 465249259Sdim// Now patterns for the operation without a shift being needed. No patterns are 466249259Sdim// created for uxtx/sxtx since they're non-uniform and it's expected that 467249259Sdim// add/sub (shifted register) will handle those cases anyway. 468249259Sdimmulticlass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop, 469249259Sdim extend_types exts> { 470249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxtb), 471249259Sdim (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>; 472249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxth), 473249259Sdim (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>; 474249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxtw), 475249259Sdim (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>; 476249259Sdim 477249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxtb), 478249259Sdim (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>; 479249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxth), 480249259Sdim (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>; 481249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxtw), 482249259Sdim (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>; 483249259Sdim} 484249259Sdim 485249259Sdimdefm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>; 486249259Sdimdefm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>; 487249259Sdimdefm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>; 488249259Sdimdefm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>; 489249259Sdim 490249259Sdimdefm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>; 491249259Sdimdefm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>; 492249259Sdimdefm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>; 493249259Sdimdefm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>; 494249259Sdim 495249259Sdim// An extend of "lsl #imm" is valid if and only if one of Rn and Rd is 496249259Sdim// sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the 497249259Sdim// operation. Also permitted in this case is complete omission of the argument, 498249259Sdim// which implies "lsl #0". 499249259Sdimmulticlass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd, 500249259Sdim RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 501249259Sdim def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 502249259Sdim (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 503249259Sdim 504249259Sdim def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"), 505249259Sdim (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 506249259Sdim 507249259Sdim} 508249259Sdim 509249259Sdimdefm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 510249259Sdimdefm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 511249259Sdimdefm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>; 512249259Sdimdefm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>; 513249259Sdimdefm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 514249259Sdimdefm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 515249259Sdimdefm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>; 516249259Sdimdefm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>; 517249259Sdim 518249259Sdim// Rd cannot be sp for flag-setting variants so only half of the aliases are 519249259Sdim// needed. 520249259Sdimdefm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>; 521249259Sdimdefm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>; 522249259Sdimdefm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>; 523249259Sdimdefm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>; 524249259Sdim 525249259Sdim// CMP unfortunately has to be different because the instruction doesn't have a 526249259Sdim// dest register. 527249259Sdimmulticlass cmp_lsl_aliases<string asmop, Instruction inst, 528249259Sdim RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 529249259Sdim def : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 530249259Sdim (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 531249259Sdim 532249259Sdim def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"), 533249259Sdim (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 534249259Sdim} 535249259Sdim 536249259Sdimdefm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>; 537249259Sdimdefm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>; 538249259Sdimdefm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>; 539249259Sdimdefm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>; 540249259Sdim 541249259Sdim//===----------------------------------------------------------------------===// 542249259Sdim// Add-subtract (immediate) instructions 543249259Sdim//===----------------------------------------------------------------------===// 544249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV 545249259Sdim 546249259Sdim// These instructions accept a 12-bit unsigned immediate, optionally shifted 547249259Sdim// left by 12 bits. Official assembly format specifies a 12 bit immediate with 548249259Sdim// one of "", "LSL #0", "LSL #12" supplementary operands. 549249259Sdim 550249259Sdim// There are surprisingly few ways to make this work with TableGen, so this 551249259Sdim// implementation has separate instructions for the "LSL #0" and "LSL #12" 552249259Sdim// variants. 553249259Sdim 554249259Sdim// If the MCInst retained a single combined immediate (which could be 0x123000, 555249259Sdim// for example) then both components (imm & shift) would have to be delegated to 556249259Sdim// a single assembly operand. This would entail a separate operand parser 557249259Sdim// (because the LSL would have to live in the same AArch64Operand as the 558249259Sdim// immediate to be accessible); assembly parsing is rather complex and 559249259Sdim// error-prone C++ code. 560249259Sdim// 561249259Sdim// By splitting the immediate, we can delegate handling this optional operand to 562249259Sdim// an InstAlias. Supporting functions to generate the correct MCInst are still 563249259Sdim// required, but these are essentially trivial and parsing can remain generic. 564249259Sdim// 565249259Sdim// Rejected plans with rationale: 566249259Sdim// ------------------------------ 567249259Sdim// 568249259Sdim// In an ideal world you'de have two first class immediate operands (in 569249259Sdim// InOperandList, specifying imm12 and shift). Unfortunately this is not 570249259Sdim// selectable by any means I could discover. 571249259Sdim// 572249259Sdim// An Instruction with two MCOperands hidden behind a single entry in 573249259Sdim// InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional, 574249259Sdim// but required more C++ code to handle encoding/decoding. Parsing (the intended 575249259Sdim// main beneficiary) ended up equally complex because of the optional nature of 576249259Sdim// "LSL #0". 577249259Sdim// 578249259Sdim// Attempting to circumvent the need for a custom OperandParser above by giving 579249259Sdim// InstAliases without the "lsl #0" failed. add/sub could be accommodated but 580249259Sdim// the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands 581249259Sdim// should be parsed: there was no way to accommodate an "lsl #12". 582249259Sdim 583249259Sdimlet ParserMethod = "ParseImmWithLSLOperand", 584249259Sdim RenderMethod = "addImmWithLSLOperands" in { 585249259Sdim // Derived PredicateMethod fields are different for each 586249259Sdim def addsubimm_lsl0_asmoperand : AsmOperandClass { 587249259Sdim let Name = "AddSubImmLSL0"; 588249259Sdim // If an error is reported against this operand, instruction could also be a 589249259Sdim // register variant. 590249259Sdim let DiagnosticType = "AddSubSecondSource"; 591249259Sdim } 592249259Sdim 593249259Sdim def addsubimm_lsl12_asmoperand : AsmOperandClass { 594249259Sdim let Name = "AddSubImmLSL12"; 595249259Sdim let DiagnosticType = "AddSubSecondSource"; 596249259Sdim } 597249259Sdim} 598249259Sdim 599249259Sdimdef shr_12_XFORM : SDNodeXForm<imm, [{ 600249259Sdim return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32); 601249259Sdim}]>; 602249259Sdim 603249259Sdimdef shr_12_neg_XFORM : SDNodeXForm<imm, [{ 604249259Sdim return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32); 605249259Sdim}]>; 606249259Sdim 607249259Sdimdef neg_XFORM : SDNodeXForm<imm, [{ 608249259Sdim return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32); 609249259Sdim}]>; 610249259Sdim 611249259Sdim 612249259Sdimmulticlass addsub_imm_operands<ValueType ty> { 613249259Sdim let PrintMethod = "printAddSubImmLSL0Operand", 614249259Sdim EncoderMethod = "getAddSubImmOpValue", 615249259Sdim ParserMatchClass = addsubimm_lsl0_asmoperand in { 616249259Sdim def _posimm_lsl0 : Operand<ty>, 617249259Sdim ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>; 618249259Sdim def _negimm_lsl0 : Operand<ty>, 619249259Sdim ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }], 620249259Sdim neg_XFORM>; 621249259Sdim } 622249259Sdim 623249259Sdim let PrintMethod = "printAddSubImmLSL12Operand", 624249259Sdim EncoderMethod = "getAddSubImmOpValue", 625249259Sdim ParserMatchClass = addsubimm_lsl12_asmoperand in { 626249259Sdim def _posimm_lsl12 : Operand<ty>, 627249259Sdim ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }], 628249259Sdim shr_12_XFORM>; 629249259Sdim 630249259Sdim def _negimm_lsl12 : Operand<ty>, 631249259Sdim ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }], 632249259Sdim shr_12_neg_XFORM>; 633249259Sdim } 634249259Sdim} 635249259Sdim 636249259Sdim// The add operands don't need any transformation 637249259Sdimdefm addsubimm_operand_i32 : addsub_imm_operands<i32>; 638249259Sdimdefm addsubimm_operand_i64 : addsub_imm_operands<i64>; 639249259Sdim 640249259Sdimmulticlass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift, 641249259Sdim string asmop, string cmpasmop, 642249259Sdim Operand imm_operand, Operand cmp_imm_operand, 643249259Sdim RegisterClass GPR, RegisterClass GPRsp, 644249259Sdim AArch64Reg ZR, ValueType Ty> { 645249259Sdim // All registers for non-S variants allow SP 646249259Sdim def _s : A64I_addsubimm<sf, op, 0b0, shift, 647249259Sdim (outs GPRsp:$Rd), 648249259Sdim (ins GPRsp:$Rn, imm_operand:$Imm12), 649249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm12"), 650249259Sdim [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))], 651249259Sdim NoItinerary>; 652249259Sdim 653249259Sdim 654249259Sdim // S variants can read SP but would write to ZR 655249259Sdim def _S : A64I_addsubimm<sf, op, 0b1, shift, 656249259Sdim (outs GPR:$Rd), 657249259Sdim (ins GPRsp:$Rn, imm_operand:$Imm12), 658249259Sdim !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"), 659249259Sdim [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))], 660249259Sdim NoItinerary> { 661249259Sdim let Defs = [NZCV]; 662249259Sdim } 663249259Sdim 664249259Sdim // Note that the pattern here for ADDS is subtle. Canonically CMP 665249259Sdim // a, b becomes SUBS a, b. If b < 0 then this is equivalent to 666249259Sdim // ADDS a, (-b). This is not true in general. 667249259Sdim def _cmp : A64I_addsubimm<sf, op, 0b1, shift, 668249259Sdim (outs), (ins GPRsp:$Rn, imm_operand:$Imm12), 669249259Sdim !strconcat(cmpasmop, " $Rn, $Imm12"), 670249259Sdim [(set NZCV, 671249259Sdim (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))], 672249259Sdim NoItinerary> { 673249259Sdim let Rd = 0b11111; 674249259Sdim let Defs = [NZCV]; 675249259Sdim let isCompare = 1; 676249259Sdim } 677249259Sdim} 678249259Sdim 679249259Sdim 680249259Sdimmulticlass addsubimm_shifts<string prefix, bit sf, bit op, 681249259Sdim string asmop, string cmpasmop, string operand, string cmpoperand, 682249259Sdim RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR, 683249259Sdim ValueType Ty> { 684249259Sdim defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00, 685249259Sdim asmop, cmpasmop, 686249259Sdim !cast<Operand>(operand # "_lsl0"), 687249259Sdim !cast<Operand>(cmpoperand # "_lsl0"), 688249259Sdim GPR, GPRsp, ZR, Ty>; 689249259Sdim 690249259Sdim defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01, 691249259Sdim asmop, cmpasmop, 692249259Sdim !cast<Operand>(operand # "_lsl12"), 693249259Sdim !cast<Operand>(cmpoperand # "_lsl12"), 694249259Sdim GPR, GPRsp, ZR, Ty>; 695249259Sdim} 696249259Sdim 697249259Sdimdefm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn", 698249259Sdim "addsubimm_operand_i32_posimm", 699249259Sdim "addsubimm_operand_i32_negimm", 700249259Sdim GPR32, GPR32wsp, WZR, i32>; 701249259Sdimdefm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn", 702249259Sdim "addsubimm_operand_i64_posimm", 703249259Sdim "addsubimm_operand_i64_negimm", 704249259Sdim GPR64, GPR64xsp, XZR, i64>; 705249259Sdimdefm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp", 706249259Sdim "addsubimm_operand_i32_negimm", 707249259Sdim "addsubimm_operand_i32_posimm", 708249259Sdim GPR32, GPR32wsp, WZR, i32>; 709249259Sdimdefm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp", 710249259Sdim "addsubimm_operand_i64_negimm", 711249259Sdim "addsubimm_operand_i64_posimm", 712249259Sdim GPR64, GPR64xsp, XZR, i64>; 713249259Sdim 714249259Sdimmulticlass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> { 715249259Sdim def _fromsp : InstAlias<"mov $Rd, $Rn", 716249259Sdim (addop GPRsp:$Rd, SP:$Rn, 0), 717249259Sdim 0b1>; 718249259Sdim 719249259Sdim def _tosp : InstAlias<"mov $Rd, $Rn", 720249259Sdim (addop SP:$Rd, GPRsp:$Rn, 0), 721249259Sdim 0b1>; 722249259Sdim} 723249259Sdim 724249259Sdim// Recall Rxsp is a RegisterClass containing *just* xsp. 725249259Sdimdefm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>; 726249259Sdimdefm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>; 727249259Sdim 728249259Sdim//===----------------------------------------------------------------------===// 729249259Sdim// Add-subtract (shifted register) instructions 730249259Sdim//===----------------------------------------------------------------------===// 731249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS 732249259Sdim 733249259Sdim//===------------------------------- 734249259Sdim// 1. The "shifed register" operands. Shared with logical insts. 735249259Sdim//===------------------------------- 736249259Sdim 737249259Sdimmulticlass shift_operands<string prefix, string form> { 738249259Sdim def _asmoperand_i32 : AsmOperandClass { 739249259Sdim let Name = "Shift" # form # "i32"; 740249259Sdim let RenderMethod = "addShiftOperands"; 741249259Sdim let PredicateMethod = "isShift<A64SE::" # form # ", false>"; 742249259Sdim let DiagnosticType = "AddSubRegShift32"; 743249259Sdim } 744249259Sdim 745249259Sdim // Note that the operand type is intentionally i64 because the DAGCombiner 746249259Sdim // puts these into a canonical form. 747249259Sdim def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 748249259Sdim let ParserMatchClass 749249259Sdim = !cast<AsmOperandClass>(prefix # "_asmoperand_i32"); 750249259Sdim let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 751249259Sdim let DecoderMethod = "Decode32BitShiftOperand"; 752249259Sdim } 753249259Sdim 754249259Sdim def _asmoperand_i64 : AsmOperandClass { 755249259Sdim let Name = "Shift" # form # "i64"; 756249259Sdim let RenderMethod = "addShiftOperands"; 757249259Sdim let PredicateMethod = "isShift<A64SE::" # form # ", true>"; 758249259Sdim let DiagnosticType = "AddSubRegShift64"; 759249259Sdim } 760249259Sdim 761249259Sdim def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 762249259Sdim let ParserMatchClass 763249259Sdim = !cast<AsmOperandClass>(prefix # "_asmoperand_i64"); 764249259Sdim let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 765249259Sdim } 766249259Sdim} 767249259Sdim 768249259Sdimdefm lsl_operand : shift_operands<"lsl_operand", "LSL">; 769249259Sdimdefm lsr_operand : shift_operands<"lsr_operand", "LSR">; 770249259Sdimdefm asr_operand : shift_operands<"asr_operand", "ASR">; 771249259Sdim 772249259Sdim// Not used for add/sub, but defined here for completeness. The "logical 773249259Sdim// (shifted register)" instructions *do* have an ROR variant. 774249259Sdimdefm ror_operand : shift_operands<"ror_operand", "ROR">; 775249259Sdim 776249259Sdim//===------------------------------- 777249259Sdim// 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions. 778249259Sdim//===------------------------------- 779249259Sdim 780249259Sdim// N.b. the commutable parameter is just !N. It will be first against the wall 781249259Sdim// when the revolution comes. 782249259Sdimmulticlass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable, 783249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 784249259Sdim RegisterClass GPR, list<Register> defs> { 785249259Sdim let isCommutable = commutable, Defs = defs in { 786249259Sdim def _lsl : A64I_addsubshift<sf, op, s, 0b00, 787249259Sdim (outs GPR:$Rd), 788249259Sdim (ins GPR:$Rn, GPR:$Rm, 789249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 790249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 791249259Sdim [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 792249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 793249259Sdim )], 794249259Sdim NoItinerary>; 795249259Sdim 796249259Sdim def _lsr : A64I_addsubshift<sf, op, s, 0b01, 797249259Sdim (outs GPR:$Rd), 798249259Sdim (ins GPR:$Rn, GPR:$Rm, 799249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 800249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 801249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 802249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 803249259Sdim )], 804249259Sdim NoItinerary>; 805249259Sdim 806249259Sdim def _asr : A64I_addsubshift<sf, op, s, 0b10, 807249259Sdim (outs GPR:$Rd), 808249259Sdim (ins GPR:$Rn, GPR:$Rm, 809249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 810249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 811249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 812249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 813249259Sdim )], 814249259Sdim NoItinerary>; 815249259Sdim } 816249259Sdim 817249259Sdim def _noshift 818249259Sdim : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 819249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 820249259Sdim GPR:$Rm, 0)>; 821249259Sdim 822249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 823249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 824249259Sdim} 825249259Sdim 826249259Sdimmulticlass addsub_sizes<string prefix, bit op, bit s, bit commutable, 827249259Sdim string asmop, SDPatternOperator opfrag, 828249259Sdim list<Register> defs> { 829249259Sdim defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s, 830249259Sdim commutable, asmop, opfrag, i64, GPR64, defs>; 831249259Sdim defm www : addsub_shifts<prefix # "www", 0b0, op, s, 832249259Sdim commutable, asmop, opfrag, i32, GPR32, defs>; 833249259Sdim} 834249259Sdim 835249259Sdim 836249259Sdimdefm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>; 837249259Sdimdefm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>; 838249259Sdim 839249259Sdimdefm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>; 840249259Sdimdefm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>; 841249259Sdim 842249259Sdim//===------------------------------- 843249259Sdim// 1. The NEG/NEGS aliases 844249259Sdim//===------------------------------- 845249259Sdim 846249259Sdimmulticlass neg_alias<Instruction INST, RegisterClass GPR, Register ZR, 847249259Sdim ValueType ty, Operand shift_operand, SDNode shiftop> { 848249259Sdim def : InstAlias<"neg $Rd, $Rm, $Imm6", 849249259Sdim (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 850249259Sdim 851249259Sdim def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)), 852249259Sdim (INST ZR, $Rm, shift_operand:$Imm6)>; 853249259Sdim} 854249259Sdim 855249259Sdimdefm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>; 856249259Sdimdefm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>; 857249259Sdimdefm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>; 858249259Sdimdef : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 859249259Sdimdef : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>; 860249259Sdim 861249259Sdimdefm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>; 862249259Sdimdefm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>; 863249259Sdimdefm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>; 864249259Sdimdef : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 865249259Sdimdef : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>; 866249259Sdim 867249259Sdim// NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to 868249259Sdim// be involved. 869249259Sdimclass negs_alias<Instruction INST, RegisterClass GPR, 870249259Sdim Register ZR, Operand shift_operand, SDNode shiftop> 871249259Sdim : InstAlias<"negs $Rd, $Rm, $Imm6", 872249259Sdim (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 873249259Sdim 874249259Sdimdef : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>; 875249259Sdimdef : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>; 876249259Sdimdef : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>; 877249259Sdimdef : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 878249259Sdim 879249259Sdimdef : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>; 880249259Sdimdef : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>; 881249259Sdimdef : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>; 882249259Sdimdef : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 883249259Sdim 884249259Sdim//===------------------------------- 885249259Sdim// 1. The CMP/CMN aliases 886249259Sdim//===------------------------------- 887249259Sdim 888249259Sdimmulticlass cmp_shifts<string prefix, bit sf, bit op, bit commutable, 889249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 890249259Sdim RegisterClass GPR> { 891249259Sdim let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in { 892249259Sdim def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00, 893249259Sdim (outs), 894249259Sdim (ins GPR:$Rn, GPR:$Rm, 895249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 896249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 897249259Sdim [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm, 898249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 899249259Sdim )], 900249259Sdim NoItinerary>; 901249259Sdim 902249259Sdim def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01, 903249259Sdim (outs), 904249259Sdim (ins GPR:$Rn, GPR:$Rm, 905249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 906249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 907249259Sdim [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm, 908249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 909249259Sdim )], 910249259Sdim NoItinerary>; 911249259Sdim 912249259Sdim def _asr : A64I_addsubshift<sf, op, 0b1, 0b10, 913249259Sdim (outs), 914249259Sdim (ins GPR:$Rn, GPR:$Rm, 915249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 916249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 917249259Sdim [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm, 918249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 919249259Sdim )], 920249259Sdim NoItinerary>; 921249259Sdim } 922249259Sdim 923249259Sdim def _noshift 924249259Sdim : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 925249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 926249259Sdim 927249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 928249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 929249259Sdim} 930249259Sdim 931249259Sdimdefm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>; 932249259Sdimdefm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>; 933249259Sdim 934249259Sdimdefm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>; 935249259Sdimdefm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>; 936249259Sdim 937249259Sdim//===----------------------------------------------------------------------===// 938249259Sdim// Add-subtract (with carry) instructions 939249259Sdim//===----------------------------------------------------------------------===// 940249259Sdim// Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS 941249259Sdim 942249259Sdimmulticlass A64I_addsubcarrySizes<bit op, bit s, string asmop> { 943249259Sdim let Uses = [NZCV] in { 944249259Sdim def www : A64I_addsubcarry<0b0, op, s, 0b000000, 945249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm), 946249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 947249259Sdim [], NoItinerary>; 948249259Sdim 949249259Sdim def xxx : A64I_addsubcarry<0b1, op, s, 0b000000, 950249259Sdim (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm), 951249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 952249259Sdim [], NoItinerary>; 953249259Sdim } 954249259Sdim} 955249259Sdim 956249259Sdimlet isCommutable = 1 in { 957249259Sdim defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">; 958249259Sdim} 959249259Sdim 960249259Sdimdefm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">; 961249259Sdim 962249259Sdimlet Defs = [NZCV] in { 963249259Sdim let isCommutable = 1 in { 964249259Sdim defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">; 965249259Sdim } 966249259Sdim 967249259Sdim defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">; 968249259Sdim} 969249259Sdim 970249259Sdimdef : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>; 971249259Sdimdef : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 972249259Sdimdef : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>; 973249259Sdimdef : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 974249259Sdim 975249259Sdim// Note that adde and sube can form a chain longer than two (e.g. for 256-bit 976249259Sdim// addition). So the flag-setting instructions are appropriate. 977249259Sdimdef : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>; 978249259Sdimdef : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>; 979249259Sdimdef : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>; 980249259Sdimdef : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>; 981249259Sdim 982249259Sdim//===----------------------------------------------------------------------===// 983249259Sdim// Bitfield 984249259Sdim//===----------------------------------------------------------------------===// 985249259Sdim// Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL, 986249259Sdim// UBFIZ, UBFX 987249259Sdim 988249259Sdim// Because of the rather complicated nearly-overlapping aliases, the decoding of 989249259Sdim// this range of instructions is handled manually. The architectural 990249259Sdim// instructions are BFM, SBFM and UBFM but a disassembler should never produce 991249259Sdim// these. 992249259Sdim// 993249259Sdim// In the end, the best option was to use BFM instructions for decoding under 994249259Sdim// almost all circumstances, but to create aliasing *Instructions* for each of 995249259Sdim// the canonical forms and specify a completely custom decoder which would 996249259Sdim// substitute the correct MCInst as needed. 997249259Sdim// 998249259Sdim// This also simplifies instruction selection, parsing etc because the MCInsts 999249259Sdim// have a shape that's closer to their use in code. 1000249259Sdim 1001249259Sdim//===------------------------------- 1002249259Sdim// 1. The architectural BFM instructions 1003249259Sdim//===------------------------------- 1004249259Sdim 1005249259Sdimdef uimm5_asmoperand : AsmOperandClass { 1006249259Sdim let Name = "UImm5"; 1007249259Sdim let PredicateMethod = "isUImm<5>"; 1008249259Sdim let RenderMethod = "addImmOperands"; 1009249259Sdim let DiagnosticType = "UImm5"; 1010249259Sdim} 1011249259Sdim 1012249259Sdimdef uimm6_asmoperand : AsmOperandClass { 1013249259Sdim let Name = "UImm6"; 1014249259Sdim let PredicateMethod = "isUImm<6>"; 1015249259Sdim let RenderMethod = "addImmOperands"; 1016249259Sdim let DiagnosticType = "UImm6"; 1017249259Sdim} 1018249259Sdim 1019249259Sdimdef bitfield32_imm : Operand<i64>, 1020249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> { 1021249259Sdim let ParserMatchClass = uimm5_asmoperand; 1022249259Sdim 1023249259Sdim let DecoderMethod = "DecodeBitfield32ImmOperand"; 1024249259Sdim} 1025249259Sdim 1026249259Sdim 1027249259Sdimdef bitfield64_imm : Operand<i64>, 1028249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> { 1029249259Sdim let ParserMatchClass = uimm6_asmoperand; 1030249259Sdim 1031249259Sdim // Default decoder works in 64-bit case: the 6-bit field can take any value. 1032249259Sdim} 1033249259Sdim 1034249259Sdimmulticlass A64I_bitfieldSizes<bits<2> opc, string asmop> { 1035249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1036249259Sdim (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1037249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1038249259Sdim [], NoItinerary> { 1039249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1040249259Sdim } 1041249259Sdim 1042249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1043249259Sdim (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1044249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1045249259Sdim [], NoItinerary> { 1046249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1047249259Sdim } 1048249259Sdim} 1049249259Sdim 1050249259Sdimdefm SBFM : A64I_bitfieldSizes<0b00, "sbfm">; 1051249259Sdimdefm UBFM : A64I_bitfieldSizes<0b10, "ubfm">; 1052249259Sdim 1053249259Sdim// BFM instructions modify the destination register rather than defining it 1054249259Sdim// completely. 1055249259Sdimdef BFMwwii : 1056249259Sdim A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1057249259Sdim (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1058249259Sdim "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1059249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1060249259Sdim let Constraints = "$src = $Rd"; 1061249259Sdim} 1062249259Sdim 1063249259Sdimdef BFMxxii : 1064249259Sdim A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1065249259Sdim (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1066249259Sdim "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1067249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1068249259Sdim let Constraints = "$src = $Rd"; 1069249259Sdim} 1070249259Sdim 1071249259Sdim 1072249259Sdim//===------------------------------- 1073249259Sdim// 2. Extend aliases to 64-bit dest 1074249259Sdim//===------------------------------- 1075249259Sdim 1076249259Sdim// Unfortunately the extensions that end up as 64-bits cannot be handled by an 1077249259Sdim// instruction alias: their syntax is (for example) "SXTB x0, w0", which needs 1078249259Sdim// to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is 1079249259Sdim// not capable of such a map as far as I'm aware 1080249259Sdim 1081249259Sdim// Note that these instructions are strictly more specific than the 1082249259Sdim// BFM ones (in ImmR) so they can handle their own decoding. 1083249259Sdimclass A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty, 1084249259Sdim string asmop, bits<6> imms, dag pattern> 1085249259Sdim : A64I_bitfield<sf, opc, sf, 1086249259Sdim (outs GPRDest:$Rd), (ins GPR32:$Rn), 1087249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), 1088249259Sdim [(set dty:$Rd, pattern)], NoItinerary> { 1089249259Sdim let ImmR = 0b000000; 1090249259Sdim let ImmS = imms; 1091249259Sdim} 1092249259Sdim 1093249259Sdim// Signed extensions 1094249259Sdimdef SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7, 1095249259Sdim (sext_inreg (anyext i32:$Rn), i8)>; 1096249259Sdimdef SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7, 1097249259Sdim (sext_inreg i32:$Rn, i8)>; 1098249259Sdimdef SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15, 1099249259Sdim (sext_inreg (anyext i32:$Rn), i16)>; 1100249259Sdimdef SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15, 1101249259Sdim (sext_inreg i32:$Rn, i16)>; 1102249259Sdimdef SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>; 1103249259Sdim 1104249259Sdim// Unsigned extensions 1105249259Sdimdef UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7, 1106249259Sdim (and i32:$Rn, 255)>; 1107249259Sdimdef UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15, 1108249259Sdim (and i32:$Rn, 65535)>; 1109249259Sdim 1110249259Sdim// The 64-bit unsigned variants are not strictly architectural but recommended 1111249259Sdim// for consistency. 1112249259Sdimlet isAsmParserOnly = 1 in { 1113249259Sdim def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7, 1114249259Sdim (and (anyext i32:$Rn), 255)>; 1115249259Sdim def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15, 1116249259Sdim (and (anyext i32:$Rn), 65535)>; 1117249259Sdim} 1118249259Sdim 1119249259Sdim// Extra patterns for when the source register is actually 64-bits 1120249259Sdim// too. There's no architectural difference here, it's just LLVM 1121249259Sdim// shinanigans. There's no need for equivalent zero-extension patterns 1122249259Sdim// because they'll already be caught by logical (immediate) matching. 1123249259Sdimdef : Pat<(sext_inreg i64:$Rn, i8), 1124249259Sdim (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>; 1125249259Sdimdef : Pat<(sext_inreg i64:$Rn, i16), 1126249259Sdim (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>; 1127249259Sdimdef : Pat<(sext_inreg i64:$Rn, i32), 1128249259Sdim (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>; 1129249259Sdim 1130249259Sdim 1131249259Sdim//===------------------------------- 1132249259Sdim// 3. Aliases for ASR and LSR (the simple shifts) 1133249259Sdim//===------------------------------- 1134249259Sdim 1135249259Sdim// These also handle their own decoding because ImmS being set makes 1136249259Sdim// them take precedence over BFM. 1137249259Sdimmulticlass A64I_shift<bits<2> opc, string asmop, SDNode opnode> { 1138249259Sdim def wwi : A64I_bitfield<0b0, opc, 0b0, 1139249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR), 1140249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1141249259Sdim [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))], 1142249259Sdim NoItinerary> { 1143249259Sdim let ImmS = 31; 1144249259Sdim } 1145249259Sdim 1146249259Sdim def xxi : A64I_bitfield<0b1, opc, 0b1, 1147249259Sdim (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR), 1148249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1149249259Sdim [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))], 1150249259Sdim NoItinerary> { 1151249259Sdim let ImmS = 63; 1152249259Sdim } 1153249259Sdim 1154249259Sdim} 1155249259Sdim 1156249259Sdimdefm ASR : A64I_shift<0b00, "asr", sra>; 1157249259Sdimdefm LSR : A64I_shift<0b10, "lsr", srl>; 1158249259Sdim 1159249259Sdim//===------------------------------- 1160249259Sdim// 4. Aliases for LSL 1161249259Sdim//===------------------------------- 1162249259Sdim 1163249259Sdim// Unfortunately LSL and subsequent aliases are much more complicated. We need 1164249259Sdim// to be able to say certain output instruction fields depend in a complex 1165249259Sdim// manner on combinations of input assembly fields). 1166249259Sdim// 1167249259Sdim// MIOperandInfo *might* have been able to do it, but at the cost of 1168249259Sdim// significantly more C++ code. 1169249259Sdim 1170249259Sdim// N.b. contrary to usual practice these operands store the shift rather than 1171249259Sdim// the machine bits in an MCInst. The complexity overhead of consistency 1172249259Sdim// outweighed the benefits in this case (custom asmparser, printer and selection 1173249259Sdim// vs custom encoder). 1174249259Sdimdef bitfield32_lsl_imm : Operand<i64>, 1175249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1176249259Sdim let ParserMatchClass = uimm5_asmoperand; 1177249259Sdim let EncoderMethod = "getBitfield32LSLOpValue"; 1178249259Sdim} 1179249259Sdim 1180249259Sdimdef bitfield64_lsl_imm : Operand<i64>, 1181249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1182249259Sdim let ParserMatchClass = uimm6_asmoperand; 1183249259Sdim let EncoderMethod = "getBitfield64LSLOpValue"; 1184249259Sdim} 1185249259Sdim 1186249259Sdimclass A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty, 1187249259Sdim Operand operand> 1188249259Sdim : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm), 1189249259Sdim "lsl\t$Rd, $Rn, $FullImm", 1190249259Sdim [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))], 1191249259Sdim NoItinerary> { 1192249259Sdim bits<12> FullImm; 1193249259Sdim let ImmR = FullImm{5-0}; 1194249259Sdim let ImmS = FullImm{11-6}; 1195249259Sdim 1196249259Sdim // No disassembler allowed because it would overlap with BFM which does the 1197249259Sdim // actual work. 1198249259Sdim let isAsmParserOnly = 1; 1199249259Sdim} 1200249259Sdim 1201249259Sdimdef LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>; 1202249259Sdimdef LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>; 1203249259Sdim 1204249259Sdim//===------------------------------- 1205249259Sdim// 5. Aliases for bitfield extract instructions 1206249259Sdim//===------------------------------- 1207249259Sdim 1208249259Sdimdef bfx32_width_asmoperand : AsmOperandClass { 1209249259Sdim let Name = "BFX32Width"; 1210249259Sdim let PredicateMethod = "isBitfieldWidth<32>"; 1211249259Sdim let RenderMethod = "addBFXWidthOperands"; 1212249259Sdim let DiagnosticType = "Width32"; 1213249259Sdim} 1214249259Sdim 1215249259Sdimdef bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> { 1216249259Sdim let PrintMethod = "printBFXWidthOperand"; 1217249259Sdim let ParserMatchClass = bfx32_width_asmoperand; 1218249259Sdim} 1219249259Sdim 1220249259Sdimdef bfx64_width_asmoperand : AsmOperandClass { 1221249259Sdim let Name = "BFX64Width"; 1222249259Sdim let PredicateMethod = "isBitfieldWidth<64>"; 1223249259Sdim let RenderMethod = "addBFXWidthOperands"; 1224249259Sdim let DiagnosticType = "Width64"; 1225249259Sdim} 1226249259Sdim 1227249259Sdimdef bfx64_width : Operand<i64> { 1228249259Sdim let PrintMethod = "printBFXWidthOperand"; 1229249259Sdim let ParserMatchClass = bfx64_width_asmoperand; 1230249259Sdim} 1231249259Sdim 1232249259Sdim 1233249259Sdimmulticlass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> { 1234249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1235249259Sdim (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1236249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1237249259Sdim [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))], 1238249259Sdim NoItinerary> { 1239249259Sdim // As above, no disassembler allowed. 1240249259Sdim let isAsmParserOnly = 1; 1241249259Sdim } 1242249259Sdim 1243249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1244249259Sdim (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1245249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1246249259Sdim [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))], 1247249259Sdim NoItinerary> { 1248249259Sdim // As above, no disassembler allowed. 1249249259Sdim let isAsmParserOnly = 1; 1250249259Sdim } 1251249259Sdim} 1252249259Sdim 1253249259Sdimdefm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>; 1254249259Sdimdefm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>; 1255249259Sdim 1256249259Sdim// Again, variants based on BFM modify Rd so need it as an input too. 1257249259Sdimdef BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1258249259Sdim (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1259249259Sdim "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1260249259Sdim // As above, no disassembler allowed. 1261249259Sdim let isAsmParserOnly = 1; 1262249259Sdim let Constraints = "$src = $Rd"; 1263249259Sdim} 1264249259Sdim 1265249259Sdimdef BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1266249259Sdim (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1267249259Sdim "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1268249259Sdim // As above, no disassembler allowed. 1269249259Sdim let isAsmParserOnly = 1; 1270249259Sdim let Constraints = "$src = $Rd"; 1271249259Sdim} 1272249259Sdim 1273249259Sdim// SBFX instructions can do a 1-instruction sign-extension of boolean values. 1274249259Sdimdef : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>; 1275249259Sdimdef : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>; 1276249259Sdimdef : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)), 1277249259Sdim (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>; 1278249259Sdim 1279249259Sdim// UBFX makes sense as an implementation of a 64-bit zero-extension too. Could 1280249259Sdim// use either 64-bit or 32-bit variant, but 32-bit might be more efficient. 1281263508Sdimdef : Pat<(i64 (zext i32:$Rn)), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31), 1282249259Sdim sub_32)>; 1283249259Sdim 1284249259Sdim//===------------------------------- 1285249259Sdim// 6. Aliases for bitfield insert instructions 1286249259Sdim//===------------------------------- 1287249259Sdim 1288249259Sdimdef bfi32_lsb_asmoperand : AsmOperandClass { 1289249259Sdim let Name = "BFI32LSB"; 1290249259Sdim let PredicateMethod = "isUImm<5>"; 1291249259Sdim let RenderMethod = "addBFILSBOperands<32>"; 1292249259Sdim let DiagnosticType = "UImm5"; 1293249259Sdim} 1294249259Sdim 1295249259Sdimdef bfi32_lsb : Operand<i64>, 1296249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1297249259Sdim let PrintMethod = "printBFILSBOperand<32>"; 1298249259Sdim let ParserMatchClass = bfi32_lsb_asmoperand; 1299249259Sdim} 1300249259Sdim 1301249259Sdimdef bfi64_lsb_asmoperand : AsmOperandClass { 1302249259Sdim let Name = "BFI64LSB"; 1303249259Sdim let PredicateMethod = "isUImm<6>"; 1304249259Sdim let RenderMethod = "addBFILSBOperands<64>"; 1305249259Sdim let DiagnosticType = "UImm6"; 1306249259Sdim} 1307249259Sdim 1308249259Sdimdef bfi64_lsb : Operand<i64>, 1309249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1310249259Sdim let PrintMethod = "printBFILSBOperand<64>"; 1311249259Sdim let ParserMatchClass = bfi64_lsb_asmoperand; 1312249259Sdim} 1313249259Sdim 1314249259Sdim// Width verification is performed during conversion so width operand can be 1315249259Sdim// shared between 32/64-bit cases. Still needed for the print method though 1316249259Sdim// because ImmR encodes "width - 1". 1317249259Sdimdef bfi32_width_asmoperand : AsmOperandClass { 1318249259Sdim let Name = "BFI32Width"; 1319249259Sdim let PredicateMethod = "isBitfieldWidth<32>"; 1320249259Sdim let RenderMethod = "addBFIWidthOperands"; 1321249259Sdim let DiagnosticType = "Width32"; 1322249259Sdim} 1323249259Sdim 1324249259Sdimdef bfi32_width : Operand<i64>, 1325249259Sdim ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> { 1326249259Sdim let PrintMethod = "printBFIWidthOperand"; 1327249259Sdim let ParserMatchClass = bfi32_width_asmoperand; 1328249259Sdim} 1329249259Sdim 1330249259Sdimdef bfi64_width_asmoperand : AsmOperandClass { 1331249259Sdim let Name = "BFI64Width"; 1332249259Sdim let PredicateMethod = "isBitfieldWidth<64>"; 1333249259Sdim let RenderMethod = "addBFIWidthOperands"; 1334249259Sdim let DiagnosticType = "Width64"; 1335249259Sdim} 1336249259Sdim 1337249259Sdimdef bfi64_width : Operand<i64>, 1338249259Sdim ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> { 1339249259Sdim let PrintMethod = "printBFIWidthOperand"; 1340249259Sdim let ParserMatchClass = bfi64_width_asmoperand; 1341249259Sdim} 1342249259Sdim 1343249259Sdimmulticlass A64I_bitfield_insert<bits<2> opc, string asmop> { 1344249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1345249259Sdim (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1346249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1347249259Sdim [], NoItinerary> { 1348249259Sdim // As above, no disassembler allowed. 1349249259Sdim let isAsmParserOnly = 1; 1350249259Sdim } 1351249259Sdim 1352249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1353249259Sdim (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1354249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1355249259Sdim [], NoItinerary> { 1356249259Sdim // As above, no disassembler allowed. 1357249259Sdim let isAsmParserOnly = 1; 1358249259Sdim } 1359249259Sdim} 1360249259Sdim 1361249259Sdimdefm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">; 1362249259Sdimdefm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">; 1363249259Sdim 1364249259Sdim 1365249259Sdimdef BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1366249259Sdim (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1367249259Sdim "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1368249259Sdim // As above, no disassembler allowed. 1369249259Sdim let isAsmParserOnly = 1; 1370249259Sdim let Constraints = "$src = $Rd"; 1371249259Sdim} 1372249259Sdim 1373249259Sdimdef BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1374249259Sdim (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1375249259Sdim "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1376249259Sdim // As above, no disassembler allowed. 1377249259Sdim let isAsmParserOnly = 1; 1378249259Sdim let Constraints = "$src = $Rd"; 1379249259Sdim} 1380249259Sdim 1381249259Sdim//===----------------------------------------------------------------------===// 1382249259Sdim// Compare and branch (immediate) 1383249259Sdim//===----------------------------------------------------------------------===// 1384249259Sdim// Contains: CBZ, CBNZ 1385249259Sdim 1386249259Sdimclass label_asmoperand<int width, int scale> : AsmOperandClass { 1387249259Sdim let Name = "Label" # width # "_" # scale; 1388249259Sdim let PredicateMethod = "isLabel<" # width # "," # scale # ">"; 1389249259Sdim let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">"; 1390249259Sdim let DiagnosticType = "Label"; 1391249259Sdim} 1392249259Sdim 1393249259Sdimdef label_wid19_scal4_asmoperand : label_asmoperand<19, 4>; 1394249259Sdim 1395249259Sdim// All conditional immediate branches are the same really: 19 signed bits scaled 1396249259Sdim// by the instruction-size (4). 1397249259Sdimdef bcc_target : Operand<OtherVT> { 1398249259Sdim // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 1399249259Sdim let ParserMatchClass = label_wid19_scal4_asmoperand; 1400249259Sdim let PrintMethod = "printLabelOperand<19, 4>"; 1401249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>"; 1402249259Sdim let OperandType = "OPERAND_PCREL"; 1403249259Sdim} 1404249259Sdim 1405249259Sdimmulticlass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> { 1406249259Sdim let isBranch = 1, isTerminator = 1 in { 1407249259Sdim def x : A64I_cmpbr<0b1, op, 1408249259Sdim (outs), 1409249259Sdim (ins GPR64:$Rt, bcc_target:$Label), 1410249259Sdim !strconcat(asmop,"\t$Rt, $Label"), 1411249259Sdim [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)], 1412249259Sdim NoItinerary>; 1413249259Sdim 1414249259Sdim def w : A64I_cmpbr<0b0, op, 1415249259Sdim (outs), 1416249259Sdim (ins GPR32:$Rt, bcc_target:$Label), 1417249259Sdim !strconcat(asmop,"\t$Rt, $Label"), 1418249259Sdim [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)], 1419249259Sdim NoItinerary>; 1420249259Sdim } 1421249259Sdim} 1422249259Sdim 1423249259Sdimdefm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{ 1424249259Sdim return Imm == A64CC::EQ; 1425249259Sdim}]> >; 1426249259Sdimdefm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{ 1427249259Sdim return Imm == A64CC::NE; 1428249259Sdim}]> >; 1429249259Sdim 1430249259Sdim//===----------------------------------------------------------------------===// 1431249259Sdim// Conditional branch (immediate) instructions 1432249259Sdim//===----------------------------------------------------------------------===// 1433249259Sdim// Contains: B.cc 1434249259Sdim 1435249259Sdimdef cond_code_asmoperand : AsmOperandClass { 1436249259Sdim let Name = "CondCode"; 1437249259Sdim let DiagnosticType = "CondCode"; 1438249259Sdim} 1439249259Sdim 1440249259Sdimdef cond_code : Operand<i32>, ImmLeaf<i32, [{ 1441249259Sdim return Imm >= 0 && Imm <= 15; 1442249259Sdim}]> { 1443249259Sdim let PrintMethod = "printCondCodeOperand"; 1444249259Sdim let ParserMatchClass = cond_code_asmoperand; 1445249259Sdim} 1446249259Sdim 1447249259Sdimdef Bcc : A64I_condbr<0b0, 0b0, (outs), 1448249259Sdim (ins cond_code:$Cond, bcc_target:$Label), 1449249259Sdim "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)], 1450249259Sdim NoItinerary> { 1451249259Sdim let Uses = [NZCV]; 1452249259Sdim let isBranch = 1; 1453249259Sdim let isTerminator = 1; 1454249259Sdim} 1455249259Sdim 1456249259Sdim//===----------------------------------------------------------------------===// 1457249259Sdim// Conditional compare (immediate) instructions 1458249259Sdim//===----------------------------------------------------------------------===// 1459249259Sdim// Contains: CCMN, CCMP 1460249259Sdim 1461249259Sdimdef uimm4_asmoperand : AsmOperandClass { 1462249259Sdim let Name = "UImm4"; 1463249259Sdim let PredicateMethod = "isUImm<4>"; 1464249259Sdim let RenderMethod = "addImmOperands"; 1465249259Sdim let DiagnosticType = "UImm4"; 1466249259Sdim} 1467249259Sdim 1468249259Sdimdef uimm4 : Operand<i32> { 1469249259Sdim let ParserMatchClass = uimm4_asmoperand; 1470249259Sdim} 1471249259Sdim 1472249259Sdimdef uimm5 : Operand<i32> { 1473249259Sdim let ParserMatchClass = uimm5_asmoperand; 1474249259Sdim} 1475249259Sdim 1476249259Sdim// The only difference between this operand and the one for instructions like 1477249259Sdim// B.cc is that it's parsed manually. The other get parsed implicitly as part of 1478249259Sdim// the mnemonic handling. 1479249259Sdimdef cond_code_op_asmoperand : AsmOperandClass { 1480249259Sdim let Name = "CondCodeOp"; 1481249259Sdim let RenderMethod = "addCondCodeOperands"; 1482249259Sdim let PredicateMethod = "isCondCode"; 1483249259Sdim let ParserMethod = "ParseCondCodeOperand"; 1484249259Sdim let DiagnosticType = "CondCode"; 1485249259Sdim} 1486249259Sdim 1487249259Sdimdef cond_code_op : Operand<i32> { 1488249259Sdim let PrintMethod = "printCondCodeOperand"; 1489249259Sdim let ParserMatchClass = cond_code_op_asmoperand; 1490249259Sdim} 1491249259Sdim 1492249259Sdimclass A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1493249259Sdim : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs), 1494249259Sdim (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond), 1495249259Sdim !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"), 1496249259Sdim [], NoItinerary> { 1497249259Sdim let Defs = [NZCV]; 1498249259Sdim} 1499249259Sdim 1500249259Sdimdef CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">; 1501249259Sdimdef CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">; 1502249259Sdimdef CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">; 1503249259Sdimdef CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">; 1504249259Sdim 1505249259Sdim//===----------------------------------------------------------------------===// 1506249259Sdim// Conditional compare (register) instructions 1507249259Sdim//===----------------------------------------------------------------------===// 1508249259Sdim// Contains: CCMN, CCMP 1509249259Sdim 1510249259Sdimclass A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1511249259Sdim : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1, 1512249259Sdim (outs), 1513249259Sdim (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 1514249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 1515249259Sdim [], NoItinerary> { 1516249259Sdim let Defs = [NZCV]; 1517249259Sdim} 1518249259Sdim 1519249259Sdimdef CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">; 1520249259Sdimdef CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">; 1521249259Sdimdef CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">; 1522249259Sdimdef CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">; 1523249259Sdim 1524249259Sdim//===----------------------------------------------------------------------===// 1525249259Sdim// Conditional select instructions 1526249259Sdim//===----------------------------------------------------------------------===// 1527249259Sdim// Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG 1528249259Sdim 1529249259Sdim// Condition code which is encoded as the inversion (semantically rather than 1530249259Sdim// bitwise) in the instruction. 1531249259Sdimdef inv_cond_code_op_asmoperand : AsmOperandClass { 1532249259Sdim let Name = "InvCondCodeOp"; 1533249259Sdim let RenderMethod = "addInvCondCodeOperands"; 1534249259Sdim let PredicateMethod = "isCondCode"; 1535249259Sdim let ParserMethod = "ParseCondCodeOperand"; 1536249259Sdim let DiagnosticType = "CondCode"; 1537249259Sdim} 1538249259Sdim 1539249259Sdimdef inv_cond_code_op : Operand<i32> { 1540249259Sdim let ParserMatchClass = inv_cond_code_op_asmoperand; 1541249259Sdim} 1542249259Sdim 1543249259Sdim// Having a separate operand for the selectable use-case is debatable, but gives 1544249259Sdim// consistency with cond_code. 1545249259Sdimdef inv_cond_XFORM : SDNodeXForm<imm, [{ 1546249259Sdim A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue()); 1547249259Sdim return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32); 1548249259Sdim}]>; 1549249259Sdim 1550249259Sdimdef inv_cond_code 1551249259Sdim : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>; 1552249259Sdim 1553249259Sdim 1554249259Sdimmulticlass A64I_condselSizes<bit op, bits<2> op2, string asmop, 1555249259Sdim SDPatternOperator select> { 1556249259Sdim let Uses = [NZCV] in { 1557249259Sdim def wwwc : A64I_condsel<0b0, op, 0b0, op2, 1558249259Sdim (outs GPR32:$Rd), 1559249259Sdim (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond), 1560249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1561249259Sdim [(set i32:$Rd, (select i32:$Rn, i32:$Rm))], 1562249259Sdim NoItinerary>; 1563249259Sdim 1564249259Sdim 1565249259Sdim def xxxc : A64I_condsel<0b1, op, 0b0, op2, 1566249259Sdim (outs GPR64:$Rd), 1567249259Sdim (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond), 1568249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1569249259Sdim [(set i64:$Rd, (select i64:$Rn, i64:$Rm))], 1570249259Sdim NoItinerary>; 1571249259Sdim } 1572249259Sdim} 1573249259Sdim 1574249259Sdimdef simple_select 1575249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), 1576249259Sdim (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>; 1577249259Sdim 1578249259Sdimclass complex_select<SDPatternOperator opnode> 1579249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), 1580249259Sdim (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>; 1581249259Sdim 1582249259Sdim 1583249259Sdimdefm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>; 1584249259Sdimdefm CSINC : A64I_condselSizes<0b0, 0b01, "csinc", 1585249259Sdim complex_select<PatFrag<(ops node:$val), 1586249259Sdim (add node:$val, 1)>>>; 1587249259Sdimdefm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>; 1588249259Sdimdefm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>; 1589249259Sdim 1590249259Sdim// Now the instruction aliases, which fit nicely into LLVM's model: 1591249259Sdim 1592249259Sdimdef : InstAlias<"cset $Rd, $Cond", 1593249259Sdim (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1594249259Sdimdef : InstAlias<"cset $Rd, $Cond", 1595249259Sdim (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1596249259Sdimdef : InstAlias<"csetm $Rd, $Cond", 1597249259Sdim (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1598249259Sdimdef : InstAlias<"csetm $Rd, $Cond", 1599249259Sdim (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1600249259Sdimdef : InstAlias<"cinc $Rd, $Rn, $Cond", 1601249259Sdim (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1602249259Sdimdef : InstAlias<"cinc $Rd, $Rn, $Cond", 1603249259Sdim (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1604249259Sdimdef : InstAlias<"cinv $Rd, $Rn, $Cond", 1605249259Sdim (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1606249259Sdimdef : InstAlias<"cinv $Rd, $Rn, $Cond", 1607249259Sdim (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1608249259Sdimdef : InstAlias<"cneg $Rd, $Rn, $Cond", 1609249259Sdim (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1610249259Sdimdef : InstAlias<"cneg $Rd, $Rn, $Cond", 1611249259Sdim (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1612249259Sdim 1613249259Sdim// Finally some helper patterns. 1614249259Sdim 1615249259Sdim// For CSET (a.k.a. zero-extension of icmp) 1616249259Sdimdef : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1617249259Sdim (CSINCwwwc WZR, WZR, cond_code:$Cond)>; 1618249259Sdimdef : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1619249259Sdim (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>; 1620249259Sdim 1621249259Sdimdef : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1622249259Sdim (CSINCxxxc XZR, XZR, cond_code:$Cond)>; 1623249259Sdimdef : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1624249259Sdim (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>; 1625249259Sdim 1626249259Sdim// For CSETM (a.k.a. sign-extension of icmp) 1627249259Sdimdef : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1628249259Sdim (CSINVwwwc WZR, WZR, cond_code:$Cond)>; 1629249259Sdimdef : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1630249259Sdim (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>; 1631249259Sdim 1632249259Sdimdef : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1633249259Sdim (CSINVxxxc XZR, XZR, cond_code:$Cond)>; 1634249259Sdimdef : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1635249259Sdim (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>; 1636249259Sdim 1637249259Sdim// CINC, CINV and CNEG get dealt with automatically, which leaves the issue of 1638249259Sdim// commutativity. The instructions are to complex for isCommutable to be used, 1639249259Sdim// so we have to create the patterns manually: 1640249259Sdim 1641249259Sdim// No commutable pattern for CSEL since the commuted version is isomorphic. 1642249259Sdim 1643249259Sdim// CSINC 1644249259Sdimdef :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond), 1645249259Sdim (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1646249259Sdimdef :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond), 1647249259Sdim (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1648249259Sdim 1649249259Sdim// CSINV 1650249259Sdimdef :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1651249259Sdim (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1652249259Sdimdef :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1653249259Sdim (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1654249259Sdim 1655249259Sdim// CSNEG 1656249259Sdimdef :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1657249259Sdim (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1658249259Sdimdef :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1659249259Sdim (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1660249259Sdim 1661249259Sdim//===----------------------------------------------------------------------===// 1662249259Sdim// Data Processing (1 source) instructions 1663249259Sdim//===----------------------------------------------------------------------===// 1664249259Sdim// Contains: RBIT, REV16, REV, REV32, CLZ, CLS. 1665249259Sdim 1666249259Sdim// We define an unary operator which always fails. We will use this to 1667249259Sdim// define unary operators that cannot be matched. 1668249259Sdim 1669249259Sdimclass A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop, 1670249259Sdim list<dag> patterns, RegisterClass GPRrc, 1671249259Sdim InstrItinClass itin>: 1672249259Sdim A64I_dp_1src<sf, 1673249259Sdim 0, 1674249259Sdim 0b00000, 1675249259Sdim opcode, 1676249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), 1677249259Sdim (outs GPRrc:$Rd), 1678249259Sdim (ins GPRrc:$Rn), 1679249259Sdim patterns, 1680249259Sdim itin>; 1681249259Sdim 1682249259Sdimmulticlass A64I_dp_1src <bits<6> opcode, string asmop> { 1683249259Sdim let hasSideEffects = 0 in { 1684249259Sdim def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>; 1685249259Sdim def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>; 1686249259Sdim } 1687249259Sdim} 1688249259Sdim 1689249259Sdimdefm RBIT : A64I_dp_1src<0b000000, "rbit">; 1690249259Sdimdefm CLS : A64I_dp_1src<0b000101, "cls">; 1691249259Sdimdefm CLZ : A64I_dp_1src<0b000100, "clz">; 1692249259Sdim 1693249259Sdimdef : Pat<(ctlz i32:$Rn), (CLZww $Rn)>; 1694249259Sdimdef : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>; 1695249259Sdimdef : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>; 1696249259Sdimdef : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>; 1697249259Sdim 1698249259Sdimdef : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>; 1699249259Sdimdef : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>; 1700249259Sdimdef : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>; 1701249259Sdimdef : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>; 1702249259Sdim 1703249259Sdim 1704249259Sdimdef REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev", 1705249259Sdim [(set i32:$Rd, (bswap i32:$Rn))], 1706249259Sdim GPR32, NoItinerary>; 1707249259Sdimdef REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev", 1708249259Sdim [(set i64:$Rd, (bswap i64:$Rn))], 1709249259Sdim GPR64, NoItinerary>; 1710249259Sdimdef REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32", 1711249259Sdim [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))], 1712249259Sdim GPR64, NoItinerary>; 1713249259Sdimdef REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16", 1714249259Sdim [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))], 1715249259Sdim GPR32, 1716249259Sdim NoItinerary>; 1717249259Sdimdef REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>; 1718249259Sdim 1719249259Sdim//===----------------------------------------------------------------------===// 1720249259Sdim// Data Processing (2 sources) instructions 1721249259Sdim//===----------------------------------------------------------------------===// 1722249259Sdim// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, 1723249259Sdim// LSR, ASR, ROR 1724249259Sdim 1725249259Sdim 1726249259Sdimclass dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns, 1727249259Sdim RegisterClass GPRsp, 1728249259Sdim InstrItinClass itin>: 1729249259Sdim A64I_dp_2src<sf, 1730249259Sdim opcode, 1731249259Sdim 0, 1732249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 1733249259Sdim (outs GPRsp:$Rd), 1734249259Sdim (ins GPRsp:$Rn, GPRsp:$Rm), 1735249259Sdim patterns, 1736249259Sdim itin>; 1737249259Sdim 1738249259Sdimmulticlass dp_2src_crc<bit c, string asmop> { 1739249259Sdim def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0}, 1740249259Sdim !strconcat(asmop, "b"), [], GPR32, NoItinerary>; 1741249259Sdim def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1}, 1742249259Sdim !strconcat(asmop, "h"), [], GPR32, NoItinerary>; 1743249259Sdim def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0}, 1744249259Sdim !strconcat(asmop, "w"), [], GPR32, NoItinerary>; 1745249259Sdim def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0, 1746249259Sdim !strconcat(asmop, "x\t$Rd, $Rn, $Rm"), 1747249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [], 1748249259Sdim NoItinerary>; 1749249259Sdim} 1750249259Sdim 1751249259Sdimmulticlass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> { 1752249259Sdim def www : dp_2src_impl<0b0, 1753249259Sdim opcode, 1754249259Sdim asmop, 1755249259Sdim [(set i32:$Rd, 1756249259Sdim (op i32:$Rn, (i64 (zext i32:$Rm))))], 1757249259Sdim GPR32, 1758249259Sdim NoItinerary>; 1759249259Sdim def xxx : dp_2src_impl<0b1, 1760249259Sdim opcode, 1761249259Sdim asmop, 1762249259Sdim [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1763249259Sdim GPR64, 1764249259Sdim NoItinerary>; 1765249259Sdim} 1766249259Sdim 1767249259Sdim 1768249259Sdimmulticlass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> { 1769249259Sdim def www : dp_2src_impl<0b0, 1770249259Sdim opcode, 1771249259Sdim asmop, 1772249259Sdim [(set i32:$Rd, (op i32:$Rn, i32:$Rm))], 1773249259Sdim GPR32, 1774249259Sdim NoItinerary>; 1775249259Sdim def xxx : dp_2src_impl<0b1, 1776249259Sdim opcode, 1777249259Sdim asmop, 1778249259Sdim [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1779249259Sdim GPR64, 1780249259Sdim NoItinerary>; 1781249259Sdim} 1782249259Sdim 1783249259Sdim// Here we define the data processing 2 source instructions. 1784249259Sdimdefm CRC32 : dp_2src_crc<0b0, "crc32">; 1785249259Sdimdefm CRC32C : dp_2src_crc<0b1, "crc32c">; 1786249259Sdim 1787249259Sdimdefm UDIV : dp_2src<0b000010, "udiv", udiv>; 1788249259Sdimdefm SDIV : dp_2src<0b000011, "sdiv", sdiv>; 1789249259Sdim 1790249259Sdimdefm LSLV : dp_2src_zext<0b001000, "lsl", shl>; 1791249259Sdimdefm LSRV : dp_2src_zext<0b001001, "lsr", srl>; 1792249259Sdimdefm ASRV : dp_2src_zext<0b001010, "asr", sra>; 1793249259Sdimdefm RORV : dp_2src_zext<0b001011, "ror", rotr>; 1794249259Sdim 1795249259Sdim// Extra patterns for an incoming 64-bit value for a 32-bit 1796249259Sdim// operation. Since the LLVM operations are undefined (as in C) if the 1797249259Sdim// RHS is out of range, it's perfectly permissible to discard the high 1798249259Sdim// bits of the GPR64. 1799249259Sdimdef : Pat<(shl i32:$Rn, i64:$Rm), 1800249259Sdim (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1801249259Sdimdef : Pat<(srl i32:$Rn, i64:$Rm), 1802249259Sdim (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1803249259Sdimdef : Pat<(sra i32:$Rn, i64:$Rm), 1804249259Sdim (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1805249259Sdimdef : Pat<(rotr i32:$Rn, i64:$Rm), 1806249259Sdim (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1807249259Sdim 1808249259Sdim// Here we define the aliases for the data processing 2 source instructions. 1809249259Sdimdef LSL_mnemonic : MnemonicAlias<"lslv", "lsl">; 1810249259Sdimdef LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">; 1811249259Sdimdef ASR_menmonic : MnemonicAlias<"asrv", "asr">; 1812249259Sdimdef ROR_menmonic : MnemonicAlias<"rorv", "ror">; 1813249259Sdim 1814249259Sdim//===----------------------------------------------------------------------===// 1815249259Sdim// Data Processing (3 sources) instructions 1816249259Sdim//===----------------------------------------------------------------------===// 1817249259Sdim// Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH 1818249259Sdim// + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL 1819249259Sdim 1820249259Sdimclass A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg, 1821249259Sdim ValueType AccTy, RegisterClass SrcReg, 1822249259Sdim string asmop, dag pattern> 1823249259Sdim : A64I_dp3<sf, opcode, 1824249259Sdim (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra), 1825249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"), 1826249259Sdim [(set AccTy:$Rd, pattern)], NoItinerary> { 1827249259Sdim RegisterClass AccGPR = AccReg; 1828249259Sdim RegisterClass SrcGPR = SrcReg; 1829249259Sdim} 1830249259Sdim 1831249259Sdimdef MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd", 1832249259Sdim (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1833249259Sdimdef MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd", 1834249259Sdim (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1835249259Sdim 1836249259Sdimdef MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub", 1837249259Sdim (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1838249259Sdimdef MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub", 1839249259Sdim (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1840249259Sdim 1841249259Sdimdef SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl", 1842249259Sdim (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1843249259Sdimdef SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl", 1844249259Sdim (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1845249259Sdim 1846249259Sdimdef UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl", 1847249259Sdim (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1848249259Sdimdef UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl", 1849249259Sdim (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1850249259Sdim 1851249259Sdimlet isCommutable = 1, PostEncoderMethod = "fixMulHigh" in { 1852249259Sdim def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd), 1853249259Sdim (ins GPR64:$Rn, GPR64:$Rm), 1854249259Sdim "umulh\t$Rd, $Rn, $Rm", 1855249259Sdim [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))], 1856249259Sdim NoItinerary>; 1857249259Sdim 1858249259Sdim def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd), 1859249259Sdim (ins GPR64:$Rn, GPR64:$Rm), 1860249259Sdim "smulh\t$Rd, $Rn, $Rm", 1861249259Sdim [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))], 1862249259Sdim NoItinerary>; 1863249259Sdim} 1864249259Sdim 1865249259Sdimmulticlass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST, 1866249259Sdim Register ZR, dag pattern> { 1867249259Sdim def : InstAlias<asmop # " $Rd, $Rn, $Rm", 1868249259Sdim (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>; 1869249259Sdim 1870249259Sdim def : Pat<pattern, (INST $Rn, $Rm, ZR)>; 1871249259Sdim} 1872249259Sdim 1873249259Sdimdefm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>; 1874249259Sdimdefm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>; 1875249259Sdim 1876249259Sdimdefm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR, 1877249259Sdim (sub 0, (mul i32:$Rn, i32:$Rm))>; 1878249259Sdimdefm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR, 1879249259Sdim (sub 0, (mul i64:$Rn, i64:$Rm))>; 1880249259Sdim 1881249259Sdimdefm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR, 1882249259Sdim (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>; 1883249259Sdimdefm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR, 1884249259Sdim (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1885249259Sdim 1886249259Sdimdefm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR, 1887249259Sdim (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>; 1888249259Sdimdefm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR, 1889249259Sdim (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1890249259Sdim 1891249259Sdim 1892249259Sdim//===----------------------------------------------------------------------===// 1893249259Sdim// Exception generation 1894249259Sdim//===----------------------------------------------------------------------===// 1895249259Sdim// Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3 1896249259Sdim 1897249259Sdimdef uimm16_asmoperand : AsmOperandClass { 1898249259Sdim let Name = "UImm16"; 1899249259Sdim let PredicateMethod = "isUImm<16>"; 1900249259Sdim let RenderMethod = "addImmOperands"; 1901249259Sdim let DiagnosticType = "UImm16"; 1902249259Sdim} 1903249259Sdim 1904249259Sdimdef uimm16 : Operand<i32> { 1905249259Sdim let ParserMatchClass = uimm16_asmoperand; 1906249259Sdim} 1907249259Sdim 1908249259Sdimclass A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop> 1909249259Sdim : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16), 1910249259Sdim !strconcat(asmop, "\t$UImm16"), [], NoItinerary> { 1911249259Sdim let isBranch = 1; 1912249259Sdim let isTerminator = 1; 1913249259Sdim} 1914249259Sdim 1915249259Sdimdef SVCi : A64I_exceptImpl<0b000, 0b01, "svc">; 1916249259Sdimdef HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">; 1917249259Sdimdef SMCi : A64I_exceptImpl<0b000, 0b11, "smc">; 1918249259Sdimdef BRKi : A64I_exceptImpl<0b001, 0b00, "brk">; 1919249259Sdimdef HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">; 1920249259Sdim 1921249259Sdimdef DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">; 1922249259Sdimdef DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">; 1923249259Sdimdef DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">; 1924249259Sdim 1925249259Sdim// The immediate is optional for the DCPS instructions, defaulting to 0. 1926249259Sdimdef : InstAlias<"dcps1", (DCPS1i 0)>; 1927249259Sdimdef : InstAlias<"dcps2", (DCPS2i 0)>; 1928249259Sdimdef : InstAlias<"dcps3", (DCPS3i 0)>; 1929249259Sdim 1930249259Sdim//===----------------------------------------------------------------------===// 1931249259Sdim// Extract (immediate) 1932249259Sdim//===----------------------------------------------------------------------===// 1933249259Sdim// Contains: EXTR + alias ROR 1934249259Sdim 1935249259Sdimdef EXTRwwwi : A64I_extract<0b0, 0b000, 0b0, 1936249259Sdim (outs GPR32:$Rd), 1937249259Sdim (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB), 1938249259Sdim "extr\t$Rd, $Rn, $Rm, $LSB", 1939249259Sdim [(set i32:$Rd, 1940249259Sdim (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))], 1941249259Sdim NoItinerary>; 1942249259Sdimdef EXTRxxxi : A64I_extract<0b1, 0b000, 0b1, 1943249259Sdim (outs GPR64:$Rd), 1944249259Sdim (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB), 1945249259Sdim "extr\t$Rd, $Rn, $Rm, $LSB", 1946249259Sdim [(set i64:$Rd, 1947249259Sdim (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))], 1948249259Sdim NoItinerary>; 1949249259Sdim 1950249259Sdimdef : InstAlias<"ror $Rd, $Rs, $LSB", 1951249259Sdim (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>; 1952249259Sdimdef : InstAlias<"ror $Rd, $Rs, $LSB", 1953249259Sdim (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>; 1954249259Sdim 1955249259Sdimdef : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB), 1956249259Sdim (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>; 1957249259Sdimdef : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB), 1958249259Sdim (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>; 1959249259Sdim 1960249259Sdim//===----------------------------------------------------------------------===// 1961249259Sdim// Floating-point compare instructions 1962249259Sdim//===----------------------------------------------------------------------===// 1963249259Sdim// Contains: FCMP, FCMPE 1964249259Sdim 1965249259Sdimdef fpzero_asmoperand : AsmOperandClass { 1966249259Sdim let Name = "FPZero"; 1967249259Sdim let ParserMethod = "ParseFPImmOperand"; 1968249259Sdim let DiagnosticType = "FPZero"; 1969249259Sdim} 1970249259Sdim 1971249259Sdimdef fpz32 : Operand<f32>, 1972249259Sdim ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> { 1973249259Sdim let ParserMatchClass = fpzero_asmoperand; 1974249259Sdim let PrintMethod = "printFPZeroOperand"; 1975249259Sdim let DecoderMethod = "DecodeFPZeroOperand"; 1976249259Sdim} 1977249259Sdim 1978249259Sdimdef fpz64 : Operand<f64>, 1979249259Sdim ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1980249259Sdim let ParserMatchClass = fpzero_asmoperand; 1981249259Sdim let PrintMethod = "printFPZeroOperand"; 1982249259Sdim let DecoderMethod = "DecodeFPZeroOperand"; 1983249259Sdim} 1984249259Sdim 1985263508Sdimdef fpz64movi : Operand<i64>, 1986263508Sdim ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1987263508Sdim let ParserMatchClass = fpzero_asmoperand; 1988263508Sdim let PrintMethod = "printFPZeroOperand"; 1989263508Sdim let DecoderMethod = "DecodeFPZeroOperand"; 1990263508Sdim} 1991263508Sdim 1992249259Sdimmulticlass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> { 1993249259Sdim def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0}, 1994249259Sdim (outs), ins, "fcmp\t$Rn, $Rm", [pattern], 1995249259Sdim NoItinerary> { 1996249259Sdim let Defs = [NZCV]; 1997249259Sdim } 1998249259Sdim 1999249259Sdim def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0}, 2000249259Sdim (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> { 2001249259Sdim let Defs = [NZCV]; 2002249259Sdim } 2003249259Sdim} 2004249259Sdim 2005249259Sdimdefm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), 2006249259Sdim (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>; 2007249259Sdimdefm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), 2008249259Sdim (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>; 2009249259Sdim 2010249259Sdim// What would be Rm should be written as 0; note that even though it's called 2011249259Sdim// "$Rm" here to fit in with the InstrFormats, it's actually an immediate. 2012249259Sdimdefm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm), 2013249259Sdim (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>; 2014249259Sdim 2015249259Sdimdefm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm), 2016249259Sdim (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>; 2017249259Sdim 2018249259Sdim 2019249259Sdim//===----------------------------------------------------------------------===// 2020249259Sdim// Floating-point conditional compare instructions 2021249259Sdim//===----------------------------------------------------------------------===// 2022249259Sdim// Contains: FCCMP, FCCMPE 2023249259Sdim 2024249259Sdimclass A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop> 2025249259Sdim : A64I_fpccmp<0b0, 0b0, type, op, 2026249259Sdim (outs), 2027249259Sdim (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 2028249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 2029249259Sdim [], NoItinerary> { 2030249259Sdim let Defs = [NZCV]; 2031249259Sdim} 2032249259Sdim 2033249259Sdimdef FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">; 2034249259Sdimdef FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">; 2035249259Sdimdef FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">; 2036249259Sdimdef FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">; 2037249259Sdim 2038249259Sdim//===----------------------------------------------------------------------===// 2039249259Sdim// Floating-point conditional select instructions 2040249259Sdim//===----------------------------------------------------------------------===// 2041249259Sdim// Contains: FCSEL 2042249259Sdim 2043249259Sdimlet Uses = [NZCV] in { 2044249259Sdim def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd), 2045249259Sdim (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond), 2046249259Sdim "fcsel\t$Rd, $Rn, $Rm, $Cond", 2047249259Sdim [(set f32:$Rd, 2048249259Sdim (simple_select f32:$Rn, f32:$Rm))], 2049249259Sdim NoItinerary>; 2050249259Sdim 2051249259Sdim 2052249259Sdim def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd), 2053249259Sdim (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond), 2054249259Sdim "fcsel\t$Rd, $Rn, $Rm, $Cond", 2055249259Sdim [(set f64:$Rd, 2056249259Sdim (simple_select f64:$Rn, f64:$Rm))], 2057249259Sdim NoItinerary>; 2058249259Sdim} 2059249259Sdim 2060249259Sdim//===----------------------------------------------------------------------===// 2061249259Sdim// Floating-point data-processing (1 source) 2062249259Sdim//===----------------------------------------------------------------------===// 2063249259Sdim// Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI]. 2064249259Sdim 2065249259Sdimdef FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val), 2066249259Sdim [{ (void)N; return false; }]>; 2067249259Sdim 2068249259Sdim// First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d" 2069249259Sdim// syntax. Default to no pattern because most are odd enough not to have one. 2070249259Sdimmulticlass A64I_fpdp1sizes<bits<6> opcode, string asmstr, 2071249259Sdim SDPatternOperator opnode = FPNoUnop> { 2072249259Sdim def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn), 2073249259Sdim !strconcat(asmstr, "\t$Rd, $Rn"), 2074249259Sdim [(set f32:$Rd, (opnode f32:$Rn))], 2075249259Sdim NoItinerary>; 2076249259Sdim 2077249259Sdim def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn), 2078249259Sdim !strconcat(asmstr, "\t$Rd, $Rn"), 2079249259Sdim [(set f64:$Rd, (opnode f64:$Rn))], 2080249259Sdim NoItinerary>; 2081249259Sdim} 2082249259Sdim 2083249259Sdimdefm FMOV : A64I_fpdp1sizes<0b000000, "fmov">; 2084249259Sdimdefm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>; 2085249259Sdimdefm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>; 2086249259Sdimdefm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>; 2087249259Sdim 2088249259Sdimdefm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">; 2089249259Sdimdefm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>; 2090249259Sdimdefm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>; 2091249259Sdimdefm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>; 2092249259Sdimdefm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">; 2093249259Sdimdefm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>; 2094249259Sdimdefm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>; 2095249259Sdim 2096249259Sdim// The FCVT instrucitons have different source and destination register-types, 2097249259Sdim// but the fields are uniform everywhere a D-register (say) crops up. Package 2098249259Sdim// this information in a Record. 2099249259Sdimclass FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> { 2100249259Sdim RegisterClass Class = rc; 2101249259Sdim ValueType VT = vt; 2102249259Sdim bit t1 = fld{1}; 2103249259Sdim bit t0 = fld{0}; 2104249259Sdim} 2105249259Sdim 2106249259Sdimdef FCVT16 : FCVTRegType<FPR16, 0b11, f16>; 2107249259Sdimdef FCVT32 : FCVTRegType<FPR32, 0b00, f32>; 2108249259Sdimdef FCVT64 : FCVTRegType<FPR64, 0b01, f64>; 2109249259Sdim 2110249259Sdimclass A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode> 2111249259Sdim : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0}, 2112249259Sdim {0,0,0,1, DestReg.t1, DestReg.t0}, 2113249259Sdim (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn), 2114249259Sdim "fcvt\t$Rd, $Rn", 2115249259Sdim [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>; 2116249259Sdim 2117249259Sdimdef FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>; 2118249259Sdimdef FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>; 2119249259Sdimdef FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>; 2120249259Sdimdef FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>; 2121249259Sdimdef FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>; 2122249259Sdimdef FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>; 2123249259Sdim 2124249259Sdim 2125249259Sdim//===----------------------------------------------------------------------===// 2126249259Sdim// Floating-point data-processing (2 sources) instructions 2127249259Sdim//===----------------------------------------------------------------------===// 2128249259Sdim// Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL 2129249259Sdim 2130249259Sdimdef FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs), 2131249259Sdim [{ (void)N; return false; }]>; 2132249259Sdim 2133249259Sdimmulticlass A64I_fpdp2sizes<bits<4> opcode, string asmstr, 2134249259Sdim SDPatternOperator opnode> { 2135249259Sdim def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode, 2136249259Sdim (outs FPR32:$Rd), 2137249259Sdim (ins FPR32:$Rn, FPR32:$Rm), 2138249259Sdim !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2139249259Sdim [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))], 2140249259Sdim NoItinerary>; 2141249259Sdim 2142249259Sdim def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode, 2143249259Sdim (outs FPR64:$Rd), 2144249259Sdim (ins FPR64:$Rn, FPR64:$Rm), 2145249259Sdim !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2146249259Sdim [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))], 2147249259Sdim NoItinerary>; 2148249259Sdim} 2149249259Sdim 2150249259Sdimlet isCommutable = 1 in { 2151249259Sdim defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>; 2152249259Sdim defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>; 2153249259Sdim 2154249259Sdim // No patterns for these. 2155249259Sdim defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>; 2156249259Sdim defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>; 2157249259Sdim defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>; 2158249259Sdim defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>; 2159249259Sdim 2160249259Sdim defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul", 2161249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 2162249259Sdim (fneg (fmul node:$lhs, node:$rhs))> >; 2163249259Sdim} 2164249259Sdim 2165249259Sdimdefm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>; 2166249259Sdimdefm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>; 2167249259Sdim 2168249259Sdim//===----------------------------------------------------------------------===// 2169249259Sdim// Floating-point data-processing (3 sources) instructions 2170249259Sdim//===----------------------------------------------------------------------===// 2171249259Sdim// Contains: FMADD, FMSUB, FNMADD, FNMSUB 2172249259Sdim 2173249259Sdimdef fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2174249259Sdim (fma (fneg node:$Rn), node:$Rm, node:$Ra)>; 2175249259Sdimdef fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2176249259Sdim (fma node:$Rn, node:$Rm, (fneg node:$Ra))>; 2177249259Sdimdef fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2178249259Sdim (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>; 2179249259Sdim 2180249259Sdimclass A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT, 2181249259Sdim bits<2> type, bit o1, bit o0, SDPatternOperator fmakind> 2182249259Sdim : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd), 2183249259Sdim (ins FPR:$Rn, FPR:$Rm, FPR:$Ra), 2184249259Sdim !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"), 2185249259Sdim [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))], 2186249259Sdim NoItinerary>; 2187249259Sdim 2188249259Sdimdef FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>; 2189249259Sdimdef FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>; 2190249259Sdimdef FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>; 2191249259Sdimdef FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>; 2192249259Sdim 2193249259Sdimdef FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>; 2194249259Sdimdef FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>; 2195249259Sdimdef FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>; 2196249259Sdimdef FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>; 2197249259Sdim 2198263508Sdim// Extra patterns for when we're allowed to optimise separate multiplication and 2199263508Sdim// addition. 2200263508Sdimlet Predicates = [HasFPARMv8, UseFusedMAC] in { 2201263508Sdimdef : Pat<(f32 (fadd FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2202263508Sdim (FMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2203263508Sdimdef : Pat<(f32 (fsub FPR32:$Ra, (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2204263508Sdim (FMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2205263508Sdimdef : Pat<(f32 (fsub (f32 (fmul FPR32:$Rn, FPR32:$Rm)), FPR32:$Ra)), 2206263508Sdim (FNMADDssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2207263508Sdimdef : Pat<(f32 (fsub (f32 (fneg FPR32:$Ra)), (f32 (fmul FPR32:$Rn, FPR32:$Rm)))), 2208263508Sdim (FNMSUBssss FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>; 2209263508Sdim 2210263508Sdimdef : Pat<(f64 (fadd FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2211263508Sdim (FMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2212263508Sdimdef : Pat<(f64 (fsub FPR64:$Ra, (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2213263508Sdim (FMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2214263508Sdimdef : Pat<(f64 (fsub (f64 (fmul FPR64:$Rn, FPR64:$Rm)), FPR64:$Ra)), 2215263508Sdim (FNMADDdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2216263508Sdimdef : Pat<(f64 (fsub (f64 (fneg FPR64:$Ra)), (f64 (fmul FPR64:$Rn, FPR64:$Rm)))), 2217263508Sdim (FNMSUBdddd FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>; 2218263508Sdim} 2219263508Sdim 2220263508Sdim 2221249259Sdim//===----------------------------------------------------------------------===// 2222249259Sdim// Floating-point <-> fixed-point conversion instructions 2223249259Sdim//===----------------------------------------------------------------------===// 2224249259Sdim// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2225249259Sdim 2226249259Sdim// #1-#32 allowed, encoded as "64 - <specified imm> 2227249259Sdimdef fixedpos_asmoperand_i32 : AsmOperandClass { 2228249259Sdim let Name = "CVTFixedPos32"; 2229249259Sdim let RenderMethod = "addCVTFixedPosOperands"; 2230249259Sdim let PredicateMethod = "isCVTFixedPos<32>"; 2231249259Sdim let DiagnosticType = "CVTFixedPos32"; 2232249259Sdim} 2233249259Sdim 2234249259Sdim// Also encoded as "64 - <specified imm>" but #1-#64 allowed. 2235249259Sdimdef fixedpos_asmoperand_i64 : AsmOperandClass { 2236249259Sdim let Name = "CVTFixedPos64"; 2237249259Sdim let RenderMethod = "addCVTFixedPosOperands"; 2238249259Sdim let PredicateMethod = "isCVTFixedPos<64>"; 2239249259Sdim let DiagnosticType = "CVTFixedPos64"; 2240249259Sdim} 2241249259Sdim 2242249259Sdim// We need the cartesian product of f32/f64 i32/i64 operands for 2243249259Sdim// conversions: 2244249259Sdim// + Selection needs to use operands of correct floating type 2245249259Sdim// + Assembly parsing and decoding depend on integer width 2246249259Sdimclass cvtfix_i32_op<ValueType FloatVT> 2247249259Sdim : Operand<FloatVT>, 2248249259Sdim ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> { 2249249259Sdim let ParserMatchClass = fixedpos_asmoperand_i32; 2250249259Sdim let DecoderMethod = "DecodeCVT32FixedPosOperand"; 2251249259Sdim let PrintMethod = "printCVTFixedPosOperand"; 2252249259Sdim} 2253249259Sdim 2254249259Sdimclass cvtfix_i64_op<ValueType FloatVT> 2255249259Sdim : Operand<FloatVT>, 2256249259Sdim ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> { 2257249259Sdim let ParserMatchClass = fixedpos_asmoperand_i64; 2258249259Sdim let PrintMethod = "printCVTFixedPosOperand"; 2259249259Sdim} 2260249259Sdim 2261249259Sdim// Because of the proliferation of weird operands, it's not really 2262249259Sdim// worth going for a multiclass here. Oh well. 2263249259Sdim 2264249259Sdimclass A64I_fptofix<bit sf, bits<2> type, bits<3> opcode, 2265249259Sdim RegisterClass GPR, RegisterClass FPR, 2266249259Sdim ValueType DstTy, ValueType SrcTy, 2267249259Sdim Operand scale_op, string asmop, SDNode cvtop> 2268249259Sdim : A64I_fpfixed<sf, 0b0, type, 0b11, opcode, 2269249259Sdim (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale), 2270249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2271249259Sdim [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))], 2272249259Sdim NoItinerary>; 2273249259Sdim 2274249259Sdimdef FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32, 2275249259Sdim cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>; 2276249259Sdimdef FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32, 2277249259Sdim cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>; 2278249259Sdimdef FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32, 2279249259Sdim cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>; 2280249259Sdimdef FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32, 2281249259Sdim cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>; 2282249259Sdim 2283249259Sdimdef FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64, 2284249259Sdim cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>; 2285249259Sdimdef FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64, 2286249259Sdim cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>; 2287249259Sdimdef FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64, 2288249259Sdim cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>; 2289249259Sdimdef FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64, 2290249259Sdim cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>; 2291249259Sdim 2292249259Sdim 2293249259Sdimclass A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode, 2294249259Sdim RegisterClass FPR, RegisterClass GPR, 2295249259Sdim ValueType DstTy, ValueType SrcTy, 2296249259Sdim Operand scale_op, string asmop, SDNode cvtop> 2297249259Sdim : A64I_fpfixed<sf, 0b0, type, 0b00, opcode, 2298249259Sdim (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale), 2299249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2300249259Sdim [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))], 2301249259Sdim NoItinerary>; 2302249259Sdim 2303249259Sdimdef SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32, 2304249259Sdim cvtfix_i32_op<f32>, "scvtf", sint_to_fp>; 2305249259Sdimdef SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64, 2306249259Sdim cvtfix_i64_op<f32>, "scvtf", sint_to_fp>; 2307249259Sdimdef UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32, 2308249259Sdim cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>; 2309249259Sdimdef UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64, 2310249259Sdim cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>; 2311249259Sdimdef SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32, 2312249259Sdim cvtfix_i32_op<f64>, "scvtf", sint_to_fp>; 2313249259Sdimdef SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64, 2314249259Sdim cvtfix_i64_op<f64>, "scvtf", sint_to_fp>; 2315249259Sdimdef UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32, 2316249259Sdim cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>; 2317249259Sdimdef UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64, 2318249259Sdim cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>; 2319249259Sdim 2320249259Sdim//===----------------------------------------------------------------------===// 2321249259Sdim// Floating-point <-> integer conversion instructions 2322249259Sdim//===----------------------------------------------------------------------===// 2323249259Sdim// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2324249259Sdim 2325249259Sdimclass A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode, 2326249259Sdim RegisterClass DestPR, RegisterClass SrcPR, string asmop> 2327249259Sdim : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn), 2328249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>; 2329249259Sdim 2330249259Sdimmulticlass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> { 2331249259Sdim def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, 2332249259Sdim GPR32, FPR32, asmop # "s">; 2333249259Sdim def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, 2334249259Sdim GPR64, FPR32, asmop # "s">; 2335249259Sdim def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, 2336249259Sdim GPR32, FPR32, asmop # "u">; 2337249259Sdim def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, 2338249259Sdim GPR64, FPR32, asmop # "u">; 2339249259Sdim 2340249259Sdim def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, 2341249259Sdim GPR32, FPR64, asmop # "s">; 2342249259Sdim def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, 2343249259Sdim GPR64, FPR64, asmop # "s">; 2344249259Sdim def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, 2345249259Sdim GPR32, FPR64, asmop # "u">; 2346249259Sdim def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, 2347249259Sdim GPR64, FPR64, asmop # "u">; 2348249259Sdim} 2349249259Sdim 2350249259Sdimdefm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">; 2351249259Sdimdefm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">; 2352249259Sdimdefm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">; 2353249259Sdimdefm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">; 2354249259Sdimdefm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">; 2355249259Sdim 2356263508Sdimlet Predicates = [HasFPARMv8] in { 2357249259Sdimdef : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>; 2358249259Sdimdef : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>; 2359249259Sdimdef : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>; 2360249259Sdimdef : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>; 2361249259Sdimdef : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>; 2362249259Sdimdef : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>; 2363249259Sdimdef : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>; 2364249259Sdimdef : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>; 2365263508Sdim} 2366249259Sdim 2367249259Sdimmulticlass A64I_inttofp<bit o0, string asmop> { 2368249259Sdim def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>; 2369249259Sdim def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>; 2370249259Sdim def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>; 2371249259Sdim def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>; 2372249259Sdim} 2373249259Sdim 2374249259Sdimdefm S : A64I_inttofp<0b0, "scvtf">; 2375249259Sdimdefm U : A64I_inttofp<0b1, "ucvtf">; 2376249259Sdim 2377263508Sdimlet Predicates = [HasFPARMv8] in { 2378249259Sdimdef : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>; 2379249259Sdimdef : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>; 2380249259Sdimdef : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>; 2381249259Sdimdef : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>; 2382249259Sdimdef : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>; 2383249259Sdimdef : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>; 2384249259Sdimdef : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>; 2385249259Sdimdef : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>; 2386263508Sdim} 2387249259Sdim 2388249259Sdimdef FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">; 2389249259Sdimdef FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">; 2390249259Sdimdef FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">; 2391249259Sdimdef FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">; 2392249259Sdim 2393263508Sdimlet Predicates = [HasFPARMv8] in { 2394249259Sdimdef : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>; 2395249259Sdimdef : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>; 2396249259Sdimdef : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>; 2397249259Sdimdef : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>; 2398263508Sdim} 2399249259Sdim 2400249259Sdimdef lane1_asmoperand : AsmOperandClass { 2401249259Sdim let Name = "Lane1"; 2402249259Sdim let RenderMethod = "addImmOperands"; 2403249259Sdim let DiagnosticType = "Lane1"; 2404249259Sdim} 2405249259Sdim 2406249259Sdimdef lane1 : Operand<i32> { 2407249259Sdim let ParserMatchClass = lane1_asmoperand; 2408249259Sdim let PrintMethod = "printBareImmOperand"; 2409249259Sdim} 2410249259Sdim 2411249259Sdimlet DecoderMethod = "DecodeFMOVLaneInstruction" in { 2412249259Sdim def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110, 2413249259Sdim (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane), 2414249259Sdim "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>; 2415249259Sdim 2416249259Sdim def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111, 2417249259Sdim (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane), 2418249259Sdim "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>; 2419249259Sdim} 2420249259Sdim 2421263508Sdimlet Predicates = [HasFPARMv8] in { 2422249259Sdimdef : InstAlias<"fmov $Rd, $Rn.2d[$Lane]", 2423249259Sdim (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>; 2424249259Sdim 2425249259Sdimdef : InstAlias<"fmov $Rd.2d[$Lane], $Rn", 2426249259Sdim (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>; 2427263508Sdim} 2428249259Sdim 2429249259Sdim//===----------------------------------------------------------------------===// 2430249259Sdim// Floating-point immediate instructions 2431249259Sdim//===----------------------------------------------------------------------===// 2432249259Sdim// Contains: FMOV 2433249259Sdim 2434249259Sdimdef fpimm_asmoperand : AsmOperandClass { 2435249259Sdim let Name = "FMOVImm"; 2436249259Sdim let ParserMethod = "ParseFPImmOperand"; 2437249259Sdim let DiagnosticType = "FPImm"; 2438249259Sdim} 2439249259Sdim 2440249259Sdim// The MCOperand for these instructions are the encoded 8-bit values. 2441249259Sdimdef SDXF_fpimm : SDNodeXForm<fpimm, [{ 2442249259Sdim uint32_t Imm8; 2443249259Sdim A64Imms::isFPImm(N->getValueAPF(), Imm8); 2444249259Sdim return CurDAG->getTargetConstant(Imm8, MVT::i32); 2445249259Sdim}]>; 2446249259Sdim 2447249259Sdimclass fmov_operand<ValueType FT> 2448249259Sdim : Operand<i32>, 2449249259Sdim PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }], 2450249259Sdim SDXF_fpimm> { 2451249259Sdim let PrintMethod = "printFPImmOperand"; 2452249259Sdim let ParserMatchClass = fpimm_asmoperand; 2453249259Sdim} 2454249259Sdim 2455249259Sdimdef fmov32_operand : fmov_operand<f32>; 2456249259Sdimdef fmov64_operand : fmov_operand<f64>; 2457249259Sdim 2458249259Sdimclass A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT, 2459249259Sdim Operand fmov_operand> 2460249259Sdim : A64I_fpimm<0b0, 0b0, type, 0b00000, 2461249259Sdim (outs Reg:$Rd), 2462249259Sdim (ins fmov_operand:$Imm8), 2463249259Sdim "fmov\t$Rd, $Imm8", 2464249259Sdim [(set VT:$Rd, fmov_operand:$Imm8)], 2465249259Sdim NoItinerary>; 2466249259Sdim 2467249259Sdimdef FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>; 2468249259Sdimdef FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>; 2469249259Sdim 2470249259Sdim//===----------------------------------------------------------------------===// 2471249259Sdim// Load-register (literal) instructions 2472249259Sdim//===----------------------------------------------------------------------===// 2473249259Sdim// Contains: LDR, LDRSW, PRFM 2474249259Sdim 2475249259Sdimdef ldrlit_label_asmoperand : AsmOperandClass { 2476249259Sdim let Name = "LoadLitLabel"; 2477249259Sdim let RenderMethod = "addLabelOperands<19, 4>"; 2478249259Sdim let DiagnosticType = "Label"; 2479249259Sdim} 2480249259Sdim 2481249259Sdimdef ldrlit_label : Operand<i64> { 2482249259Sdim let EncoderMethod = "getLoadLitLabelOpValue"; 2483249259Sdim 2484249259Sdim // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 2485249259Sdim let PrintMethod = "printLabelOperand<19, 4>"; 2486249259Sdim let ParserMatchClass = ldrlit_label_asmoperand; 2487249259Sdim let OperandType = "OPERAND_PCREL"; 2488249259Sdim} 2489249259Sdim 2490249259Sdim// Various instructions take an immediate value (which can always be used), 2491249259Sdim// where some numbers have a symbolic name to make things easier. These operands 2492249259Sdim// and the associated functions abstract away the differences. 2493249259Sdimmulticlass namedimm<string prefix, string mapper> { 2494249259Sdim def _asmoperand : AsmOperandClass { 2495249259Sdim let Name = "NamedImm" # prefix; 2496249259Sdim let PredicateMethod = "isUImm"; 2497249259Sdim let RenderMethod = "addImmOperands"; 2498249259Sdim let ParserMethod = "ParseNamedImmOperand<" # mapper # ">"; 2499249259Sdim let DiagnosticType = "NamedImm_" # prefix; 2500249259Sdim } 2501249259Sdim 2502249259Sdim def _op : Operand<i32> { 2503249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 2504249259Sdim let PrintMethod = "printNamedImmOperand<" # mapper # ">"; 2505249259Sdim let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">"; 2506249259Sdim } 2507249259Sdim} 2508249259Sdim 2509249259Sdimdefm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">; 2510249259Sdim 2511249259Sdimclass A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg, 2512249259Sdim list<dag> patterns = []> 2513249259Sdim : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19), 2514249259Sdim "ldr\t$Rt, $Imm19", patterns, NoItinerary>; 2515249259Sdim 2516249259Sdimlet mayLoad = 1 in { 2517249259Sdim def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>; 2518249259Sdim def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>; 2519249259Sdim} 2520249259Sdim 2521263508Sdimlet Predicates = [HasFPARMv8] in { 2522249259Sdimdef LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>; 2523249259Sdimdef LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>; 2524263508Sdim} 2525249259Sdim 2526249259Sdimlet mayLoad = 1 in { 2527263508Sdim let Predicates = [HasFPARMv8] in { 2528249259Sdim def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>; 2529263508Sdim } 2530249259Sdim 2531249259Sdim 2532249259Sdim def LDRSWx_lit : A64I_LDRlit<0b10, 0b0, 2533249259Sdim (outs GPR64:$Rt), 2534249259Sdim (ins ldrlit_label:$Imm19), 2535249259Sdim "ldrsw\t$Rt, $Imm19", 2536249259Sdim [], NoItinerary>; 2537249259Sdim 2538249259Sdim def PRFM_lit : A64I_LDRlit<0b11, 0b0, 2539249259Sdim (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19), 2540249259Sdim "prfm\t$Rt, $Imm19", 2541249259Sdim [], NoItinerary>; 2542249259Sdim} 2543249259Sdim 2544249259Sdim//===----------------------------------------------------------------------===// 2545249259Sdim// Load-store exclusive instructions 2546249259Sdim//===----------------------------------------------------------------------===// 2547249259Sdim// Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB, 2548249259Sdim// STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB, 2549249259Sdim// STLRH, STLR, LDARB, LDARH, LDAR 2550249259Sdim 2551249259Sdim// Since these instructions have the undefined register bits set to 1 in 2552249259Sdim// their canonical form, we need a post encoder method to set those bits 2553249259Sdim// to 1 when encoding these instructions. We do this using the 2554249259Sdim// fixLoadStoreExclusive function. This function has template parameters: 2555249259Sdim// 2556249259Sdim// fixLoadStoreExclusive<int hasRs, int hasRt2> 2557249259Sdim// 2558249259Sdim// hasRs indicates that the instruction uses the Rs field, so we won't set 2559249259Sdim// it to 1 (and the same for Rt2). We don't need template parameters for 2560249259Sdim// the other register fiels since Rt and Rn are always used. 2561249259Sdim 2562249259Sdim// This operand parses a GPR64xsp register, followed by an optional immediate 2563249259Sdim// #0. 2564249259Sdimdef GPR64xsp0_asmoperand : AsmOperandClass { 2565249259Sdim let Name = "GPR64xsp0"; 2566249259Sdim let PredicateMethod = "isWrappedReg"; 2567249259Sdim let RenderMethod = "addRegOperands"; 2568249259Sdim let ParserMethod = "ParseLSXAddressOperand"; 2569249259Sdim // Diagnostics are provided by ParserMethod 2570249259Sdim} 2571249259Sdim 2572249259Sdimdef GPR64xsp0 : RegisterOperand<GPR64xsp> { 2573249259Sdim let ParserMatchClass = GPR64xsp0_asmoperand; 2574249259Sdim} 2575249259Sdim 2576249259Sdim//===---------------------------------- 2577249259Sdim// Store-exclusive (releasing & normal) 2578249259Sdim//===---------------------------------- 2579249259Sdim 2580249259Sdimclass A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2581249259Sdim dag ins, list<dag> pat, 2582249259Sdim InstrItinClass itin> : 2583249259Sdim A64I_LDSTex_stn <size, 2584249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2585249259Sdim outs, ins, 2586249259Sdim !strconcat(asm, "\t$Rs, $Rt, [$Rn]"), 2587249259Sdim pat, itin> { 2588249259Sdim let mayStore = 1; 2589249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; 2590249259Sdim} 2591249259Sdim 2592249259Sdimmulticlass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { 2593249259Sdim def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2594249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2595249259Sdim [], NoItinerary>; 2596249259Sdim 2597249259Sdim def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2598249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2599249259Sdim [],NoItinerary>; 2600249259Sdim 2601249259Sdim def _word: A64I_SRexs_impl<0b10, opcode, asmstr, 2602249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2603249259Sdim [], NoItinerary>; 2604249259Sdim 2605249259Sdim def _dword: A64I_SRexs_impl<0b11, opcode, asmstr, 2606249259Sdim (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2607249259Sdim [], NoItinerary>; 2608249259Sdim} 2609249259Sdim 2610249259Sdimdefm STXR : A64I_SRex<"stxr", 0b000, "STXR">; 2611249259Sdimdefm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">; 2612249259Sdim 2613249259Sdim//===---------------------------------- 2614249259Sdim// Loads 2615249259Sdim//===---------------------------------- 2616249259Sdim 2617249259Sdimclass A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2618249259Sdim dag ins, list<dag> pat, 2619249259Sdim InstrItinClass itin> : 2620249259Sdim A64I_LDSTex_tn <size, 2621249259Sdim opcode{2}, 1, opcode{1}, opcode{0}, 2622249259Sdim outs, ins, 2623249259Sdim !strconcat(asm, "\t$Rt, [$Rn]"), 2624249259Sdim pat, itin> { 2625249259Sdim let mayLoad = 1; 2626249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2627249259Sdim} 2628249259Sdim 2629249259Sdimmulticlass A64I_LRex<string asmstr, bits<3> opcode> { 2630249259Sdim def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2631249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2632249259Sdim [], NoItinerary>; 2633249259Sdim 2634249259Sdim def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2635249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2636249259Sdim [], NoItinerary>; 2637249259Sdim 2638249259Sdim def _word: A64I_LRexs_impl<0b10, opcode, asmstr, 2639249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2640249259Sdim [], NoItinerary>; 2641249259Sdim 2642249259Sdim def _dword: A64I_LRexs_impl<0b11, opcode, asmstr, 2643249259Sdim (outs GPR64:$Rt), (ins GPR64xsp0:$Rn), 2644249259Sdim [], NoItinerary>; 2645249259Sdim} 2646249259Sdim 2647249259Sdimdefm LDXR : A64I_LRex<"ldxr", 0b000>; 2648249259Sdimdefm LDAXR : A64I_LRex<"ldaxr", 0b001>; 2649249259Sdimdefm LDAR : A64I_LRex<"ldar", 0b101>; 2650249259Sdim 2651249259Sdimclass acquiring_load<PatFrag base> 2652249259Sdim : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 2653251662Sdim AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2654251662Sdim return Ordering == Acquire || Ordering == SequentiallyConsistent; 2655249259Sdim}]>; 2656249259Sdim 2657249259Sdimdef atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 2658249259Sdimdef atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 2659249259Sdimdef atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 2660249259Sdimdef atomic_load_acquire_64 : acquiring_load<atomic_load_64>; 2661249259Sdim 2662249259Sdimdef : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>; 2663249259Sdimdef : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>; 2664249259Sdimdef : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>; 2665249259Sdimdef : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>; 2666249259Sdim 2667249259Sdim//===---------------------------------- 2668249259Sdim// Store-release (no exclusivity) 2669249259Sdim//===---------------------------------- 2670249259Sdim 2671249259Sdimclass A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2672249259Sdim dag ins, list<dag> pat, 2673249259Sdim InstrItinClass itin> : 2674249259Sdim A64I_LDSTex_tn <size, 2675249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2676249259Sdim outs, ins, 2677249259Sdim !strconcat(asm, "\t$Rt, [$Rn]"), 2678249259Sdim pat, itin> { 2679249259Sdim let mayStore = 1; 2680249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2681249259Sdim} 2682249259Sdim 2683249259Sdimclass releasing_store<PatFrag base> 2684249259Sdim : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 2685251662Sdim AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2686251662Sdim return Ordering == Release || Ordering == SequentiallyConsistent; 2687249259Sdim}]>; 2688249259Sdim 2689249259Sdimdef atomic_store_release_8 : releasing_store<atomic_store_8>; 2690249259Sdimdef atomic_store_release_16 : releasing_store<atomic_store_16>; 2691249259Sdimdef atomic_store_release_32 : releasing_store<atomic_store_32>; 2692249259Sdimdef atomic_store_release_64 : releasing_store<atomic_store_64>; 2693249259Sdim 2694249259Sdimmulticlass A64I_SLex<string asmstr, bits<3> opcode, string prefix> { 2695249259Sdim def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2696249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2697249259Sdim [(atomic_store_release_8 i64:$Rn, i32:$Rt)], 2698249259Sdim NoItinerary>; 2699249259Sdim 2700249259Sdim def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2701249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2702249259Sdim [(atomic_store_release_16 i64:$Rn, i32:$Rt)], 2703249259Sdim NoItinerary>; 2704249259Sdim 2705249259Sdim def _word: A64I_SLexs_impl<0b10, opcode, asmstr, 2706249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2707249259Sdim [(atomic_store_release_32 i64:$Rn, i32:$Rt)], 2708249259Sdim NoItinerary>; 2709249259Sdim 2710249259Sdim def _dword: A64I_SLexs_impl<0b11, opcode, asmstr, 2711249259Sdim (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2712249259Sdim [(atomic_store_release_64 i64:$Rn, i64:$Rt)], 2713249259Sdim NoItinerary>; 2714249259Sdim} 2715249259Sdim 2716249259Sdimdefm STLR : A64I_SLex<"stlr", 0b101, "STLR">; 2717249259Sdim 2718249259Sdim//===---------------------------------- 2719249259Sdim// Store-exclusive pair (releasing & normal) 2720249259Sdim//===---------------------------------- 2721249259Sdim 2722249259Sdimclass A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2723249259Sdim dag ins, list<dag> pat, 2724249259Sdim InstrItinClass itin> : 2725249259Sdim A64I_LDSTex_stt2n <size, 2726249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2727249259Sdim outs, ins, 2728249259Sdim !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"), 2729249259Sdim pat, itin> { 2730249259Sdim let mayStore = 1; 2731249259Sdim} 2732249259Sdim 2733249259Sdim 2734249259Sdimmulticlass A64I_SPex<string asmstr, bits<3> opcode> { 2735249259Sdim def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs), 2736249259Sdim (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2, 2737249259Sdim GPR64xsp0:$Rn), 2738249259Sdim [], NoItinerary>; 2739249259Sdim 2740249259Sdim def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs), 2741249259Sdim (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2, 2742249259Sdim GPR64xsp0:$Rn), 2743249259Sdim [], NoItinerary>; 2744249259Sdim} 2745249259Sdim 2746249259Sdimdefm STXP : A64I_SPex<"stxp", 0b010>; 2747249259Sdimdefm STLXP : A64I_SPex<"stlxp", 0b011>; 2748249259Sdim 2749249259Sdim//===---------------------------------- 2750249259Sdim// Load-exclusive pair (acquiring & normal) 2751249259Sdim//===---------------------------------- 2752249259Sdim 2753249259Sdimclass A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2754249259Sdim dag ins, list<dag> pat, 2755249259Sdim InstrItinClass itin> : 2756249259Sdim A64I_LDSTex_tt2n <size, 2757249259Sdim opcode{2}, 1, opcode{1}, opcode{0}, 2758249259Sdim outs, ins, 2759249259Sdim !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"), 2760249259Sdim pat, itin>{ 2761249259Sdim let mayLoad = 1; 2762249259Sdim let DecoderMethod = "DecodeLoadPairExclusiveInstruction"; 2763249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; 2764249259Sdim} 2765249259Sdim 2766249259Sdimmulticlass A64I_LPex<string asmstr, bits<3> opcode> { 2767249259Sdim def _word: A64I_LPexs_impl<0b10, opcode, asmstr, 2768249259Sdim (outs GPR32:$Rt, GPR32:$Rt2), 2769249259Sdim (ins GPR64xsp0:$Rn), 2770249259Sdim [], NoItinerary>; 2771249259Sdim 2772249259Sdim def _dword: A64I_LPexs_impl<0b11, opcode, asmstr, 2773249259Sdim (outs GPR64:$Rt, GPR64:$Rt2), 2774249259Sdim (ins GPR64xsp0:$Rn), 2775249259Sdim [], NoItinerary>; 2776249259Sdim} 2777249259Sdim 2778249259Sdimdefm LDXP : A64I_LPex<"ldxp", 0b010>; 2779249259Sdimdefm LDAXP : A64I_LPex<"ldaxp", 0b011>; 2780249259Sdim 2781249259Sdim//===----------------------------------------------------------------------===// 2782249259Sdim// Load-store register (unscaled immediate) instructions 2783249259Sdim//===----------------------------------------------------------------------===// 2784249259Sdim// Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM 2785249259Sdim// 2786249259Sdim// and 2787249259Sdim// 2788249259Sdim//===----------------------------------------------------------------------===// 2789249259Sdim// Load-store register (register offset) instructions 2790249259Sdim//===----------------------------------------------------------------------===// 2791249259Sdim// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2792249259Sdim// 2793249259Sdim// and 2794249259Sdim// 2795249259Sdim//===----------------------------------------------------------------------===// 2796249259Sdim// Load-store register (unsigned immediate) instructions 2797249259Sdim//===----------------------------------------------------------------------===// 2798249259Sdim// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2799249259Sdim// 2800249259Sdim// and 2801249259Sdim// 2802249259Sdim//===----------------------------------------------------------------------===// 2803249259Sdim// Load-store register (immediate post-indexed) instructions 2804249259Sdim//===----------------------------------------------------------------------===// 2805249259Sdim// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2806249259Sdim// 2807249259Sdim// and 2808249259Sdim// 2809249259Sdim//===----------------------------------------------------------------------===// 2810249259Sdim// Load-store register (immediate pre-indexed) instructions 2811249259Sdim//===----------------------------------------------------------------------===// 2812249259Sdim// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2813249259Sdim 2814249259Sdim// Note that patterns are much later on in a completely separate section (they 2815249259Sdim// need ADRPxi to be defined). 2816249259Sdim 2817249259Sdim//===------------------------------- 2818249259Sdim// 1. Various operands needed 2819249259Sdim//===------------------------------- 2820249259Sdim 2821249259Sdim//===------------------------------- 2822249259Sdim// 1.1 Unsigned 12-bit immediate operands 2823249259Sdim//===------------------------------- 2824249259Sdim// The addressing mode for these instructions consists of an unsigned 12-bit 2825249259Sdim// immediate which is scaled by the size of the memory access. 2826249259Sdim// 2827249259Sdim// We represent this in the MC layer by two operands: 2828249259Sdim// 1. A base register. 2829249259Sdim// 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]" 2830249259Sdim// would have '1' in this field. 2831249259Sdim// This means that separate functions are needed for converting representations 2832249259Sdim// which *are* aware of the intended access size. 2833249259Sdim 2834249259Sdim// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 2835249259Sdim// know the access size via some means. An isolated operand does not have this 2836249259Sdim// information unless told from here, which means we need separate tablegen 2837249259Sdim// Operands for each access size. This multiclass takes care of instantiating 2838249259Sdim// the correct template functions in the rest of the backend. 2839249259Sdim 2840249259Sdim//===------------------------------- 2841249259Sdim// 1.1 Unsigned 12-bit immediate operands 2842249259Sdim//===------------------------------- 2843249259Sdim 2844249259Sdimmulticlass offsets_uimm12<int MemSize, string prefix> { 2845249259Sdim def uimm12_asmoperand : AsmOperandClass { 2846249259Sdim let Name = "OffsetUImm12_" # MemSize; 2847249259Sdim let PredicateMethod = "isOffsetUImm12<" # MemSize # ">"; 2848249259Sdim let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">"; 2849249259Sdim let DiagnosticType = "LoadStoreUImm12_" # MemSize; 2850249259Sdim } 2851249259Sdim 2852249259Sdim // Pattern is really no more than an ImmLeaf, but predicated on MemSize which 2853249259Sdim // complicates things beyond TableGen's ken. 2854249259Sdim def uimm12 : Operand<i64>, 2855249259Sdim ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> { 2856249259Sdim let ParserMatchClass 2857249259Sdim = !cast<AsmOperandClass>(prefix # uimm12_asmoperand); 2858249259Sdim 2859249259Sdim let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">"; 2860249259Sdim let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">"; 2861249259Sdim } 2862249259Sdim} 2863249259Sdim 2864249259Sdimdefm byte_ : offsets_uimm12<1, "byte_">; 2865249259Sdimdefm hword_ : offsets_uimm12<2, "hword_">; 2866249259Sdimdefm word_ : offsets_uimm12<4, "word_">; 2867249259Sdimdefm dword_ : offsets_uimm12<8, "dword_">; 2868249259Sdimdefm qword_ : offsets_uimm12<16, "qword_">; 2869249259Sdim 2870249259Sdim//===------------------------------- 2871249259Sdim// 1.1 Signed 9-bit immediate operands 2872249259Sdim//===------------------------------- 2873249259Sdim 2874249259Sdim// The MCInst is expected to store the bit-wise encoding of the value, 2875249259Sdim// which amounts to lopping off the extended sign bits. 2876249259Sdimdef SDXF_simm9 : SDNodeXForm<imm, [{ 2877249259Sdim return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32); 2878249259Sdim}]>; 2879249259Sdim 2880249259Sdimdef simm9_asmoperand : AsmOperandClass { 2881249259Sdim let Name = "SImm9"; 2882249259Sdim let PredicateMethod = "isSImm<9>"; 2883249259Sdim let RenderMethod = "addSImmOperands<9>"; 2884249259Sdim let DiagnosticType = "LoadStoreSImm9"; 2885249259Sdim} 2886249259Sdim 2887249259Sdimdef simm9 : Operand<i64>, 2888249259Sdim ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }], 2889249259Sdim SDXF_simm9> { 2890249259Sdim let PrintMethod = "printOffsetSImm9Operand"; 2891249259Sdim let ParserMatchClass = simm9_asmoperand; 2892249259Sdim} 2893249259Sdim 2894249259Sdim 2895249259Sdim//===------------------------------- 2896249259Sdim// 1.3 Register offset extensions 2897249259Sdim//===------------------------------- 2898249259Sdim 2899249259Sdim// The assembly-syntax for these addressing-modes is: 2900249259Sdim// [<Xn|SP>, <R><m> {, <extend> {<amount>}}] 2901249259Sdim// 2902249259Sdim// The essential semantics are: 2903249259Sdim// + <amount> is a shift: #<log(transfer size)> or #0 2904249259Sdim// + <R> can be W or X. 2905249259Sdim// + If <R> is W, <extend> can be UXTW or SXTW 2906249259Sdim// + If <R> is X, <extend> can be LSL or SXTX 2907249259Sdim// 2908249259Sdim// The trickiest of those constraints is that Rm can be either GPR32 or GPR64, 2909249259Sdim// which will need separate instructions for LLVM type-consistency. We'll also 2910249259Sdim// need separate operands, of course. 2911249259Sdimmulticlass regexts<int MemSize, int RmSize, RegisterClass GPR, 2912249259Sdim string Rm, string prefix> { 2913249259Sdim def regext_asmoperand : AsmOperandClass { 2914249259Sdim let Name = "AddrRegExtend_" # MemSize # "_" # Rm; 2915249259Sdim let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">"; 2916249259Sdim let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">"; 2917249259Sdim let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize; 2918249259Sdim } 2919249259Sdim 2920249259Sdim def regext : Operand<i64> { 2921249259Sdim let PrintMethod 2922249259Sdim = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">"; 2923249259Sdim 2924249259Sdim let DecoderMethod = "DecodeAddrRegExtendOperand"; 2925249259Sdim let ParserMatchClass 2926249259Sdim = !cast<AsmOperandClass>(prefix # regext_asmoperand); 2927249259Sdim } 2928249259Sdim} 2929249259Sdim 2930249259Sdimmulticlass regexts_wx<int MemSize, string prefix> { 2931249259Sdim // Rm is an X-register if LSL or SXTX are specified as the shift. 2932249259Sdim defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">; 2933249259Sdim 2934249259Sdim // Rm is a W-register if UXTW or SXTW are specified as the shift. 2935249259Sdim defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">; 2936249259Sdim} 2937249259Sdim 2938249259Sdimdefm byte_ : regexts_wx<1, "byte_">; 2939249259Sdimdefm hword_ : regexts_wx<2, "hword_">; 2940249259Sdimdefm word_ : regexts_wx<4, "word_">; 2941249259Sdimdefm dword_ : regexts_wx<8, "dword_">; 2942249259Sdimdefm qword_ : regexts_wx<16, "qword_">; 2943249259Sdim 2944249259Sdim 2945249259Sdim//===------------------------------ 2946249259Sdim// 2. The instructions themselves. 2947249259Sdim//===------------------------------ 2948249259Sdim 2949249259Sdim// We have the following instructions to implement: 2950249259Sdim// | | B | H | W | X | 2951249259Sdim// |-----------------+-------+-------+-------+--------| 2952249259Sdim// | unsigned str | STRB | STRH | STR | STR | 2953249259Sdim// | unsigned ldr | LDRB | LDRH | LDR | LDR | 2954249259Sdim// | signed ldr to W | LDRSB | LDRSH | - | - | 2955249259Sdim// | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) | 2956249259Sdim 2957249259Sdim// This will instantiate the LDR/STR instructions you'd expect to use for an 2958249259Sdim// unsigned datatype (first two rows above) or floating-point register, which is 2959249259Sdim// reasonably uniform across all access sizes. 2960249259Sdim 2961249259Sdim 2962249259Sdim//===------------------------------ 2963249259Sdim// 2.1 Regular instructions 2964249259Sdim//===------------------------------ 2965249259Sdim 2966249259Sdim// This class covers the basic unsigned or irrelevantly-signed loads and stores, 2967249259Sdim// to general-purpose and floating-point registers. 2968249259Sdim 2969249259Sdimclass AddrParams<string prefix> { 2970249259Sdim Operand uimm12 = !cast<Operand>(prefix # "_uimm12"); 2971249259Sdim 2972249259Sdim Operand regextWm = !cast<Operand>(prefix # "_Wm_regext"); 2973249259Sdim Operand regextXm = !cast<Operand>(prefix # "_Xm_regext"); 2974249259Sdim} 2975249259Sdim 2976249259Sdimdef byte_addrparams : AddrParams<"byte">; 2977249259Sdimdef hword_addrparams : AddrParams<"hword">; 2978249259Sdimdef word_addrparams : AddrParams<"word">; 2979249259Sdimdef dword_addrparams : AddrParams<"dword">; 2980249259Sdimdef qword_addrparams : AddrParams<"qword">; 2981249259Sdim 2982249259Sdimmulticlass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v, 2983249259Sdim bit high_opc, string asmsuffix, 2984249259Sdim RegisterClass GPR, AddrParams params> { 2985249259Sdim // Unsigned immediate 2986249259Sdim def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0}, 2987249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12), 2988249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2989249259Sdim [], NoItinerary> { 2990249259Sdim let mayStore = 1; 2991249259Sdim } 2992249259Sdim def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]", 2993249259Sdim (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2994249259Sdim 2995249259Sdim def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1}, 2996249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 2997249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2998249259Sdim [], NoItinerary> { 2999249259Sdim let mayLoad = 1; 3000249259Sdim } 3001249259Sdim def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]", 3002249259Sdim (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3003249259Sdim 3004249259Sdim // Register offset (four of these: load/store and Wm/Xm). 3005249259Sdim let mayLoad = 1 in { 3006249259Sdim def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0, 3007249259Sdim (outs GPR:$Rt), 3008249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3009249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3010249259Sdim [], NoItinerary>; 3011249259Sdim 3012249259Sdim def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1, 3013249259Sdim (outs GPR:$Rt), 3014249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3015249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3016249259Sdim [], NoItinerary>; 3017249259Sdim } 3018249259Sdim def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]", 3019249259Sdim (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn, 3020249259Sdim GPR64:$Rm, 2)>; 3021249259Sdim 3022249259Sdim let mayStore = 1 in { 3023249259Sdim def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0, 3024249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm, 3025249259Sdim params.regextWm:$Ext), 3026249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3027249259Sdim [], NoItinerary>; 3028249259Sdim 3029249259Sdim def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1, 3030249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 3031249259Sdim params.regextXm:$Ext), 3032249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 3033249259Sdim [], NoItinerary>; 3034249259Sdim } 3035249259Sdim def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]", 3036249259Sdim (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn, 3037249259Sdim GPR64:$Rm, 2)>; 3038249259Sdim 3039249259Sdim // Unaligned immediate 3040249259Sdim def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0}, 3041249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3042249259Sdim "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3043249259Sdim [], NoItinerary> { 3044249259Sdim let mayStore = 1; 3045249259Sdim } 3046249259Sdim def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]", 3047249259Sdim (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3048249259Sdim 3049249259Sdim def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1}, 3050249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3051249259Sdim "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3052249259Sdim [], NoItinerary> { 3053249259Sdim let mayLoad = 1; 3054249259Sdim } 3055249259Sdim def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]", 3056249259Sdim (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3057249259Sdim 3058249259Sdim // Post-indexed 3059249259Sdim def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0}, 3060249259Sdim (outs GPR64xsp:$Rn_wb), 3061249259Sdim (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3062249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3063249259Sdim [], NoItinerary> { 3064249259Sdim let Constraints = "$Rn = $Rn_wb"; 3065249259Sdim let mayStore = 1; 3066249259Sdim 3067249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3068249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3069249259Sdim } 3070249259Sdim 3071249259Sdim def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1}, 3072249259Sdim (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3073249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3074249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3075249259Sdim [], NoItinerary> { 3076249259Sdim let mayLoad = 1; 3077249259Sdim let Constraints = "$Rn = $Rn_wb"; 3078249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3079249259Sdim } 3080249259Sdim 3081249259Sdim // Pre-indexed 3082249259Sdim def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0}, 3083249259Sdim (outs GPR64xsp:$Rn_wb), 3084249259Sdim (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3085249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3086249259Sdim [], NoItinerary> { 3087249259Sdim let Constraints = "$Rn = $Rn_wb"; 3088249259Sdim let mayStore = 1; 3089249259Sdim 3090249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3091249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3092249259Sdim } 3093249259Sdim 3094249259Sdim def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1}, 3095249259Sdim (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3096249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3097249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3098249259Sdim [], NoItinerary> { 3099249259Sdim let mayLoad = 1; 3100249259Sdim let Constraints = "$Rn = $Rn_wb"; 3101249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3102249259Sdim } 3103249259Sdim 3104249259Sdim} 3105249259Sdim 3106249259Sdim// STRB/LDRB: First define the instructions 3107249259Sdimdefm LS8 3108249259Sdim : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>; 3109249259Sdim 3110249259Sdim// STRH/LDRH 3111249259Sdimdefm LS16 3112249259Sdim : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>; 3113249259Sdim 3114249259Sdim 3115249259Sdim// STR/LDR to/from a W register 3116249259Sdimdefm LS32 3117249259Sdim : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>; 3118249259Sdim 3119249259Sdim// STR/LDR to/from an X register 3120249259Sdimdefm LS64 3121249259Sdim : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>; 3122249259Sdim 3123263508Sdimlet Predicates = [HasFPARMv8] in { 3124249259Sdim// STR/LDR to/from a B register 3125249259Sdimdefm LSFP8 3126249259Sdim : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>; 3127249259Sdim 3128249259Sdim// STR/LDR to/from an H register 3129249259Sdimdefm LSFP16 3130249259Sdim : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>; 3131249259Sdim 3132249259Sdim// STR/LDR to/from an S register 3133249259Sdimdefm LSFP32 3134249259Sdim : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>; 3135249259Sdim// STR/LDR to/from a D register 3136249259Sdimdefm LSFP64 3137249259Sdim : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>; 3138249259Sdim// STR/LDR to/from a Q register 3139249259Sdimdefm LSFP128 3140249259Sdim : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, 3141249259Sdim qword_addrparams>; 3142263508Sdim} 3143249259Sdim 3144249259Sdim//===------------------------------ 3145249259Sdim// 2.3 Signed loads 3146249259Sdim//===------------------------------ 3147249259Sdim 3148249259Sdim// Byte and half-word signed loads can both go into either an X or a W register, 3149249259Sdim// so it's worth factoring out. Signed word loads don't fit because there is no 3150249259Sdim// W version. 3151249259Sdimmulticlass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params, 3152249259Sdim string prefix> { 3153249259Sdim // Unsigned offset 3154249259Sdim def w : A64I_LSunsigimm<size, 0b0, 0b11, 3155249259Sdim (outs GPR32:$Rt), 3156249259Sdim (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3157249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3158249259Sdim [], NoItinerary> { 3159249259Sdim let mayLoad = 1; 3160249259Sdim } 3161249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3162249259Sdim (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3163249259Sdim 3164249259Sdim def x : A64I_LSunsigimm<size, 0b0, 0b10, 3165249259Sdim (outs GPR64:$Rt), 3166249259Sdim (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3167249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3168249259Sdim [], NoItinerary> { 3169249259Sdim let mayLoad = 1; 3170249259Sdim } 3171249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3172249259Sdim (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3173249259Sdim 3174249259Sdim // Register offset 3175249259Sdim let mayLoad = 1 in { 3176249259Sdim def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0, 3177249259Sdim (outs GPR32:$Rt), 3178249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3179249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3180249259Sdim [], NoItinerary>; 3181249259Sdim 3182249259Sdim def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1, 3183249259Sdim (outs GPR32:$Rt), 3184249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3185249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3186249259Sdim [], NoItinerary>; 3187249259Sdim 3188249259Sdim def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0, 3189249259Sdim (outs GPR64:$Rt), 3190249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3191249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3192249259Sdim [], NoItinerary>; 3193249259Sdim 3194249259Sdim def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1, 3195249259Sdim (outs GPR64:$Rt), 3196249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3197249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3198249259Sdim [], NoItinerary>; 3199249259Sdim } 3200249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3201249259Sdim (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn, 3202249259Sdim GPR64:$Rm, 2)>; 3203249259Sdim 3204249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3205249259Sdim (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn, 3206249259Sdim GPR64:$Rm, 2)>; 3207249259Sdim 3208249259Sdim 3209249259Sdim let mayLoad = 1 in { 3210249259Sdim // Unaligned offset 3211249259Sdim def w_U : A64I_LSunalimm<size, 0b0, 0b11, 3212249259Sdim (outs GPR32:$Rt), 3213249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3214249259Sdim "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3215249259Sdim [], NoItinerary>; 3216249259Sdim 3217249259Sdim def x_U : A64I_LSunalimm<size, 0b0, 0b10, 3218249259Sdim (outs GPR64:$Rt), 3219249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3220249259Sdim "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3221249259Sdim [], NoItinerary>; 3222249259Sdim 3223249259Sdim 3224249259Sdim // Post-indexed 3225249259Sdim def w_PostInd : A64I_LSpostind<size, 0b0, 0b11, 3226249259Sdim (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3227249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3228249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3229249259Sdim [], NoItinerary> { 3230249259Sdim let Constraints = "$Rn = $Rn_wb"; 3231249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3232249259Sdim } 3233249259Sdim 3234249259Sdim def x_PostInd : A64I_LSpostind<size, 0b0, 0b10, 3235249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3236249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3237249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3238249259Sdim [], NoItinerary> { 3239249259Sdim let Constraints = "$Rn = $Rn_wb"; 3240249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3241249259Sdim } 3242249259Sdim 3243249259Sdim // Pre-indexed 3244249259Sdim def w_PreInd : A64I_LSpreind<size, 0b0, 0b11, 3245249259Sdim (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3246249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3247249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3248249259Sdim [], NoItinerary> { 3249249259Sdim let Constraints = "$Rn = $Rn_wb"; 3250249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3251249259Sdim } 3252249259Sdim 3253249259Sdim def x_PreInd : A64I_LSpreind<size, 0b0, 0b10, 3254249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3255249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3256249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3257249259Sdim [], NoItinerary> { 3258249259Sdim let Constraints = "$Rn = $Rn_wb"; 3259249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3260249259Sdim } 3261249259Sdim } // let mayLoad = 1 3262249259Sdim} 3263249259Sdim 3264249259Sdim// LDRSB 3265249259Sdimdefm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">; 3266249259Sdim// LDRSH 3267249259Sdimdefm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">; 3268249259Sdim 3269249259Sdim// LDRSW: load a 32-bit register, sign-extending to 64-bits. 3270249259Sdimdef LDRSWx 3271249259Sdim : A64I_LSunsigimm<0b10, 0b0, 0b10, 3272249259Sdim (outs GPR64:$Rt), 3273249259Sdim (ins GPR64xsp:$Rn, word_uimm12:$UImm12), 3274249259Sdim "ldrsw\t$Rt, [$Rn, $UImm12]", 3275249259Sdim [], NoItinerary> { 3276249259Sdim let mayLoad = 1; 3277249259Sdim} 3278249259Sdimdef : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3279249259Sdim 3280249259Sdimlet mayLoad = 1 in { 3281249259Sdim def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0, 3282249259Sdim (outs GPR64:$Rt), 3283249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext), 3284249259Sdim "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3285249259Sdim [], NoItinerary>; 3286249259Sdim 3287249259Sdim def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1, 3288249259Sdim (outs GPR64:$Rt), 3289249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext), 3290249259Sdim "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3291249259Sdim [], NoItinerary>; 3292249259Sdim} 3293249259Sdimdef : InstAlias<"ldrsw $Rt, [$Rn, $Rm]", 3294249259Sdim (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>; 3295249259Sdim 3296249259Sdim 3297249259Sdimdef LDURSWx 3298249259Sdim : A64I_LSunalimm<0b10, 0b0, 0b10, 3299249259Sdim (outs GPR64:$Rt), 3300249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3301249259Sdim "ldursw\t$Rt, [$Rn, $SImm9]", 3302249259Sdim [], NoItinerary> { 3303249259Sdim let mayLoad = 1; 3304249259Sdim} 3305249259Sdimdef : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3306249259Sdim 3307249259Sdimdef LDRSWx_PostInd 3308249259Sdim : A64I_LSpostind<0b10, 0b0, 0b10, 3309249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3310249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3311249259Sdim "ldrsw\t$Rt, [$Rn], $SImm9", 3312249259Sdim [], NoItinerary> { 3313249259Sdim let mayLoad = 1; 3314249259Sdim let Constraints = "$Rn = $Rn_wb"; 3315249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3316249259Sdim} 3317249259Sdim 3318249259Sdimdef LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10, 3319249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3320249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3321249259Sdim "ldrsw\t$Rt, [$Rn, $SImm9]!", 3322249259Sdim [], NoItinerary> { 3323249259Sdim let mayLoad = 1; 3324249259Sdim let Constraints = "$Rn = $Rn_wb"; 3325249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3326249259Sdim} 3327249259Sdim 3328249259Sdim//===------------------------------ 3329249259Sdim// 2.4 Prefetch operations 3330249259Sdim//===------------------------------ 3331249259Sdim 3332249259Sdimdef PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs), 3333249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12), 3334249259Sdim "prfm\t$Rt, [$Rn, $UImm12]", 3335249259Sdim [], NoItinerary> { 3336249259Sdim let mayLoad = 1; 3337249259Sdim} 3338249259Sdimdef : InstAlias<"prfm $Rt, [$Rn]", 3339249259Sdim (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3340249259Sdim 3341249259Sdimlet mayLoad = 1 in { 3342249259Sdim def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs), 3343249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3344249259Sdim GPR32:$Rm, dword_Wm_regext:$Ext), 3345249259Sdim "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3346249259Sdim [], NoItinerary>; 3347249259Sdim def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs), 3348249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3349249259Sdim GPR64:$Rm, dword_Xm_regext:$Ext), 3350249259Sdim "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3351249259Sdim [], NoItinerary>; 3352249259Sdim} 3353249259Sdim 3354249259Sdimdef : InstAlias<"prfm $Rt, [$Rn, $Rm]", 3355249259Sdim (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn, 3356249259Sdim GPR64:$Rm, 2)>; 3357249259Sdim 3358249259Sdim 3359249259Sdimdef PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs), 3360249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3361249259Sdim "prfum\t$Rt, [$Rn, $SImm9]", 3362249259Sdim [], NoItinerary> { 3363249259Sdim let mayLoad = 1; 3364249259Sdim} 3365249259Sdimdef : InstAlias<"prfum $Rt, [$Rn]", 3366249259Sdim (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3367249259Sdim 3368249259Sdim//===----------------------------------------------------------------------===// 3369249259Sdim// Load-store register (unprivileged) instructions 3370249259Sdim//===----------------------------------------------------------------------===// 3371249259Sdim// Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH 3372249259Sdim 3373249259Sdim// These instructions very much mirror the "unscaled immediate" loads, but since 3374249259Sdim// there are no floating-point variants we need to split them out into their own 3375249259Sdim// section to avoid instantiation of "ldtr d0, [sp]" etc. 3376249259Sdim 3377249259Sdimmulticlass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR, 3378249259Sdim string prefix> { 3379249259Sdim def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00, 3380249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3381249259Sdim "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3382249259Sdim [], NoItinerary> { 3383249259Sdim let mayStore = 1; 3384249259Sdim } 3385249259Sdim 3386249259Sdim def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]", 3387249259Sdim (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3388249259Sdim 3389249259Sdim def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01, 3390249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3391249259Sdim "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3392249259Sdim [], NoItinerary> { 3393249259Sdim let mayLoad = 1; 3394249259Sdim } 3395249259Sdim 3396249259Sdim def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]", 3397249259Sdim (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3398249259Sdim 3399249259Sdim} 3400249259Sdim 3401249259Sdim// STTRB/LDTRB: First define the instructions 3402249259Sdimdefm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">; 3403249259Sdim 3404249259Sdim// STTRH/LDTRH 3405249259Sdimdefm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">; 3406249259Sdim 3407249259Sdim// STTR/LDTR to/from a W register 3408249259Sdimdefm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">; 3409249259Sdim 3410249259Sdim// STTR/LDTR to/from an X register 3411249259Sdimdefm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">; 3412249259Sdim 3413249259Sdim// Now a class for the signed instructions that can go to either 32 or 64 3414249259Sdim// bits... 3415249259Sdimmulticlass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> { 3416249259Sdim let mayLoad = 1 in { 3417249259Sdim def w : A64I_LSunpriv<size, 0b0, 0b11, 3418249259Sdim (outs GPR32:$Rt), 3419249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3420249259Sdim "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3421249259Sdim [], NoItinerary>; 3422249259Sdim 3423249259Sdim def x : A64I_LSunpriv<size, 0b0, 0b10, 3424249259Sdim (outs GPR64:$Rt), 3425249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3426249259Sdim "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3427249259Sdim [], NoItinerary>; 3428249259Sdim } 3429249259Sdim 3430249259Sdim def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3431249259Sdim (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3432249259Sdim 3433249259Sdim def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3434249259Sdim (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3435249259Sdim 3436249259Sdim} 3437249259Sdim 3438249259Sdim// LDTRSB 3439249259Sdimdefm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">; 3440249259Sdim// LDTRSH 3441249259Sdimdefm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">; 3442249259Sdim 3443249259Sdim// And finally LDTRSW which only goes to 64 bits. 3444249259Sdimdef LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10, 3445249259Sdim (outs GPR64:$Rt), 3446249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3447249259Sdim "ldtrsw\t$Rt, [$Rn, $SImm9]", 3448249259Sdim [], NoItinerary> { 3449249259Sdim let mayLoad = 1; 3450249259Sdim} 3451249259Sdimdef : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3452249259Sdim 3453249259Sdim//===----------------------------------------------------------------------===// 3454249259Sdim// Load-store register pair (offset) instructions 3455249259Sdim//===----------------------------------------------------------------------===// 3456249259Sdim// 3457249259Sdim// and 3458249259Sdim// 3459249259Sdim//===----------------------------------------------------------------------===// 3460249259Sdim// Load-store register pair (post-indexed) instructions 3461249259Sdim//===----------------------------------------------------------------------===// 3462249259Sdim// Contains: STP, LDP, LDPSW 3463249259Sdim// 3464249259Sdim// and 3465249259Sdim// 3466249259Sdim//===----------------------------------------------------------------------===// 3467249259Sdim// Load-store register pair (pre-indexed) instructions 3468249259Sdim//===----------------------------------------------------------------------===// 3469249259Sdim// Contains: STP, LDP, LDPSW 3470249259Sdim// 3471249259Sdim// and 3472249259Sdim// 3473249259Sdim//===----------------------------------------------------------------------===// 3474249259Sdim// Load-store non-temporal register pair (offset) instructions 3475249259Sdim//===----------------------------------------------------------------------===// 3476249259Sdim// Contains: STNP, LDNP 3477249259Sdim 3478249259Sdim 3479249259Sdim// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 3480249259Sdim// know the access size via some means. An isolated operand does not have this 3481249259Sdim// information unless told from here, which means we need separate tablegen 3482249259Sdim// Operands for each access size. This multiclass takes care of instantiating 3483249259Sdim// the correct template functions in the rest of the backend. 3484249259Sdim 3485249259Sdimmulticlass offsets_simm7<string MemSize, string prefix> { 3486249259Sdim // The bare signed 7-bit immediate is used in post-indexed instructions, but 3487249259Sdim // because of the scaling performed a generic "simm7" operand isn't 3488249259Sdim // appropriate here either. 3489249259Sdim def simm7_asmoperand : AsmOperandClass { 3490249259Sdim let Name = "SImm7_Scaled" # MemSize; 3491249259Sdim let PredicateMethod = "isSImm7Scaled<" # MemSize # ">"; 3492249259Sdim let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">"; 3493249259Sdim let DiagnosticType = "LoadStoreSImm7_" # MemSize; 3494249259Sdim } 3495249259Sdim 3496249259Sdim def simm7 : Operand<i64> { 3497249259Sdim let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">"; 3498249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand"); 3499249259Sdim } 3500249259Sdim} 3501249259Sdim 3502249259Sdimdefm word_ : offsets_simm7<"4", "word_">; 3503249259Sdimdefm dword_ : offsets_simm7<"8", "dword_">; 3504249259Sdimdefm qword_ : offsets_simm7<"16", "qword_">; 3505249259Sdim 3506249259Sdimmulticlass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg, 3507249259Sdim Operand simm7, string prefix> { 3508249259Sdim def _STR : A64I_LSPoffset<opc, v, 0b0, (outs), 3509249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3510249259Sdim "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3511249259Sdim let mayStore = 1; 3512249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3513249259Sdim } 3514249259Sdim def : InstAlias<"stp $Rt, $Rt2, [$Rn]", 3515249259Sdim (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt, 3516249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3517249259Sdim 3518249259Sdim def _LDR : A64I_LSPoffset<opc, v, 0b1, 3519249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2), 3520249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3521249259Sdim "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3522249259Sdim let mayLoad = 1; 3523249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3524249259Sdim } 3525249259Sdim def : InstAlias<"ldp $Rt, $Rt2, [$Rn]", 3526249259Sdim (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt, 3527249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3528249259Sdim 3529249259Sdim def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0, 3530249259Sdim (outs GPR64xsp:$Rn_wb), 3531249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, 3532249259Sdim GPR64xsp:$Rn, 3533249259Sdim simm7:$SImm7), 3534249259Sdim "stp\t$Rt, $Rt2, [$Rn], $SImm7", 3535249259Sdim [], NoItinerary> { 3536249259Sdim let mayStore = 1; 3537249259Sdim let Constraints = "$Rn = $Rn_wb"; 3538249259Sdim 3539249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3540249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3541249259Sdim } 3542249259Sdim 3543249259Sdim def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1, 3544249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3545249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3546249259Sdim "ldp\t$Rt, $Rt2, [$Rn], $SImm7", 3547249259Sdim [], NoItinerary> { 3548249259Sdim let mayLoad = 1; 3549249259Sdim let Constraints = "$Rn = $Rn_wb"; 3550249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3551249259Sdim } 3552249259Sdim 3553249259Sdim def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb), 3554249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3555249259Sdim "stp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3556249259Sdim [], NoItinerary> { 3557249259Sdim let mayStore = 1; 3558249259Sdim let Constraints = "$Rn = $Rn_wb"; 3559249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3560249259Sdim } 3561249259Sdim 3562249259Sdim def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1, 3563249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3564249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3565249259Sdim "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3566249259Sdim [], NoItinerary> { 3567249259Sdim let mayLoad = 1; 3568249259Sdim let Constraints = "$Rn = $Rn_wb"; 3569249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3570249259Sdim } 3571249259Sdim 3572249259Sdim def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs), 3573249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3574249259Sdim "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3575249259Sdim let mayStore = 1; 3576249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3577249259Sdim } 3578249259Sdim def : InstAlias<"stnp $Rt, $Rt2, [$Rn]", 3579249259Sdim (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt, 3580249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3581249259Sdim 3582249259Sdim def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1, 3583249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2), 3584249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3585249259Sdim "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3586249259Sdim let mayLoad = 1; 3587249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3588249259Sdim } 3589249259Sdim def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]", 3590249259Sdim (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt, 3591249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3592249259Sdim 3593249259Sdim} 3594249259Sdim 3595249259Sdim 3596249259Sdimdefm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">; 3597249259Sdimdefm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">; 3598263508Sdim 3599263508Sdimlet Predicates = [HasFPARMv8] in { 3600249259Sdimdefm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">; 3601249259Sdimdefm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">; 3602249259Sdimdefm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, 3603249259Sdim "LSFPPair128">; 3604263508Sdim} 3605249259Sdim 3606249259Sdim 3607249259Sdimdef LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1, 3608249259Sdim (outs GPR64:$Rt, GPR64:$Rt2), 3609249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3610249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3611249259Sdim let mayLoad = 1; 3612249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3613249259Sdim} 3614249259Sdimdef : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]", 3615249259Sdim (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>; 3616249259Sdim 3617249259Sdimdef LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1, 3618249259Sdim (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3619249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3620249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7", 3621249259Sdim [], NoItinerary> { 3622249259Sdim let mayLoad = 1; 3623249259Sdim let Constraints = "$Rn = $Rn_wb"; 3624249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3625249259Sdim} 3626249259Sdim 3627249259Sdimdef LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1, 3628249259Sdim (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3629249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3630249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!", 3631249259Sdim [], NoItinerary> { 3632249259Sdim let mayLoad = 1; 3633249259Sdim let Constraints = "$Rn = $Rn_wb"; 3634249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3635249259Sdim} 3636249259Sdim 3637249259Sdim//===----------------------------------------------------------------------===// 3638249259Sdim// Logical (immediate) instructions 3639249259Sdim//===----------------------------------------------------------------------===// 3640249259Sdim// Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV 3641249259Sdim 3642249259Sdimmulticlass logical_imm_operands<string prefix, string note, 3643249259Sdim int size, ValueType VT> { 3644249259Sdim def _asmoperand : AsmOperandClass { 3645249259Sdim let Name = "LogicalImm" # note # size; 3646249259Sdim let PredicateMethod = "isLogicalImm" # note # "<" # size # ">"; 3647249259Sdim let RenderMethod = "addLogicalImmOperands<" # size # ">"; 3648249259Sdim let DiagnosticType = "LogicalSecondSource"; 3649249259Sdim } 3650249259Sdim 3651249259Sdim def _operand 3652249259Sdim : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> { 3653249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3654249259Sdim let PrintMethod = "printLogicalImmOperand<" # size # ">"; 3655249259Sdim let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">"; 3656249259Sdim } 3657249259Sdim} 3658249259Sdim 3659249259Sdimdefm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>; 3660249259Sdimdefm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>; 3661249259Sdim 3662249259Sdim// The mov versions only differ in assembly parsing, where they 3663249259Sdim// exclude values representable with either MOVZ or MOVN. 3664249259Sdimdefm logical_imm32_mov 3665249259Sdim : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>; 3666249259Sdimdefm logical_imm64_mov 3667249259Sdim : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>; 3668249259Sdim 3669249259Sdim 3670249259Sdimmulticlass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> { 3671249259Sdim def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd), 3672249259Sdim (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3673249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3674249259Sdim [(set i32:$Rd, 3675249259Sdim (opnode i32:$Rn, logical_imm32_operand:$Imm))], 3676249259Sdim NoItinerary>; 3677249259Sdim 3678249259Sdim def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd), 3679249259Sdim (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3680249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3681249259Sdim [(set i64:$Rd, 3682249259Sdim (opnode i64:$Rn, logical_imm64_operand:$Imm))], 3683249259Sdim NoItinerary>; 3684249259Sdim} 3685249259Sdim 3686249259Sdimdefm AND : A64I_logimmSizes<0b00, "and", and>; 3687249259Sdimdefm ORR : A64I_logimmSizes<0b01, "orr", or>; 3688249259Sdimdefm EOR : A64I_logimmSizes<0b10, "eor", xor>; 3689249259Sdim 3690249259Sdimlet Defs = [NZCV] in { 3691249259Sdim def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd), 3692249259Sdim (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3693249259Sdim "ands\t$Rd, $Rn, $Imm", 3694249259Sdim [], NoItinerary>; 3695249259Sdim 3696249259Sdim def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd), 3697249259Sdim (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3698249259Sdim "ands\t$Rd, $Rn, $Imm", 3699249259Sdim [], NoItinerary>; 3700249259Sdim} 3701249259Sdim 3702249259Sdim 3703249259Sdimdef : InstAlias<"tst $Rn, $Imm", 3704249259Sdim (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>; 3705249259Sdimdef : InstAlias<"tst $Rn, $Imm", 3706249259Sdim (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>; 3707249259Sdimdef : InstAlias<"mov $Rd, $Imm", 3708249259Sdim (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>; 3709249259Sdimdef : InstAlias<"mov $Rd, $Imm", 3710249259Sdim (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>; 3711249259Sdim 3712249259Sdim//===----------------------------------------------------------------------===// 3713249259Sdim// Logical (shifted register) instructions 3714249259Sdim//===----------------------------------------------------------------------===// 3715249259Sdim// Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV 3716249259Sdim 3717249259Sdim// Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS" 3718249259Sdim// behaves differently for unsigned comparisons, so we defensively only allow 3719249259Sdim// signed or n/a as the operand. In practice "unsigned greater than 0" is "not 3720249259Sdim// equal to 0" and LLVM gives us this. 3721249259Sdimdef signed_cond : PatLeaf<(cond), [{ 3722249259Sdim return !isUnsignedIntSetCC(N->get()); 3723249259Sdim}]>; 3724249259Sdim 3725249259Sdim 3726249259Sdim// These instructions share their "shift" operands with add/sub (shifted 3727249259Sdim// register instructions). They are defined there. 3728249259Sdim 3729249259Sdim// N.b. the commutable parameter is just !N. It will be first against the wall 3730249259Sdim// when the revolution comes. 3731249259Sdimmulticlass logical_shifts<string prefix, bit sf, bits<2> opc, 3732249259Sdim bit N, bit commutable, 3733249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 3734249259Sdim RegisterClass GPR, list<Register> defs> { 3735249259Sdim let isCommutable = commutable, Defs = defs in { 3736249259Sdim def _lsl : A64I_logicalshift<sf, opc, 0b00, N, 3737249259Sdim (outs GPR:$Rd), 3738249259Sdim (ins GPR:$Rn, GPR:$Rm, 3739249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3740249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3741249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 3742249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 3743249259Sdim )], 3744249259Sdim NoItinerary>; 3745249259Sdim 3746249259Sdim def _lsr : A64I_logicalshift<sf, opc, 0b01, N, 3747249259Sdim (outs GPR:$Rd), 3748249259Sdim (ins GPR:$Rn, GPR:$Rm, 3749249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3750249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3751249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 3752249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 3753249259Sdim )], 3754249259Sdim NoItinerary>; 3755249259Sdim 3756249259Sdim def _asr : A64I_logicalshift<sf, opc, 0b10, N, 3757249259Sdim (outs GPR:$Rd), 3758249259Sdim (ins GPR:$Rn, GPR:$Rm, 3759249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3760249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3761249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 3762249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 3763249259Sdim )], 3764249259Sdim NoItinerary>; 3765249259Sdim 3766249259Sdim def _ror : A64I_logicalshift<sf, opc, 0b11, N, 3767249259Sdim (outs GPR:$Rd), 3768249259Sdim (ins GPR:$Rn, GPR:$Rm, 3769249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3770249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3771249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm, 3772249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6)) 3773249259Sdim )], 3774249259Sdim NoItinerary>; 3775249259Sdim } 3776249259Sdim 3777249259Sdim def _noshift 3778249259Sdim : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 3779249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 3780249259Sdim GPR:$Rm, 0)>; 3781249259Sdim 3782249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 3783249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3784249259Sdim} 3785249259Sdim 3786249259Sdimmulticlass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable, 3787249259Sdim string asmop, SDPatternOperator opfrag, 3788249259Sdim list<Register> defs> { 3789249259Sdim defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N, 3790249259Sdim commutable, asmop, opfrag, i64, GPR64, defs>; 3791249259Sdim defm www : logical_shifts<prefix # "www", 0b0, opc, N, 3792249259Sdim commutable, asmop, opfrag, i32, GPR32, defs>; 3793249259Sdim} 3794249259Sdim 3795249259Sdim 3796249259Sdimdefm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>; 3797249259Sdimdefm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>; 3798249259Sdimdefm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>; 3799249259Sdimdefm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands", 3800249259Sdim PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), 3801249259Sdim [{ (void)N; return false; }]>, 3802249259Sdim [NZCV]>; 3803249259Sdim 3804249259Sdimdefm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic", 3805249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3806249259Sdim (and node:$lhs, (not node:$rhs))>, []>; 3807249259Sdimdefm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn", 3808249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3809249259Sdim (or node:$lhs, (not node:$rhs))>, []>; 3810249259Sdimdefm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon", 3811249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3812249259Sdim (xor node:$lhs, (not node:$rhs))>, []>; 3813249259Sdimdefm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics", 3814249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3815249259Sdim (and node:$lhs, (not node:$rhs)), 3816249259Sdim [{ (void)N; return false; }]>, 3817249259Sdim [NZCV]>; 3818249259Sdim 3819249259Sdimmulticlass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3820249259Sdim let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in { 3821249259Sdim def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0, 3822249259Sdim (outs), 3823249259Sdim (ins GPR:$Rn, GPR:$Rm, 3824249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3825249259Sdim "tst\t$Rn, $Rm, $Imm6", 3826249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm, 3827249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)), 3828249259Sdim 0, signed_cond))], 3829249259Sdim NoItinerary>; 3830249259Sdim 3831249259Sdim 3832249259Sdim def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0, 3833249259Sdim (outs), 3834249259Sdim (ins GPR:$Rn, GPR:$Rm, 3835249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3836249259Sdim "tst\t$Rn, $Rm, $Imm6", 3837249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm, 3838249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)), 3839249259Sdim 0, signed_cond))], 3840249259Sdim NoItinerary>; 3841249259Sdim 3842249259Sdim def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0, 3843249259Sdim (outs), 3844249259Sdim (ins GPR:$Rn, GPR:$Rm, 3845249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3846249259Sdim "tst\t$Rn, $Rm, $Imm6", 3847249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm, 3848249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)), 3849249259Sdim 0, signed_cond))], 3850249259Sdim NoItinerary>; 3851249259Sdim 3852249259Sdim def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0, 3853249259Sdim (outs), 3854249259Sdim (ins GPR:$Rn, GPR:$Rm, 3855249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3856249259Sdim "tst\t$Rn, $Rm, $Imm6", 3857249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm, 3858249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6)), 3859249259Sdim 0, signed_cond))], 3860249259Sdim NoItinerary>; 3861249259Sdim } 3862249259Sdim 3863249259Sdim def _noshift : InstAlias<"tst $Rn, $Rm", 3864249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3865249259Sdim 3866249259Sdim def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond), 3867249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3868249259Sdim} 3869249259Sdim 3870249259Sdimdefm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>; 3871249259Sdimdefm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>; 3872249259Sdim 3873249259Sdim 3874249259Sdimmulticlass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3875249259Sdim let isCommutable = 0, Rn = 0b11111 in { 3876249259Sdim def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1, 3877249259Sdim (outs GPR:$Rd), 3878249259Sdim (ins GPR:$Rm, 3879249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3880249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3881249259Sdim [(set ty:$Rd, (not (shl ty:$Rm, 3882249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3883249259Sdim NoItinerary>; 3884249259Sdim 3885249259Sdim 3886249259Sdim def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1, 3887249259Sdim (outs GPR:$Rd), 3888249259Sdim (ins GPR:$Rm, 3889249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3890249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3891249259Sdim [(set ty:$Rd, (not (srl ty:$Rm, 3892249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)))], 3893249259Sdim NoItinerary>; 3894249259Sdim 3895249259Sdim def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1, 3896249259Sdim (outs GPR:$Rd), 3897249259Sdim (ins GPR:$Rm, 3898249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3899249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3900249259Sdim [(set ty:$Rd, (not (sra ty:$Rm, 3901249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)))], 3902249259Sdim NoItinerary>; 3903249259Sdim 3904249259Sdim def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1, 3905249259Sdim (outs GPR:$Rd), 3906249259Sdim (ins GPR:$Rm, 3907249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3908249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3909249259Sdim [(set ty:$Rd, (not (rotr ty:$Rm, 3910249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3911249259Sdim NoItinerary>; 3912249259Sdim } 3913249259Sdim 3914249259Sdim def _noshift : InstAlias<"mvn $Rn, $Rm", 3915249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3916249259Sdim 3917249259Sdim def : Pat<(not ty:$Rm), 3918249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>; 3919249259Sdim} 3920249259Sdim 3921249259Sdimdefm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>; 3922249259Sdimdefm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>; 3923249259Sdim 3924249259Sdimdef MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 3925249259Sdimdef MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 3926249259Sdim 3927249259Sdim//===----------------------------------------------------------------------===// 3928249259Sdim// Move wide (immediate) instructions 3929249259Sdim//===----------------------------------------------------------------------===// 3930249259Sdim// Contains: MOVN, MOVZ, MOVK + MOV aliases 3931249259Sdim 3932249259Sdim// A wide variety of different relocations are needed for variants of these 3933249259Sdim// instructions, so it turns out that we need a different operand for all of 3934249259Sdim// them. 3935249259Sdimmulticlass movw_operands<string prefix, string instname, int width> { 3936249259Sdim def _imm_asmoperand : AsmOperandClass { 3937249259Sdim let Name = instname # width # "Shifted" # shift; 3938249259Sdim let PredicateMethod = "is" # instname # width # "Imm"; 3939249259Sdim let RenderMethod = "addMoveWideImmOperands"; 3940249259Sdim let ParserMethod = "ParseImmWithLSLOperand"; 3941249259Sdim let DiagnosticType = "MOVWUImm16"; 3942249259Sdim } 3943249259Sdim 3944251662Sdim def _imm : Operand<i64> { 3945249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand"); 3946249259Sdim let PrintMethod = "printMoveWideImmOperand"; 3947249259Sdim let EncoderMethod = "getMoveWideImmOpValue"; 3948249259Sdim let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">"; 3949249259Sdim 3950249259Sdim let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3951249259Sdim } 3952249259Sdim} 3953249259Sdim 3954249259Sdimdefm movn32 : movw_operands<"movn32", "MOVN", 32>; 3955249259Sdimdefm movn64 : movw_operands<"movn64", "MOVN", 64>; 3956249259Sdimdefm movz32 : movw_operands<"movz32", "MOVZ", 32>; 3957249259Sdimdefm movz64 : movw_operands<"movz64", "MOVZ", 64>; 3958249259Sdimdefm movk32 : movw_operands<"movk32", "MOVK", 32>; 3959249259Sdimdefm movk64 : movw_operands<"movk64", "MOVK", 64>; 3960249259Sdim 3961249259Sdimmulticlass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, 3962249259Sdim dag ins64bit> { 3963249259Sdim 3964249259Sdim def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit, 3965249259Sdim !strconcat(asmop, "\t$Rd, $FullImm"), 3966249259Sdim [], NoItinerary> { 3967249259Sdim bits<18> FullImm; 3968249259Sdim let UImm16 = FullImm{15-0}; 3969249259Sdim let Shift = FullImm{17-16}; 3970249259Sdim } 3971249259Sdim 3972249259Sdim def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit, 3973249259Sdim !strconcat(asmop, "\t$Rd, $FullImm"), 3974249259Sdim [], NoItinerary> { 3975249259Sdim bits<18> FullImm; 3976249259Sdim let UImm16 = FullImm{15-0}; 3977249259Sdim let Shift = FullImm{17-16}; 3978249259Sdim } 3979249259Sdim} 3980249259Sdim 3981249259Sdimlet isMoveImm = 1, isReMaterializable = 1, 3982249259Sdim isAsCheapAsAMove = 1, hasSideEffects = 0 in { 3983249259Sdim defm MOVN : A64I_movwSizes<0b00, "movn", 3984249259Sdim (ins movn32_imm:$FullImm), 3985249259Sdim (ins movn64_imm:$FullImm)>; 3986249259Sdim 3987249259Sdim // Some relocations are able to convert between a MOVZ and a MOVN. If these 3988249259Sdim // are applied the instruction must be emitted with the corresponding bits as 3989249259Sdim // 0, which means a MOVZ needs to override that bit from the default. 3990249259Sdim let PostEncoderMethod = "fixMOVZ" in 3991249259Sdim defm MOVZ : A64I_movwSizes<0b10, "movz", 3992249259Sdim (ins movz32_imm:$FullImm), 3993249259Sdim (ins movz64_imm:$FullImm)>; 3994249259Sdim} 3995249259Sdim 3996249259Sdimlet Constraints = "$src = $Rd" in 3997249259Sdimdefm MOVK : A64I_movwSizes<0b11, "movk", 3998249259Sdim (ins GPR32:$src, movk32_imm:$FullImm), 3999249259Sdim (ins GPR64:$src, movk64_imm:$FullImm)>; 4000249259Sdim 4001249259Sdim 4002249259Sdim// And now the "MOV" aliases. These also need their own operands because what 4003249259Sdim// they accept is completely different to what the base instructions accept. 4004249259Sdimmulticlass movalias_operand<string prefix, string basename, 4005249259Sdim string immpredicate, int width> { 4006249259Sdim def _asmoperand : AsmOperandClass { 4007249259Sdim let Name = basename # width # "MovAlias"; 4008249259Sdim let PredicateMethod 4009249259Sdim = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">"; 4010249259Sdim let RenderMethod 4011249259Sdim = "addMoveWideMovAliasOperands<" # width # ", " 4012249259Sdim # "A64Imms::" # immpredicate # ">"; 4013249259Sdim } 4014249259Sdim 4015251662Sdim def _movimm : Operand<i64> { 4016249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 4017249259Sdim 4018249259Sdim let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 4019249259Sdim } 4020249259Sdim} 4021249259Sdim 4022249259Sdimdefm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>; 4023249259Sdimdefm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>; 4024249259Sdimdefm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>; 4025249259Sdimdefm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>; 4026249259Sdim 4027249259Sdim// FIXME: these are officially canonical aliases, but TableGen is too limited to 4028249259Sdim// print them at the moment. I believe in this case an "AliasPredicate" method 4029249259Sdim// will need to be implemented. to allow it, as well as the more generally 4030249259Sdim// useful handling of non-register, non-constant operands. 4031249259Sdimclass movalias<Instruction INST, RegisterClass GPR, Operand operand> 4032249259Sdim : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>; 4033249259Sdim 4034249259Sdimdef : movalias<MOVZwii, GPR32, movz32_movimm>; 4035249259Sdimdef : movalias<MOVZxii, GPR64, movz64_movimm>; 4036249259Sdimdef : movalias<MOVNwii, GPR32, movn32_movimm>; 4037249259Sdimdef : movalias<MOVNxii, GPR64, movn64_movimm>; 4038249259Sdim 4039263508Sdimdef movw_addressref_g0 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<0>">; 4040263508Sdimdef movw_addressref_g1 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<1>">; 4041263508Sdimdef movw_addressref_g2 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<2>">; 4042263508Sdimdef movw_addressref_g3 : ComplexPattern<i64, 2, "SelectMOVWAddressRef<3>">; 4043251662Sdim 4044263508Sdimdef : Pat<(A64WrapperLarge movw_addressref_g3:$G3, movw_addressref_g2:$G2, 4045263508Sdim movw_addressref_g1:$G1, movw_addressref_g0:$G0), 4046263508Sdim (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref_g3:$G3), 4047263508Sdim movw_addressref_g2:$G2), 4048263508Sdim movw_addressref_g1:$G1), 4049263508Sdim movw_addressref_g0:$G0)>; 4050251662Sdim 4051249259Sdim//===----------------------------------------------------------------------===// 4052249259Sdim// PC-relative addressing instructions 4053249259Sdim//===----------------------------------------------------------------------===// 4054249259Sdim// Contains: ADR, ADRP 4055249259Sdim 4056249259Sdimdef adr_label : Operand<i64> { 4057249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>"; 4058249259Sdim 4059249259Sdim // This label is a 21-bit offset from PC, unscaled 4060249259Sdim let PrintMethod = "printLabelOperand<21, 1>"; 4061249259Sdim let ParserMatchClass = label_asmoperand<21, 1>; 4062249259Sdim let OperandType = "OPERAND_PCREL"; 4063249259Sdim} 4064249259Sdim 4065249259Sdimdef adrp_label_asmoperand : AsmOperandClass { 4066249259Sdim let Name = "AdrpLabel"; 4067249259Sdim let RenderMethod = "addLabelOperands<21, 4096>"; 4068249259Sdim let DiagnosticType = "Label"; 4069249259Sdim} 4070249259Sdim 4071249259Sdimdef adrp_label : Operand<i64> { 4072249259Sdim let EncoderMethod = "getAdrpLabelOpValue"; 4073249259Sdim 4074249259Sdim // This label is a 21-bit offset from PC, scaled by the page-size: 4096. 4075249259Sdim let PrintMethod = "printLabelOperand<21, 4096>"; 4076249259Sdim let ParserMatchClass = adrp_label_asmoperand; 4077249259Sdim let OperandType = "OPERAND_PCREL"; 4078249259Sdim} 4079249259Sdim 4080249259Sdimlet hasSideEffects = 0 in { 4081249259Sdim def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label), 4082249259Sdim "adr\t$Rd, $Label", [], NoItinerary>; 4083249259Sdim 4084249259Sdim def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label), 4085249259Sdim "adrp\t$Rd, $Label", [], NoItinerary>; 4086249259Sdim} 4087249259Sdim 4088249259Sdim//===----------------------------------------------------------------------===// 4089249259Sdim// System instructions 4090249259Sdim//===----------------------------------------------------------------------===// 4091249259Sdim// Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS 4092249259Sdim// + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL 4093249259Sdim 4094249259Sdim// Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values. 4095249259Sdimdef uimm3_asmoperand : AsmOperandClass { 4096249259Sdim let Name = "UImm3"; 4097249259Sdim let PredicateMethod = "isUImm<3>"; 4098249259Sdim let RenderMethod = "addImmOperands"; 4099249259Sdim let DiagnosticType = "UImm3"; 4100249259Sdim} 4101249259Sdim 4102249259Sdimdef uimm3 : Operand<i32> { 4103249259Sdim let ParserMatchClass = uimm3_asmoperand; 4104249259Sdim} 4105249259Sdim 4106249259Sdim// The HINT alias can accept a simple unsigned 7-bit immediate. 4107249259Sdimdef uimm7_asmoperand : AsmOperandClass { 4108249259Sdim let Name = "UImm7"; 4109249259Sdim let PredicateMethod = "isUImm<7>"; 4110249259Sdim let RenderMethod = "addImmOperands"; 4111249259Sdim let DiagnosticType = "UImm7"; 4112249259Sdim} 4113249259Sdim 4114249259Sdimdef uimm7 : Operand<i32> { 4115249259Sdim let ParserMatchClass = uimm7_asmoperand; 4116249259Sdim} 4117249259Sdim 4118249259Sdim// Multiclass namedimm is defined with the prefetch operands. Most of these fit 4119249259Sdim// into the NamedImmMapper scheme well: they either accept a named operand or 4120249259Sdim// any immediate under a particular value (which may be 0, implying no immediate 4121249259Sdim// is allowed). 4122249259Sdimdefm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">; 4123249259Sdimdefm isb : namedimm<"isb", "A64ISB::ISBMapper">; 4124249259Sdimdefm ic : namedimm<"ic", "A64IC::ICMapper">; 4125249259Sdimdefm dc : namedimm<"dc", "A64DC::DCMapper">; 4126249259Sdimdefm at : namedimm<"at", "A64AT::ATMapper">; 4127249259Sdimdefm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">; 4128249259Sdim 4129249259Sdim// However, MRS and MSR are more complicated for a few reasons: 4130249259Sdim// * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an 4131249259Sdim// implementation-defined effect 4132249259Sdim// * Most registers are shared, but some are read-only or write-only. 4133249259Sdim// * There is a variant of MSR which accepts the same register name (SPSel), 4134249259Sdim// but which would have a different encoding. 4135249259Sdim 4136249259Sdim// In principle these could be resolved in with more complicated subclasses of 4137249259Sdim// NamedImmMapper, however that imposes an overhead on other "named 4138249259Sdim// immediates". Both in concrete terms with virtual tables and in unnecessary 4139249259Sdim// abstraction. 4140249259Sdim 4141249259Sdim// The solution adopted here is to take the MRS/MSR Mappers out of the usual 4142249259Sdim// hierarchy (they're not derived from NamedImmMapper) and to add logic for 4143249259Sdim// their special situation. 4144249259Sdimdef mrs_asmoperand : AsmOperandClass { 4145249259Sdim let Name = "MRS"; 4146249259Sdim let ParserMethod = "ParseSysRegOperand"; 4147249259Sdim let DiagnosticType = "MRS"; 4148249259Sdim} 4149249259Sdim 4150249259Sdimdef mrs_op : Operand<i32> { 4151249259Sdim let ParserMatchClass = mrs_asmoperand; 4152249259Sdim let PrintMethod = "printMRSOperand"; 4153249259Sdim let DecoderMethod = "DecodeMRSOperand"; 4154249259Sdim} 4155249259Sdim 4156249259Sdimdef msr_asmoperand : AsmOperandClass { 4157249259Sdim let Name = "MSRWithReg"; 4158249259Sdim 4159249259Sdim // Note that SPSel is valid for both this and the pstate operands, but with 4160249259Sdim // different immediate encodings. This is why these operands provide a string 4161249259Sdim // AArch64Operand rather than an immediate. The overlap is small enough that 4162249259Sdim // it could be resolved with hackery now, but who can say in future? 4163249259Sdim let ParserMethod = "ParseSysRegOperand"; 4164249259Sdim let DiagnosticType = "MSR"; 4165249259Sdim} 4166249259Sdim 4167249259Sdimdef msr_op : Operand<i32> { 4168249259Sdim let ParserMatchClass = msr_asmoperand; 4169249259Sdim let PrintMethod = "printMSROperand"; 4170249259Sdim let DecoderMethod = "DecodeMSROperand"; 4171249259Sdim} 4172249259Sdim 4173249259Sdimdef pstate_asmoperand : AsmOperandClass { 4174249259Sdim let Name = "MSRPState"; 4175249259Sdim // See comment above about parser. 4176249259Sdim let ParserMethod = "ParseSysRegOperand"; 4177249259Sdim let DiagnosticType = "MSR"; 4178249259Sdim} 4179249259Sdim 4180249259Sdimdef pstate_op : Operand<i32> { 4181249259Sdim let ParserMatchClass = pstate_asmoperand; 4182249259Sdim let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>"; 4183249259Sdim let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>"; 4184249259Sdim} 4185249259Sdim 4186249259Sdim// When <CRn> is specified, an assembler should accept something like "C4", not 4187249259Sdim// the usual "#4" immediate. 4188249259Sdimdef CRx_asmoperand : AsmOperandClass { 4189249259Sdim let Name = "CRx"; 4190249259Sdim let PredicateMethod = "isUImm<4>"; 4191249259Sdim let RenderMethod = "addImmOperands"; 4192249259Sdim let ParserMethod = "ParseCRxOperand"; 4193249259Sdim // Diagnostics are handled in all cases by ParseCRxOperand. 4194249259Sdim} 4195249259Sdim 4196249259Sdimdef CRx : Operand<i32> { 4197249259Sdim let ParserMatchClass = CRx_asmoperand; 4198249259Sdim let PrintMethod = "printCRxOperand"; 4199249259Sdim} 4200249259Sdim 4201249259Sdim 4202249259Sdim// Finally, we can start defining the instructions. 4203249259Sdim 4204249259Sdim// HINT is straightforward, with a few aliases. 4205249259Sdimdef HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7", 4206249259Sdim [], NoItinerary> { 4207249259Sdim bits<7> UImm7; 4208249259Sdim let CRm = UImm7{6-3}; 4209249259Sdim let Op2 = UImm7{2-0}; 4210249259Sdim 4211249259Sdim let Op0 = 0b00; 4212249259Sdim let Op1 = 0b011; 4213249259Sdim let CRn = 0b0010; 4214249259Sdim let Rt = 0b11111; 4215249259Sdim} 4216249259Sdim 4217249259Sdimdef : InstAlias<"nop", (HINTi 0)>; 4218249259Sdimdef : InstAlias<"yield", (HINTi 1)>; 4219249259Sdimdef : InstAlias<"wfe", (HINTi 2)>; 4220249259Sdimdef : InstAlias<"wfi", (HINTi 3)>; 4221249259Sdimdef : InstAlias<"sev", (HINTi 4)>; 4222249259Sdimdef : InstAlias<"sevl", (HINTi 5)>; 4223249259Sdim 4224249259Sdim// Quite a few instructions then follow a similar pattern of fixing common 4225249259Sdim// fields in the bitpattern, we'll define a helper-class for them. 4226249259Sdimclass simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2, 4227249259Sdim Operand operand, string asmop> 4228249259Sdim : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"), 4229249259Sdim [], NoItinerary> { 4230249259Sdim let Op0 = op0; 4231249259Sdim let Op1 = op1; 4232249259Sdim let CRn = crn; 4233249259Sdim let Op2 = op2; 4234249259Sdim let Rt = 0b11111; 4235249259Sdim} 4236249259Sdim 4237249259Sdim 4238249259Sdimdef CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">; 4239249259Sdimdef DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">; 4240249259Sdimdef DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">; 4241249259Sdimdef ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">; 4242249259Sdim 4243249259Sdimdef : InstAlias<"clrex", (CLREXi 0b1111)>; 4244249259Sdimdef : InstAlias<"isb", (ISBi 0b1111)>; 4245249259Sdim 4246249259Sdim// (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP 4247249259Sdim// configurations at least. 4248249259Sdimdef : Pat<(atomic_fence imm, imm), (DMBi 0xb)>; 4249249259Sdim 4250249259Sdim// Any SYS bitpattern can be represented with a complex and opaque "SYS" 4251249259Sdim// instruction. 4252249259Sdimdef SYSiccix : A64I_system<0b0, (outs), 4253249259Sdim (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, 4254249259Sdim uimm3:$Op2, GPR64:$Rt), 4255249259Sdim "sys\t$Op1, $CRn, $CRm, $Op2, $Rt", 4256249259Sdim [], NoItinerary> { 4257249259Sdim let Op0 = 0b01; 4258249259Sdim} 4259249259Sdim 4260249259Sdim// You can skip the Xt argument whether it makes sense or not for the generic 4261249259Sdim// SYS instruction. 4262249259Sdimdef : InstAlias<"sys $Op1, $CRn, $CRm, $Op2", 4263249259Sdim (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>; 4264249259Sdim 4265249259Sdim 4266249259Sdim// But many have aliases, which obviously don't fit into 4267249259Sdimclass SYSalias<dag ins, string asmstring> 4268249259Sdim : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> { 4269249259Sdim let isAsmParserOnly = 1; 4270249259Sdim 4271249259Sdim bits<14> SysOp; 4272249259Sdim let Op0 = 0b01; 4273249259Sdim let Op1 = SysOp{13-11}; 4274249259Sdim let CRn = SysOp{10-7}; 4275249259Sdim let CRm = SysOp{6-3}; 4276249259Sdim let Op2 = SysOp{2-0}; 4277249259Sdim} 4278249259Sdim 4279249259Sdimdef ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">; 4280249259Sdim 4281249259Sdimdef ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> { 4282249259Sdim let Rt = 0b11111; 4283249259Sdim} 4284249259Sdim 4285249259Sdimdef DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">; 4286249259Sdimdef ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">; 4287249259Sdim 4288249259Sdimdef TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">; 4289249259Sdim 4290249259Sdimdef TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> { 4291249259Sdim let Rt = 0b11111; 4292249259Sdim} 4293249259Sdim 4294249259Sdim 4295249259Sdimdef SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt), 4296249259Sdim (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2), 4297249259Sdim "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2", 4298249259Sdim [], NoItinerary> { 4299249259Sdim let Op0 = 0b01; 4300249259Sdim} 4301249259Sdim 4302249259Sdim// The instructions themselves are rather simple for MSR and MRS. 4303249259Sdimdef MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt), 4304249259Sdim "msr\t$SysReg, $Rt", [], NoItinerary> { 4305249259Sdim bits<16> SysReg; 4306249259Sdim let Op0 = SysReg{15-14}; 4307249259Sdim let Op1 = SysReg{13-11}; 4308249259Sdim let CRn = SysReg{10-7}; 4309249259Sdim let CRm = SysReg{6-3}; 4310249259Sdim let Op2 = SysReg{2-0}; 4311249259Sdim} 4312249259Sdim 4313249259Sdimdef MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg), 4314249259Sdim "mrs\t$Rt, $SysReg", [], NoItinerary> { 4315249259Sdim bits<16> SysReg; 4316249259Sdim let Op0 = SysReg{15-14}; 4317249259Sdim let Op1 = SysReg{13-11}; 4318249259Sdim let CRn = SysReg{10-7}; 4319249259Sdim let CRm = SysReg{6-3}; 4320249259Sdim let Op2 = SysReg{2-0}; 4321249259Sdim} 4322249259Sdim 4323249259Sdimdef MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm), 4324249259Sdim "msr\t$PState, $CRm", [], NoItinerary> { 4325249259Sdim bits<6> PState; 4326249259Sdim 4327249259Sdim let Op0 = 0b00; 4328249259Sdim let Op1 = PState{5-3}; 4329249259Sdim let CRn = 0b0100; 4330249259Sdim let Op2 = PState{2-0}; 4331249259Sdim let Rt = 0b11111; 4332249259Sdim} 4333249259Sdim 4334249259Sdim//===----------------------------------------------------------------------===// 4335249259Sdim// Test & branch (immediate) instructions 4336249259Sdim//===----------------------------------------------------------------------===// 4337249259Sdim// Contains: TBZ, TBNZ 4338249259Sdim 4339249259Sdim// The bit to test is a simple unsigned 6-bit immediate in the X-register 4340249259Sdim// versions. 4341249259Sdimdef uimm6 : Operand<i64> { 4342249259Sdim let ParserMatchClass = uimm6_asmoperand; 4343249259Sdim} 4344249259Sdim 4345249259Sdimdef label_wid14_scal4_asmoperand : label_asmoperand<14, 4>; 4346249259Sdim 4347249259Sdimdef tbimm_target : Operand<OtherVT> { 4348249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>"; 4349249259Sdim 4350249259Sdim // This label is a 14-bit offset from PC, scaled by the instruction-width: 4. 4351249259Sdim let PrintMethod = "printLabelOperand<14, 4>"; 4352249259Sdim let ParserMatchClass = label_wid14_scal4_asmoperand; 4353249259Sdim 4354249259Sdim let OperandType = "OPERAND_PCREL"; 4355249259Sdim} 4356249259Sdim 4357249259Sdimdef A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>; 4358249259Sdimdef A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>; 4359249259Sdim 4360249259Sdim// These instructions correspond to patterns involving "and" with a power of 4361249259Sdim// two, which we need to be able to select. 4362249259Sdimdef tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">; 4363249259Sdimdef tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">; 4364249259Sdim 4365249259Sdimlet isBranch = 1, isTerminator = 1 in { 4366249259Sdim def TBZxii : A64I_TBimm<0b0, (outs), 4367249259Sdim (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4368249259Sdim "tbz\t$Rt, $Imm, $Label", 4369249259Sdim [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4370249259Sdim A64eq, bb:$Label)], 4371249259Sdim NoItinerary>; 4372249259Sdim 4373249259Sdim def TBNZxii : A64I_TBimm<0b1, (outs), 4374249259Sdim (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4375249259Sdim "tbnz\t$Rt, $Imm, $Label", 4376249259Sdim [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4377249259Sdim A64ne, bb:$Label)], 4378249259Sdim NoItinerary>; 4379249259Sdim 4380249259Sdim 4381249259Sdim // Note, these instructions overlap with the above 64-bit patterns. This is 4382249259Sdim // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both 4383249259Sdim // do the same thing and are both permitted assembly. They also both have 4384249259Sdim // sensible DAG patterns. 4385249259Sdim def TBZwii : A64I_TBimm<0b0, (outs), 4386249259Sdim (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4387249259Sdim "tbz\t$Rt, $Imm, $Label", 4388249259Sdim [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4389249259Sdim A64eq, bb:$Label)], 4390249259Sdim NoItinerary> { 4391249259Sdim let Imm{5} = 0b0; 4392249259Sdim } 4393249259Sdim 4394249259Sdim def TBNZwii : A64I_TBimm<0b1, (outs), 4395249259Sdim (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4396249259Sdim "tbnz\t$Rt, $Imm, $Label", 4397249259Sdim [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4398249259Sdim A64ne, bb:$Label)], 4399249259Sdim NoItinerary> { 4400249259Sdim let Imm{5} = 0b0; 4401249259Sdim } 4402249259Sdim} 4403249259Sdim 4404249259Sdim//===----------------------------------------------------------------------===// 4405249259Sdim// Unconditional branch (immediate) instructions 4406249259Sdim//===----------------------------------------------------------------------===// 4407249259Sdim// Contains: B, BL 4408249259Sdim 4409249259Sdimdef label_wid26_scal4_asmoperand : label_asmoperand<26, 4>; 4410249259Sdim 4411249259Sdimdef bimm_target : Operand<OtherVT> { 4412249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>"; 4413249259Sdim 4414249259Sdim // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4415249259Sdim let PrintMethod = "printLabelOperand<26, 4>"; 4416249259Sdim let ParserMatchClass = label_wid26_scal4_asmoperand; 4417249259Sdim 4418249259Sdim let OperandType = "OPERAND_PCREL"; 4419249259Sdim} 4420249259Sdim 4421249259Sdimdef blimm_target : Operand<i64> { 4422249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>"; 4423249259Sdim 4424249259Sdim // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4425249259Sdim let PrintMethod = "printLabelOperand<26, 4>"; 4426249259Sdim let ParserMatchClass = label_wid26_scal4_asmoperand; 4427249259Sdim 4428249259Sdim let OperandType = "OPERAND_PCREL"; 4429249259Sdim} 4430249259Sdim 4431249259Sdimclass A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type> 4432249259Sdim : A64I_Bimm<op, (outs), (ins lbl_type:$Label), 4433249259Sdim !strconcat(asmop, "\t$Label"), patterns, 4434249259Sdim NoItinerary>; 4435249259Sdim 4436249259Sdimlet isBranch = 1 in { 4437249259Sdim def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> { 4438249259Sdim let isTerminator = 1; 4439249259Sdim let isBarrier = 1; 4440249259Sdim } 4441249259Sdim 4442249259Sdim def BLimm : A64I_BimmImpl<0b1, "bl", 4443249259Sdim [(AArch64Call tglobaladdr:$Label)], blimm_target> { 4444249259Sdim let isCall = 1; 4445249259Sdim let Defs = [X30]; 4446249259Sdim } 4447249259Sdim} 4448249259Sdim 4449249259Sdimdef : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>; 4450249259Sdim 4451249259Sdim//===----------------------------------------------------------------------===// 4452249259Sdim// Unconditional branch (register) instructions 4453249259Sdim//===----------------------------------------------------------------------===// 4454249259Sdim// Contains: BR, BLR, RET, ERET, DRP. 4455249259Sdim 4456249259Sdim// Most of the notional opcode fields in the A64I_Breg format are fixed in A64 4457249259Sdim// at the moment. 4458249259Sdimclass A64I_BregImpl<bits<4> opc, 4459249259Sdim dag outs, dag ins, string asmstr, list<dag> patterns, 4460249259Sdim InstrItinClass itin = NoItinerary> 4461249259Sdim : A64I_Breg<opc, 0b11111, 0b000000, 0b00000, 4462249259Sdim outs, ins, asmstr, patterns, itin> { 4463249259Sdim let isBranch = 1; 4464249259Sdim let isIndirectBranch = 1; 4465249259Sdim} 4466249259Sdim 4467249259Sdim// Note that these are not marked isCall or isReturn because as far as LLVM is 4468249259Sdim// concerned they're not. "ret" is just another jump unless it has been selected 4469249259Sdim// by LLVM as the function's return. 4470249259Sdim 4471249259Sdimlet isBranch = 1 in { 4472249259Sdim def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn), 4473249259Sdim "br\t$Rn", [(brind i64:$Rn)]> { 4474249259Sdim let isBarrier = 1; 4475249259Sdim let isTerminator = 1; 4476249259Sdim } 4477249259Sdim 4478249259Sdim def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn), 4479249259Sdim "blr\t$Rn", [(AArch64Call i64:$Rn)]> { 4480249259Sdim let isBarrier = 0; 4481249259Sdim let isCall = 1; 4482249259Sdim let Defs = [X30]; 4483249259Sdim } 4484249259Sdim 4485249259Sdim def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn), 4486249259Sdim "ret\t$Rn", []> { 4487249259Sdim let isBarrier = 1; 4488249259Sdim let isTerminator = 1; 4489249259Sdim let isReturn = 1; 4490249259Sdim } 4491249259Sdim 4492249259Sdim // Create a separate pseudo-instruction for codegen to use so that we don't 4493249259Sdim // flag x30 as used in every function. It'll be restored before the RET by the 4494249259Sdim // epilogue if it's legitimately used. 4495249259Sdim def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> { 4496249259Sdim let isTerminator = 1; 4497249259Sdim let isBarrier = 1; 4498249259Sdim let isReturn = 1; 4499249259Sdim } 4500249259Sdim 4501249259Sdim def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> { 4502249259Sdim let Rn = 0b11111; 4503249259Sdim let isBarrier = 1; 4504249259Sdim let isTerminator = 1; 4505249259Sdim let isReturn = 1; 4506249259Sdim } 4507249259Sdim 4508249259Sdim def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> { 4509249259Sdim let Rn = 0b11111; 4510249259Sdim let isBarrier = 1; 4511249259Sdim } 4512249259Sdim} 4513249259Sdim 4514249259Sdimdef RETAlias : InstAlias<"ret", (RETx X30)>; 4515249259Sdim 4516249259Sdim 4517249259Sdim//===----------------------------------------------------------------------===// 4518249259Sdim// Address generation patterns 4519249259Sdim//===----------------------------------------------------------------------===// 4520249259Sdim 4521249259Sdim// Primary method of address generation for the small/absolute memory model is 4522249259Sdim// an ADRP/ADR pair: 4523249259Sdim// ADRP x0, some_variable 4524249259Sdim// ADD x0, x0, #:lo12:some_variable 4525249259Sdim// 4526249259Sdim// The load/store elision of the ADD is accomplished when selecting 4527249259Sdim// addressing-modes. This just mops up the cases where that doesn't work and we 4528249259Sdim// really need an address in some register. 4529249259Sdim 4530249259Sdim// This wrapper applies a LO12 modifier to the address. Otherwise we could just 4531249259Sdim// use the same address. 4532249259Sdim 4533249259Sdimclass ADRP_ADD<SDNode Wrapper, SDNode addrop> 4534249259Sdim : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)), 4535249259Sdim (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>; 4536249259Sdim 4537249259Sdimdef : ADRP_ADD<A64WrapperSmall, tblockaddress>; 4538249259Sdimdef : ADRP_ADD<A64WrapperSmall, texternalsym>; 4539249259Sdimdef : ADRP_ADD<A64WrapperSmall, tglobaladdr>; 4540249259Sdimdef : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>; 4541249259Sdimdef : ADRP_ADD<A64WrapperSmall, tjumptable>; 4542249259Sdim 4543249259Sdim//===----------------------------------------------------------------------===// 4544249259Sdim// GOT access patterns 4545249259Sdim//===----------------------------------------------------------------------===// 4546249259Sdim 4547249259Sdimclass GOTLoadSmall<SDNode addrfrag> 4548249259Sdim : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)), 4549249259Sdim (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>; 4550249259Sdim 4551249259Sdimdef : GOTLoadSmall<texternalsym>; 4552249259Sdimdef : GOTLoadSmall<tglobaladdr>; 4553249259Sdimdef : GOTLoadSmall<tglobaltlsaddr>; 4554249259Sdim 4555249259Sdim//===----------------------------------------------------------------------===// 4556249259Sdim// Tail call handling 4557249259Sdim//===----------------------------------------------------------------------===// 4558249259Sdim 4559249259Sdimlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in { 4560249259Sdim def TC_RETURNdi 4561249259Sdim : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff), 4562249259Sdim [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>; 4563249259Sdim 4564249259Sdim def TC_RETURNxi 4565249259Sdim : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), 4566249259Sdim [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>; 4567249259Sdim} 4568249259Sdim 4569249259Sdimlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 4570249259Sdim Uses = [XSP] in { 4571249259Sdim def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [], 4572249259Sdim (Bimm bimm_target:$Label)>; 4573249259Sdim 4574249259Sdim def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [], 4575249259Sdim (BRx GPR64:$Rd)>; 4576249259Sdim} 4577249259Sdim 4578249259Sdim 4579249259Sdimdef : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 4580249259Sdim (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>; 4581249259Sdim 4582249259Sdim//===----------------------------------------------------------------------===// 4583249259Sdim// Thread local storage 4584249259Sdim//===----------------------------------------------------------------------===// 4585249259Sdim 4586249259Sdim// This is a pseudo-instruction representing the ".tlsdesccall" directive in 4587249259Sdim// assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the 4588249259Sdim// current location. It should always be immediately followed by a BLR 4589249259Sdim// instruction, and is intended solely for relaxation by the linker. 4590249259Sdim 4591249259Sdimdef : Pat<(A64threadpointer), (MRSxi 0xde82)>; 4592249259Sdim 4593249259Sdimdef TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> { 4594249259Sdim let hasSideEffects = 1; 4595249259Sdim} 4596249259Sdim 4597249259Sdimdef TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var), 4598249259Sdim [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> { 4599249259Sdim let isCall = 1; 4600249259Sdim let Defs = [X30]; 4601249259Sdim} 4602249259Sdim 4603249259Sdimdef : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var), 4604249259Sdim (TLSDESC_BLRx $Rn, texternalsym:$Var)>; 4605249259Sdim 4606249259Sdim//===----------------------------------------------------------------------===// 4607249259Sdim// Bitfield patterns 4608249259Sdim//===----------------------------------------------------------------------===// 4609249259Sdim 4610249259Sdimdef bfi32_lsb_to_immr : SDNodeXForm<imm, [{ 4611249259Sdim return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64); 4612249259Sdim}]>; 4613249259Sdim 4614249259Sdimdef bfi64_lsb_to_immr : SDNodeXForm<imm, [{ 4615249259Sdim return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64); 4616249259Sdim}]>; 4617249259Sdim 4618249259Sdimdef bfi_width_to_imms : SDNodeXForm<imm, [{ 4619249259Sdim return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64); 4620249259Sdim}]>; 4621249259Sdim 4622249259Sdim 4623249259Sdim// The simpler patterns deal with cases where no AND mask is actually needed 4624249259Sdim// (either all bits are used or the low 32 bits are used). 4625249259Sdimlet AddedComplexity = 10 in { 4626249259Sdim 4627249259Sdimdef : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4628249259Sdim (BFIxxii $src, $Rn, 4629249259Sdim (bfi64_lsb_to_immr (i64 imm:$ImmR)), 4630249259Sdim (bfi_width_to_imms (i64 imm:$ImmS)))>; 4631249259Sdim 4632249259Sdimdef : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS), 4633249259Sdim (BFIwwii $src, $Rn, 4634249259Sdim (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4635249259Sdim (bfi_width_to_imms (i64 imm:$ImmS)))>; 4636249259Sdim 4637249259Sdim 4638249259Sdimdef : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4639249259Sdim (i64 4294967295)), 4640249259Sdim (SUBREG_TO_REG (i64 0), 4641249259Sdim (BFIwwii (EXTRACT_SUBREG $src, sub_32), 4642249259Sdim (EXTRACT_SUBREG $Rn, sub_32), 4643249259Sdim (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4644249259Sdim (bfi_width_to_imms (i64 imm:$ImmS))), 4645249259Sdim sub_32)>; 4646249259Sdim 4647249259Sdim} 4648249259Sdim 4649249259Sdim//===----------------------------------------------------------------------===// 4650249259Sdim// Miscellaneous patterns 4651249259Sdim//===----------------------------------------------------------------------===// 4652249259Sdim 4653249259Sdim// Truncation from 64 to 32-bits just involves renaming your register. 4654249259Sdimdef : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>; 4655249259Sdim 4656249259Sdim// Similarly, extension where we don't care about the high bits is 4657249259Sdim// just a rename. 4658249259Sdimdef : Pat<(i64 (anyext i32:$val)), 4659249259Sdim (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>; 4660249259Sdim 4661249259Sdim// SELECT instructions providing f128 types need to be handled by a 4662249259Sdim// pseudo-instruction since the eventual code will need to introduce basic 4663249259Sdim// blocks and control flow. 4664249259Sdimdef F128CSEL : PseudoInst<(outs FPR128:$Rd), 4665249259Sdim (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond), 4666249259Sdim [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> { 4667249259Sdim let Uses = [NZCV]; 4668249259Sdim let usesCustomInserter = 1; 4669249259Sdim} 4670249259Sdim 4671249259Sdim//===----------------------------------------------------------------------===// 4672249259Sdim// Load/store patterns 4673249259Sdim//===----------------------------------------------------------------------===// 4674249259Sdim 4675249259Sdim// There are lots of patterns here, because we need to allow at least three 4676249259Sdim// parameters to vary independently. 4677249259Sdim// 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ... 4678249259Sdim// 2. LLVM source: zextloadi8, anyextloadi8, ... 4679249259Sdim// 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ... 4680249259Sdim// 4681249259Sdim// The biggest problem turns out to be the address-generation variable. At the 4682249259Sdim// point of instantiation we need to produce two DAGs, one for the pattern and 4683249259Sdim// one for the instruction. Doing this at the lowest level of classes doesn't 4684249259Sdim// work. 4685249259Sdim// 4686249259Sdim// Consider the simple uimm12 addressing mode, and the desire to match both (add 4687249259Sdim// GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the 4688249259Sdim// instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or 4689249259Sdim// "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this 4690249259Sdim// operation, and PatFrags are for selection not output. 4691249259Sdim// 4692249259Sdim// As a result, the address-generation patterns are the final 4693249259Sdim// instantiations. However, we do still need to vary the operand for the address 4694249259Sdim// further down (At the point we're deciding A64WrapperSmall, we don't know 4695249259Sdim// the memory width of the operation). 4696249259Sdim 4697249259Sdim//===------------------------------ 4698249259Sdim// 1. Basic infrastructural defs 4699249259Sdim//===------------------------------ 4700249259Sdim 4701249259Sdim// First, some simple classes for !foreach and !subst to use: 4702249259Sdimclass Decls { 4703249259Sdim dag pattern; 4704249259Sdim} 4705249259Sdim 4706249259Sdimdef decls : Decls; 4707249259Sdimdef ALIGN; 4708249259Sdimdef INST; 4709249259Sdimdef OFFSET; 4710249259Sdimdef SHIFT; 4711249259Sdim 4712249259Sdim// You can't use !subst on an actual immediate, but you *can* use it on an 4713249259Sdim// operand record that happens to match a single immediate. So we do. 4714249259Sdimdef imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>; 4715249259Sdimdef imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>; 4716249259Sdimdef imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>; 4717249259Sdimdef imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>; 4718249259Sdimdef imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>; 4719249259Sdim 4720249259Sdim// If the low bits of a pointer are known to be 0 then an "or" is just as good 4721249259Sdim// as addition for computing an offset. This fragment forwards that check for 4722249259Sdim// TableGen's use. 4723249259Sdimdef add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), 4724249259Sdim[{ 4725249259Sdim return CurDAG->isBaseWithConstantOffset(SDValue(N, 0)); 4726249259Sdim}]>; 4727249259Sdim 4728249259Sdim// Load/store (unsigned immediate) operations with relocations against global 4729249259Sdim// symbols (for lo12) are only valid if those symbols have correct alignment 4730249259Sdim// (since the immediate offset is divided by the access scale, it can't have a 4731249259Sdim// remainder). 4732249259Sdim// 4733249259Sdim// The guaranteed alignment is provided as part of the WrapperSmall 4734249259Sdim// operation, and checked against one of these. 4735249259Sdimdef any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>; 4736249259Sdimdef min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>; 4737249259Sdimdef min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>; 4738249259Sdimdef min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>; 4739249259Sdimdef min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>; 4740249259Sdim 4741249259Sdim// "Normal" load/store instructions can be used on atomic operations, provided 4742249259Sdim// the ordering parameter is at most "monotonic". Anything above that needs 4743249259Sdim// special handling with acquire/release instructions. 4744249259Sdimclass simple_load<PatFrag base> 4745249259Sdim : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4746249259Sdim return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4747249259Sdim}]>; 4748249259Sdim 4749249259Sdimdef atomic_load_simple_i8 : simple_load<atomic_load_8>; 4750249259Sdimdef atomic_load_simple_i16 : simple_load<atomic_load_16>; 4751249259Sdimdef atomic_load_simple_i32 : simple_load<atomic_load_32>; 4752249259Sdimdef atomic_load_simple_i64 : simple_load<atomic_load_64>; 4753249259Sdim 4754249259Sdimclass simple_store<PatFrag base> 4755249259Sdim : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4756249259Sdim return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4757249259Sdim}]>; 4758249259Sdim 4759249259Sdimdef atomic_store_simple_i8 : simple_store<atomic_store_8>; 4760249259Sdimdef atomic_store_simple_i16 : simple_store<atomic_store_16>; 4761249259Sdimdef atomic_store_simple_i32 : simple_store<atomic_store_32>; 4762249259Sdimdef atomic_store_simple_i64 : simple_store<atomic_store_64>; 4763249259Sdim 4764249259Sdim//===------------------------------ 4765249259Sdim// 2. UImm12 and SImm9 4766249259Sdim//===------------------------------ 4767249259Sdim 4768249259Sdim// These instructions have two operands providing the address so they can be 4769249259Sdim// treated similarly for most purposes. 4770249259Sdim 4771249259Sdim//===------------------------------ 4772249259Sdim// 2.1 Base patterns covering extend/truncate semantics 4773249259Sdim//===------------------------------ 4774249259Sdim 4775249259Sdim// Atomic patterns can be shared between integer operations of all sizes, a 4776249259Sdim// quick multiclass here allows reuse. 4777249259Sdimmulticlass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4778249259Sdim dag Offset, dag address, ValueType transty, 4779249259Sdim ValueType sty> { 4780249259Sdim def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4781249259Sdim (LOAD Base, Offset)>; 4782249259Sdim 4783249259Sdim def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4784249259Sdim (STORE $Rt, Base, Offset)>; 4785249259Sdim} 4786249259Sdim 4787249259Sdim// Instructions accessing a memory chunk smaller than a register (or, in a 4788249259Sdim// pinch, the same size) have a characteristic set of patterns they want to 4789249259Sdim// match: extending loads and truncating stores. This class deals with the 4790249259Sdim// sign-neutral version of those patterns. 4791249259Sdim// 4792249259Sdim// It will be instantiated across multiple addressing-modes. 4793249259Sdimmulticlass ls_small_pats<Instruction LOAD, Instruction STORE, 4794249259Sdim dag Base, dag Offset, 4795249259Sdim dag address, ValueType sty> 4796249259Sdim : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> { 4797249259Sdim def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>; 4798249259Sdim 4799249259Sdim def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>; 4800249259Sdim 4801249259Sdim // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4802249259Sdim // register was actually set. 4803249259Sdim def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4804249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4805249259Sdim 4806249259Sdim def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4807249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4808249259Sdim 4809249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4810249259Sdim (STORE $Rt, Base, Offset)>; 4811249259Sdim 4812249259Sdim // For truncating store from 64-bits, we have to manually tell LLVM to 4813249259Sdim // ignore the high bits of the x register. 4814249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4815249259Sdim (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4816249259Sdim} 4817249259Sdim 4818249259Sdim// Next come patterns for sign-extending loads. 4819249259Sdimmulticlass load_signed_pats<string T, string U, dag Base, dag Offset, 4820249259Sdim dag address, ValueType sty> { 4821249259Sdim def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4822249259Sdim (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>; 4823249259Sdim 4824249259Sdim def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 4825249259Sdim (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>; 4826249259Sdim 4827249259Sdim} 4828249259Sdim 4829249259Sdim// and finally "natural-width" loads and stores come next. 4830249259Sdimmulticlass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4831249259Sdim dag Offset, dag address, ValueType sty> { 4832249259Sdim def : Pat<(sty (load address)), (LOAD Base, Offset)>; 4833249259Sdim def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>; 4834249259Sdim} 4835249259Sdim 4836249259Sdim// Integer operations also get atomic instructions to select for. 4837249259Sdimmulticlass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4838249259Sdim dag Offset, dag address, ValueType sty> 4839249259Sdim : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>, 4840249259Sdim ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>; 4841249259Sdim 4842249259Sdim//===------------------------------ 4843249259Sdim// 2.2. Addressing-mode instantiations 4844249259Sdim//===------------------------------ 4845249259Sdim 4846249259Sdimmulticlass uimm12_pats<dag address, dag Base, dag Offset> { 4847249259Sdim defm : ls_small_pats<LS8_LDR, LS8_STR, Base, 4848249259Sdim !foreach(decls.pattern, Offset, 4849249259Sdim !subst(OFFSET, byte_uimm12, decls.pattern)), 4850249259Sdim !foreach(decls.pattern, address, 4851249259Sdim !subst(OFFSET, byte_uimm12, 4852249259Sdim !subst(ALIGN, any_align, decls.pattern))), 4853249259Sdim i8>; 4854249259Sdim defm : ls_small_pats<LS16_LDR, LS16_STR, Base, 4855249259Sdim !foreach(decls.pattern, Offset, 4856249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4857249259Sdim !foreach(decls.pattern, address, 4858249259Sdim !subst(OFFSET, hword_uimm12, 4859249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4860249259Sdim i16>; 4861249259Sdim defm : ls_small_pats<LS32_LDR, LS32_STR, Base, 4862249259Sdim !foreach(decls.pattern, Offset, 4863249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4864249259Sdim !foreach(decls.pattern, address, 4865249259Sdim !subst(OFFSET, word_uimm12, 4866249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4867249259Sdim i32>; 4868249259Sdim 4869249259Sdim defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base, 4870249259Sdim !foreach(decls.pattern, Offset, 4871249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4872249259Sdim !foreach(decls.pattern, address, 4873249259Sdim !subst(OFFSET, word_uimm12, 4874249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4875249259Sdim i32>; 4876249259Sdim 4877249259Sdim defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base, 4878249259Sdim !foreach(decls.pattern, Offset, 4879249259Sdim !subst(OFFSET, dword_uimm12, decls.pattern)), 4880249259Sdim !foreach(decls.pattern, address, 4881249259Sdim !subst(OFFSET, dword_uimm12, 4882249259Sdim !subst(ALIGN, min_align8, decls.pattern))), 4883249259Sdim i64>; 4884249259Sdim 4885249259Sdim defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base, 4886249259Sdim !foreach(decls.pattern, Offset, 4887249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4888249259Sdim !foreach(decls.pattern, address, 4889249259Sdim !subst(OFFSET, hword_uimm12, 4890249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4891249259Sdim f16>; 4892249259Sdim 4893249259Sdim defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base, 4894249259Sdim !foreach(decls.pattern, Offset, 4895249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4896249259Sdim !foreach(decls.pattern, address, 4897249259Sdim !subst(OFFSET, word_uimm12, 4898249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4899249259Sdim f32>; 4900249259Sdim 4901249259Sdim defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base, 4902249259Sdim !foreach(decls.pattern, Offset, 4903249259Sdim !subst(OFFSET, dword_uimm12, decls.pattern)), 4904249259Sdim !foreach(decls.pattern, address, 4905249259Sdim !subst(OFFSET, dword_uimm12, 4906249259Sdim !subst(ALIGN, min_align8, decls.pattern))), 4907249259Sdim f64>; 4908249259Sdim 4909249259Sdim defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base, 4910249259Sdim !foreach(decls.pattern, Offset, 4911249259Sdim !subst(OFFSET, qword_uimm12, decls.pattern)), 4912249259Sdim !foreach(decls.pattern, address, 4913249259Sdim !subst(OFFSET, qword_uimm12, 4914249259Sdim !subst(ALIGN, min_align16, decls.pattern))), 4915249259Sdim f128>; 4916249259Sdim 4917249259Sdim defm : load_signed_pats<"B", "", Base, 4918249259Sdim !foreach(decls.pattern, Offset, 4919249259Sdim !subst(OFFSET, byte_uimm12, decls.pattern)), 4920249259Sdim !foreach(decls.pattern, address, 4921249259Sdim !subst(OFFSET, byte_uimm12, 4922249259Sdim !subst(ALIGN, any_align, decls.pattern))), 4923249259Sdim i8>; 4924249259Sdim 4925249259Sdim defm : load_signed_pats<"H", "", Base, 4926249259Sdim !foreach(decls.pattern, Offset, 4927249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4928249259Sdim !foreach(decls.pattern, address, 4929249259Sdim !subst(OFFSET, hword_uimm12, 4930249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4931249259Sdim i16>; 4932249259Sdim 4933249259Sdim def : Pat<(sextloadi32 !foreach(decls.pattern, address, 4934249259Sdim !subst(OFFSET, word_uimm12, 4935249259Sdim !subst(ALIGN, min_align4, decls.pattern)))), 4936249259Sdim (LDRSWx Base, !foreach(decls.pattern, Offset, 4937249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)))>; 4938249259Sdim} 4939249259Sdim 4940249259Sdim// Straightforward patterns of last resort: a pointer with or without an 4941249259Sdim// appropriate offset. 4942249259Sdimdefm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>; 4943249259Sdimdefm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12), 4944249259Sdim (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4945249259Sdim 4946249259Sdim// The offset could be hidden behind an "or", of course: 4947249259Sdimdefm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12), 4948249259Sdim (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4949249259Sdim 4950249259Sdim// Global addresses under the small-absolute model should use these 4951249259Sdim// instructions. There are ELF relocations specifically for it. 4952249259Sdimdefm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN), 4953249259Sdim (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>; 4954249259Sdim 4955249259Sdimdefm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, 4956249259Sdim ALIGN), 4957249259Sdim (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>; 4958249259Sdim 4959249259Sdim// External symbols that make it this far should also get standard relocations. 4960249259Sdimdefm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, 4961249259Sdim ALIGN), 4962249259Sdim (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>; 4963249259Sdim 4964249259Sdimdefm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN), 4965249259Sdim (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>; 4966249259Sdim 4967249259Sdim// We also want to use uimm12 instructions for local variables at the moment. 4968249259Sdimdef tframeindex_XFORM : SDNodeXForm<frameindex, [{ 4969249259Sdim int FI = cast<FrameIndexSDNode>(N)->getIndex(); 4970249259Sdim return CurDAG->getTargetFrameIndex(FI, MVT::i64); 4971249259Sdim}]>; 4972249259Sdim 4973249259Sdimdefm : uimm12_pats<(i64 frameindex:$Rn), 4974249259Sdim (tframeindex_XFORM tframeindex:$Rn), (i64 0)>; 4975249259Sdim 4976249259Sdim// These can be much simpler than uimm12 because we don't to change the operand 4977249259Sdim// type (e.g. LDURB and LDURH take the same operands). 4978249259Sdimmulticlass simm9_pats<dag address, dag Base, dag Offset> { 4979249259Sdim defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>; 4980249259Sdim defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>; 4981249259Sdim 4982249259Sdim defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>; 4983249259Sdim defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>; 4984249259Sdim 4985249259Sdim defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>; 4986249259Sdim defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>; 4987249259Sdim defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>; 4988249259Sdim defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address, 4989249259Sdim f128>; 4990249259Sdim 4991249259Sdim def : Pat<(i64 (zextloadi32 address)), 4992249259Sdim (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>; 4993249259Sdim 4994249259Sdim def : Pat<(truncstorei32 i64:$Rt, address), 4995249259Sdim (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4996249259Sdim 4997249259Sdim defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>; 4998249259Sdim defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>; 4999249259Sdim def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>; 5000249259Sdim} 5001249259Sdim 5002249259Sdimdefm : simm9_pats<(add i64:$Rn, simm9:$SImm9), 5003249259Sdim (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 5004249259Sdim 5005249259Sdimdefm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9), 5006249259Sdim (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 5007249259Sdim 5008249259Sdim 5009249259Sdim//===------------------------------ 5010249259Sdim// 3. Register offset patterns 5011249259Sdim//===------------------------------ 5012249259Sdim 5013249259Sdim// Atomic patterns can be shared between integer operations of all sizes, a 5014249259Sdim// quick multiclass here allows reuse. 5015249259Sdimmulticlass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 5016249259Sdim dag Offset, dag Extend, dag address, 5017249259Sdim ValueType transty, ValueType sty> { 5018249259Sdim def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 5019249259Sdim (LOAD Base, Offset, Extend)>; 5020249259Sdim 5021249259Sdim def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 5022249259Sdim (STORE $Rt, Base, Offset, Extend)>; 5023249259Sdim} 5024249259Sdim 5025249259Sdim// The register offset instructions take three operands giving the instruction, 5026249259Sdim// and have an annoying split between instructions where Rm is 32-bit and 5027249259Sdim// 64-bit. So we need a special hierarchy to describe them. Other than that the 5028249259Sdim// same operations should be supported as for simm9 and uimm12 addressing. 5029249259Sdim 5030249259Sdimmulticlass ro_small_pats<Instruction LOAD, Instruction STORE, 5031249259Sdim dag Base, dag Offset, dag Extend, 5032249259Sdim dag address, ValueType sty> 5033249259Sdim : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> { 5034249259Sdim def : Pat<(!cast<SDNode>(zextload # sty) address), 5035249259Sdim (LOAD Base, Offset, Extend)>; 5036249259Sdim 5037249259Sdim def : Pat<(!cast<SDNode>(extload # sty) address), 5038249259Sdim (LOAD Base, Offset, Extend)>; 5039249259Sdim 5040249259Sdim // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 5041249259Sdim // register was actually set. 5042249259Sdim def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 5043249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 5044249259Sdim 5045249259Sdim def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 5046249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 5047249259Sdim 5048249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 5049249259Sdim (STORE $Rt, Base, Offset, Extend)>; 5050249259Sdim 5051249259Sdim // For truncating store from 64-bits, we have to manually tell LLVM to 5052249259Sdim // ignore the high bits of the x register. 5053249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 5054249259Sdim (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>; 5055249259Sdim 5056249259Sdim} 5057249259Sdim 5058249259Sdim// Next come patterns for sign-extending loads. 5059249259Sdimmulticlass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend, 5060249259Sdim dag address, ValueType sty> { 5061249259Sdim def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 5062249259Sdim (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset") 5063249259Sdim Base, Offset, Extend)>; 5064249259Sdim 5065249259Sdim def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 5066249259Sdim (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset") 5067249259Sdim Base, Offset, Extend)>; 5068249259Sdim} 5069249259Sdim 5070249259Sdim// and finally "natural-width" loads and stores come next. 5071249259Sdimmulticlass ro_neutral_pats<Instruction LOAD, Instruction STORE, 5072249259Sdim dag Base, dag Offset, dag Extend, dag address, 5073249259Sdim ValueType sty> { 5074249259Sdim def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>; 5075249259Sdim def : Pat<(store sty:$Rt, address), 5076249259Sdim (STORE $Rt, Base, Offset, Extend)>; 5077249259Sdim} 5078249259Sdim 5079249259Sdimmulticlass ro_int_neutral_pats<Instruction LOAD, Instruction STORE, 5080249259Sdim dag Base, dag Offset, dag Extend, dag address, 5081249259Sdim ValueType sty> 5082249259Sdim : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>, 5083249259Sdim ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>; 5084249259Sdim 5085249259Sdimmulticlass regoff_pats<string Rm, dag address, dag Base, dag Offset, 5086249259Sdim dag Extend> { 5087249259Sdim defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"), 5088249259Sdim !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"), 5089249259Sdim Base, Offset, Extend, 5090249259Sdim !foreach(decls.pattern, address, 5091249259Sdim !subst(SHIFT, imm_eq0, decls.pattern)), 5092249259Sdim i8>; 5093249259Sdim defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"), 5094249259Sdim !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"), 5095249259Sdim Base, Offset, Extend, 5096249259Sdim !foreach(decls.pattern, address, 5097249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5098249259Sdim i16>; 5099249259Sdim defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5100249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5101249259Sdim Base, Offset, Extend, 5102249259Sdim !foreach(decls.pattern, address, 5103249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5104249259Sdim i32>; 5105249259Sdim 5106249259Sdim defm : ro_int_neutral_pats< 5107249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5108249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5109249259Sdim Base, Offset, Extend, 5110249259Sdim !foreach(decls.pattern, address, 5111249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5112249259Sdim i32>; 5113249259Sdim 5114249259Sdim defm : ro_int_neutral_pats< 5115249259Sdim !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"), 5116249259Sdim !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"), 5117249259Sdim Base, Offset, Extend, 5118249259Sdim !foreach(decls.pattern, address, 5119249259Sdim !subst(SHIFT, imm_eq3, decls.pattern)), 5120249259Sdim i64>; 5121249259Sdim 5122249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"), 5123249259Sdim !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"), 5124249259Sdim Base, Offset, Extend, 5125249259Sdim !foreach(decls.pattern, address, 5126249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5127249259Sdim f16>; 5128249259Sdim 5129249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"), 5130249259Sdim !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"), 5131249259Sdim Base, Offset, Extend, 5132249259Sdim !foreach(decls.pattern, address, 5133249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5134249259Sdim f32>; 5135249259Sdim 5136249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"), 5137249259Sdim !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"), 5138249259Sdim Base, Offset, Extend, 5139249259Sdim !foreach(decls.pattern, address, 5140249259Sdim !subst(SHIFT, imm_eq3, decls.pattern)), 5141249259Sdim f64>; 5142249259Sdim 5143249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"), 5144249259Sdim !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"), 5145249259Sdim Base, Offset, Extend, 5146249259Sdim !foreach(decls.pattern, address, 5147249259Sdim !subst(SHIFT, imm_eq4, decls.pattern)), 5148249259Sdim f128>; 5149249259Sdim 5150249259Sdim defm : ro_signed_pats<"B", Rm, Base, Offset, Extend, 5151249259Sdim !foreach(decls.pattern, address, 5152249259Sdim !subst(SHIFT, imm_eq0, decls.pattern)), 5153249259Sdim i8>; 5154249259Sdim 5155249259Sdim defm : ro_signed_pats<"H", Rm, Base, Offset, Extend, 5156249259Sdim !foreach(decls.pattern, address, 5157249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5158249259Sdim i16>; 5159249259Sdim 5160249259Sdim def : Pat<(sextloadi32 !foreach(decls.pattern, address, 5161249259Sdim !subst(SHIFT, imm_eq2, decls.pattern))), 5162249259Sdim (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset") 5163249259Sdim Base, Offset, Extend)>; 5164249259Sdim} 5165249259Sdim 5166249259Sdim 5167249259Sdim// Finally we're in a position to tell LLVM exactly what addresses are reachable 5168249259Sdim// using register-offset instructions. Essentially a base plus a possibly 5169249259Sdim// extended, possibly shifted (by access size) offset. 5170249259Sdim 5171249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)), 5172249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>; 5173249259Sdim 5174249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)), 5175249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>; 5176249259Sdim 5177249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)), 5178249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>; 5179249259Sdim 5180249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)), 5181249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>; 5182249259Sdim 5183249259Sdimdefm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm), 5184249259Sdim (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>; 5185249259Sdim 5186249259Sdimdefm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)), 5187249259Sdim (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>; 5188263508Sdim 5189263508Sdim//===----------------------------------------------------------------------===// 5190263508Sdim// Advanced SIMD (NEON) Support 5191263508Sdim// 5192263508Sdim 5193263508Sdiminclude "AArch64InstrNEON.td" 5194