AArch64InstrInfo.td revision 251662
1249259Sdim//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file describes the AArch64 scalar instructions in TableGen format. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdiminclude "AArch64InstrFormats.td" 15249259Sdim 16249259Sdim//===----------------------------------------------------------------------===// 17249259Sdim// Target-specific ISD nodes and profiles 18249259Sdim//===----------------------------------------------------------------------===// 19249259Sdim 20249259Sdimdef SDT_A64ret : SDTypeProfile<0, 0, []>; 21249259Sdimdef A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain, 22249259Sdim SDNPOptInGlue, 23249259Sdim SDNPVariadic]>; 24249259Sdim 25249259Sdim// (ins NZCV, Condition, Dest) 26249259Sdimdef SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>; 27249259Sdimdef A64br_cc : SDNode<"AArch64ISD::BR_CC", SDT_A64br_cc, [SDNPHasChain]>; 28249259Sdim 29249259Sdim// (outs Result), (ins NZCV, IfTrue, IfFalse, Condition) 30249259Sdimdef SDT_A64select_cc : SDTypeProfile<1, 4, [SDTCisVT<1, i32>, 31249259Sdim SDTCisSameAs<0, 2>, 32249259Sdim SDTCisSameAs<2, 3>]>; 33249259Sdimdef A64select_cc : SDNode<"AArch64ISD::SELECT_CC", SDT_A64select_cc>; 34249259Sdim 35249259Sdim// (outs NZCV), (ins LHS, RHS, Condition) 36249259Sdimdef SDT_A64setcc : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, 37249259Sdim SDTCisSameAs<1, 2>]>; 38249259Sdimdef A64setcc : SDNode<"AArch64ISD::SETCC", SDT_A64setcc>; 39249259Sdim 40249259Sdim 41249259Sdim// (outs GPR64), (ins) 42249259Sdimdef A64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>; 43249259Sdim 44249259Sdim// A64 compares don't care about the cond really (they set all flags) so a 45249259Sdim// simple binary operator is useful. 46249259Sdimdef A64cmp : PatFrag<(ops node:$lhs, node:$rhs), 47249259Sdim (A64setcc node:$lhs, node:$rhs, cond)>; 48249259Sdim 49249259Sdim 50249259Sdim// When matching a notional (CMP op1, (sub 0, op2)), we'd like to use a CMN 51249259Sdim// instruction on the grounds that "op1 - (-op2) == op1 + op2". However, the C 52249259Sdim// and V flags can be set differently by this operation. It comes down to 53249259Sdim// whether "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are 54249259Sdim// then everything is fine. If not then the optimization is wrong. Thus general 55249259Sdim// comparisons are only valid if op2 != 0. 56249259Sdim 57249259Sdim// So, finally, the only LLVM-native comparisons that don't mention C and V are 58249259Sdim// SETEQ and SETNE. They're the only ones we can safely use CMN for in the 59249259Sdim// absence of information about op2. 60249259Sdimdef equality_cond : PatLeaf<(cond), [{ 61249259Sdim return N->get() == ISD::SETEQ || N->get() == ISD::SETNE; 62249259Sdim}]>; 63249259Sdim 64249259Sdimdef A64cmn : PatFrag<(ops node:$lhs, node:$rhs), 65249259Sdim (A64setcc node:$lhs, (sub 0, node:$rhs), equality_cond)>; 66249259Sdim 67249259Sdim// There are two layers of indirection here, driven by the following 68249259Sdim// considerations. 69249259Sdim// + TableGen does not know CodeModel or Reloc so that decision should be 70249259Sdim// made for a variable/address at ISelLowering. 71249259Sdim// + The output of ISelLowering should be selectable (hence the Wrapper, 72249259Sdim// rather than a bare target opcode) 73251662Sdimdef SDTAArch64WrapperLarge : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 74251662Sdim SDTCisSameAs<0, 2>, 75251662Sdim SDTCisSameAs<0, 3>, 76251662Sdim SDTCisSameAs<0, 4>, 77251662Sdim SDTCisPtrTy<0>]>; 78249259Sdim 79251662Sdimdef A64WrapperLarge :SDNode<"AArch64ISD::WrapperLarge", SDTAArch64WrapperLarge>; 80249259Sdim 81251662Sdimdef SDTAArch64WrapperSmall : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 82251662Sdim SDTCisSameAs<1, 2>, 83251662Sdim SDTCisVT<3, i32>, 84251662Sdim SDTCisPtrTy<0>]>; 85249259Sdim 86251662Sdimdef A64WrapperSmall :SDNode<"AArch64ISD::WrapperSmall", SDTAArch64WrapperSmall>; 87251662Sdim 88251662Sdim 89249259Sdimdef SDTAArch64GOTLoad : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 90249259Sdimdef A64GOTLoad : SDNode<"AArch64ISD::GOTLoad", SDTAArch64GOTLoad, 91249259Sdim [SDNPHasChain]>; 92249259Sdim 93249259Sdim 94249259Sdim// (A64BFI LHS, RHS, LSB, Width) 95249259Sdimdef SDTA64BFI : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 96249259Sdim SDTCisSameAs<1, 2>, 97249259Sdim SDTCisVT<3, i64>, 98249259Sdim SDTCisVT<4, i64>]>; 99249259Sdim 100249259Sdimdef A64Bfi : SDNode<"AArch64ISD::BFI", SDTA64BFI>; 101249259Sdim 102249259Sdim// (A64EXTR HiReg, LoReg, LSB) 103249259Sdimdef SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 104249259Sdim SDTCisVT<3, i64>]>; 105249259Sdimdef A64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>; 106249259Sdim 107249259Sdim// (A64[SU]BFX Field, ImmR, ImmS). 108249259Sdim// 109249259Sdim// Note that ImmR and ImmS are already encoded for the actual instructions. The 110249259Sdim// more natural LSB and Width mix together to form ImmR and ImmS, something 111249259Sdim// which TableGen can't handle. 112249259Sdimdef SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 113249259Sdimdef A64Sbfx : SDNode<"AArch64ISD::SBFX", SDTA64BFX>; 114249259Sdim 115249259Sdimdef A64Ubfx : SDNode<"AArch64ISD::UBFX", SDTA64BFX>; 116249259Sdim 117249259Sdim//===----------------------------------------------------------------------===// 118249259Sdim// Call sequence pseudo-instructions 119249259Sdim//===----------------------------------------------------------------------===// 120249259Sdim 121249259Sdim 122249259Sdimdef SDT_AArch64Call : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 123249259Sdimdef AArch64Call : SDNode<"AArch64ISD::Call", SDT_AArch64Call, 124249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; 125249259Sdim 126249259Sdimdef AArch64tcret : SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64Call, 127249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 128249259Sdim 129249259Sdim// The TLSDESCCALL node is a variant call which goes to an indirectly calculated 130249259Sdim// destination but needs a relocation against a fixed symbol. As such it has two 131249259Sdim// certain operands: the callee and the relocated variable. 132249259Sdim// 133249259Sdim// The TLS ABI only allows it to be selected to a BLR instructin (with 134249259Sdim// appropriate relocation). 135249259Sdimdef SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 136249259Sdim 137249259Sdimdef A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall, 138249259Sdim [SDNPInGlue, SDNPOutGlue, SDNPHasChain, 139249259Sdim SDNPVariadic]>; 140249259Sdim 141249259Sdim 142249259Sdimdef SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>; 143249259Sdimdef AArch64callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AArch64CallSeqStart, 144249259Sdim [SDNPHasChain, SDNPOutGlue]>; 145249259Sdim 146249259Sdimdef SDT_AArch64CallSeqEnd : SDCallSeqEnd<[ SDTCisPtrTy<0>, SDTCisPtrTy<1> ]>; 147249259Sdimdef AArch64callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AArch64CallSeqEnd, 148249259Sdim [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 149249259Sdim 150249259Sdim 151249259Sdim 152249259Sdim// These pseudo-instructions have special semantics by virtue of being passed to 153249259Sdim// the InstrInfo constructor. CALLSEQ_START/CALLSEQ_END are produced by 154249259Sdim// LowerCall to (in our case) tell the back-end about stack adjustments for 155249259Sdim// arguments passed on the stack. Here we select those markers to 156249259Sdim// pseudo-instructions which explicitly set the stack, and finally in the 157249259Sdim// RegisterInfo we convert them to a true stack adjustment. 158249259Sdimlet Defs = [XSP], Uses = [XSP] in { 159249259Sdim def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt), 160249259Sdim [(AArch64callseq_start timm:$amt)]>; 161249259Sdim 162249259Sdim def ADJCALLSTACKUP : PseudoInst<(outs), (ins i64imm:$amt1, i64imm:$amt2), 163249259Sdim [(AArch64callseq_end timm:$amt1, timm:$amt2)]>; 164249259Sdim} 165249259Sdim 166249259Sdim//===----------------------------------------------------------------------===// 167249259Sdim// Atomic operation pseudo-instructions 168249259Sdim//===----------------------------------------------------------------------===// 169249259Sdim 170251662Sdim// These get selected from C++ code as a pretty much direct translation from the 171251662Sdim// generic DAG nodes. The one exception is the AtomicOrdering is added as an 172251662Sdim// operand so that the eventual lowering can make use of it and choose 173251662Sdim// acquire/release operations when required. 174251662Sdim 175251662Sdimlet usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1 in { 176251662Sdimmulticlass AtomicSizes { 177251662Sdim def _I8 : PseudoInst<(outs GPR32:$dst), 178251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 179251662Sdim def _I16 : PseudoInst<(outs GPR32:$dst), 180251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 181251662Sdim def _I32 : PseudoInst<(outs GPR32:$dst), 182251662Sdim (ins GPR64xsp:$ptr, GPR32:$incr, i32imm:$ordering), []>; 183251662Sdim def _I64 : PseudoInst<(outs GPR64:$dst), 184251662Sdim (ins GPR64xsp:$ptr, GPR64:$incr, i32imm:$ordering), []>; 185249259Sdim} 186249259Sdim} 187249259Sdim 188251662Sdimdefm ATOMIC_LOAD_ADD : AtomicSizes; 189251662Sdimdefm ATOMIC_LOAD_SUB : AtomicSizes; 190251662Sdimdefm ATOMIC_LOAD_AND : AtomicSizes; 191251662Sdimdefm ATOMIC_LOAD_OR : AtomicSizes; 192251662Sdimdefm ATOMIC_LOAD_XOR : AtomicSizes; 193251662Sdimdefm ATOMIC_LOAD_NAND : AtomicSizes; 194251662Sdimdefm ATOMIC_SWAP : AtomicSizes; 195249259Sdimlet Defs = [NZCV] in { 196249259Sdim // These operations need a CMP to calculate the correct value 197251662Sdim defm ATOMIC_LOAD_MIN : AtomicSizes; 198251662Sdim defm ATOMIC_LOAD_MAX : AtomicSizes; 199251662Sdim defm ATOMIC_LOAD_UMIN : AtomicSizes; 200251662Sdim defm ATOMIC_LOAD_UMAX : AtomicSizes; 201249259Sdim} 202249259Sdim 203251662Sdimclass AtomicCmpSwap<RegisterClass GPRData> 204251662Sdim : PseudoInst<(outs GPRData:$dst), 205251662Sdim (ins GPR64xsp:$ptr, GPRData:$old, GPRData:$new, 206251662Sdim i32imm:$ordering), []> { 207251662Sdim let usesCustomInserter = 1; 208251662Sdim let hasCtrlDep = 1; 209251662Sdim let mayLoad = 1; 210251662Sdim let mayStore = 1; 211251662Sdim let Defs = [NZCV]; 212249259Sdim} 213249259Sdim 214251662Sdimdef ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<GPR32>; 215251662Sdimdef ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<GPR32>; 216251662Sdimdef ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<GPR32>; 217251662Sdimdef ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<GPR64>; 218251662Sdim 219249259Sdim//===----------------------------------------------------------------------===// 220249259Sdim// Add-subtract (extended register) instructions 221249259Sdim//===----------------------------------------------------------------------===// 222249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP 223249259Sdim 224249259Sdim// The RHS of these operations is conceptually a sign/zero-extended 225249259Sdim// register, optionally shifted left by 1-4. The extension can be a 226249259Sdim// NOP (e.g. "sxtx" sign-extending a 64-bit register to 64-bits) but 227249259Sdim// must be specified with one exception: 228249259Sdim 229249259Sdim// If one of the registers is sp/wsp then LSL is an alias for UXTW in 230249259Sdim// 32-bit instructions and UXTX in 64-bit versions, the shift amount 231249259Sdim// is not optional in that case (but can explicitly be 0), and the 232249259Sdim// entire suffix can be skipped (e.g. "add sp, x3, x2"). 233249259Sdim 234249259Sdimmulticlass extend_operands<string PREFIX, string Diag> { 235249259Sdim def _asmoperand : AsmOperandClass { 236249259Sdim let Name = PREFIX; 237249259Sdim let RenderMethod = "addRegExtendOperands"; 238249259Sdim let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">"; 239249259Sdim let DiagnosticType = "AddSubRegExtend" # Diag; 240249259Sdim } 241249259Sdim 242249259Sdim def _operand : Operand<i64>, 243249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> { 244249259Sdim let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">"; 245249259Sdim let DecoderMethod = "DecodeRegExtendOperand"; 246249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand"); 247249259Sdim } 248249259Sdim} 249249259Sdim 250249259Sdimdefm UXTB : extend_operands<"UXTB", "Small">; 251249259Sdimdefm UXTH : extend_operands<"UXTH", "Small">; 252249259Sdimdefm UXTW : extend_operands<"UXTW", "Small">; 253249259Sdimdefm UXTX : extend_operands<"UXTX", "Large">; 254249259Sdimdefm SXTB : extend_operands<"SXTB", "Small">; 255249259Sdimdefm SXTH : extend_operands<"SXTH", "Small">; 256249259Sdimdefm SXTW : extend_operands<"SXTW", "Small">; 257249259Sdimdefm SXTX : extend_operands<"SXTX", "Large">; 258249259Sdim 259249259Sdimdef LSL_extasmoperand : AsmOperandClass { 260249259Sdim let Name = "RegExtendLSL"; 261249259Sdim let RenderMethod = "addRegExtendOperands"; 262249259Sdim let DiagnosticType = "AddSubRegExtendLarge"; 263249259Sdim} 264249259Sdim 265249259Sdimdef LSL_extoperand : Operand<i64> { 266249259Sdim let ParserMatchClass = LSL_extasmoperand; 267249259Sdim} 268249259Sdim 269249259Sdim 270249259Sdim// The patterns for various sign-extensions are a little ugly and 271249259Sdim// non-uniform because everything has already been promoted to the 272249259Sdim// legal i64 and i32 types. We'll wrap the various variants up in a 273249259Sdim// class for use later. 274249259Sdimclass extend_types { 275249259Sdim dag uxtb; dag uxth; dag uxtw; dag uxtx; 276249259Sdim dag sxtb; dag sxth; dag sxtw; dag sxtx; 277249259Sdim ValueType ty; 278249259Sdim RegisterClass GPR; 279249259Sdim} 280249259Sdim 281249259Sdimdef extends_to_i64 : extend_types { 282249259Sdim let uxtb = (and (anyext i32:$Rm), 255); 283249259Sdim let uxth = (and (anyext i32:$Rm), 65535); 284249259Sdim let uxtw = (zext i32:$Rm); 285249259Sdim let uxtx = (i64 $Rm); 286249259Sdim 287249259Sdim let sxtb = (sext_inreg (anyext i32:$Rm), i8); 288249259Sdim let sxth = (sext_inreg (anyext i32:$Rm), i16); 289249259Sdim let sxtw = (sext i32:$Rm); 290249259Sdim let sxtx = (i64 $Rm); 291249259Sdim 292249259Sdim let ty = i64; 293249259Sdim let GPR = GPR64xsp; 294249259Sdim} 295249259Sdim 296249259Sdim 297249259Sdimdef extends_to_i32 : extend_types { 298249259Sdim let uxtb = (and i32:$Rm, 255); 299249259Sdim let uxth = (and i32:$Rm, 65535); 300249259Sdim let uxtw = (i32 i32:$Rm); 301249259Sdim let uxtx = (i32 i32:$Rm); 302249259Sdim 303249259Sdim let sxtb = (sext_inreg i32:$Rm, i8); 304249259Sdim let sxth = (sext_inreg i32:$Rm, i16); 305249259Sdim let sxtw = (i32 i32:$Rm); 306249259Sdim let sxtx = (i32 i32:$Rm); 307249259Sdim 308249259Sdim let ty = i32; 309249259Sdim let GPR = GPR32wsp; 310249259Sdim} 311249259Sdim 312249259Sdim// Now, six of the extensions supported are easy and uniform: if the source size 313249259Sdim// is 32-bits or less, then Rm is always a 32-bit register. We'll instantiate 314249259Sdim// those instructions in one block. 315249259Sdim 316249259Sdim// The uxtx/sxtx could potentially be merged in, but three facts dissuaded me: 317249259Sdim// + It would break the naming scheme: either ADDxx_uxtx or ADDww_uxtx would 318249259Sdim// be impossible. 319249259Sdim// + Patterns are very different as well. 320249259Sdim// + Passing different registers would be ugly (more fields in extend_types 321249259Sdim// would probably be the best option). 322249259Sdimmulticlass addsub_exts<bit sf, bit op, bit S, string asmop, 323249259Sdim SDPatternOperator opfrag, 324249259Sdim dag outs, extend_types exts> { 325249259Sdim def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000, 326249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3), 327249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 328249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))], 329249259Sdim NoItinerary>; 330249259Sdim def w_uxth : A64I_addsubext<sf, op, S, 0b00, 0b001, 331249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3), 332249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 333249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))], 334249259Sdim NoItinerary>; 335249259Sdim def w_uxtw : A64I_addsubext<sf, op, S, 0b00, 0b010, 336249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3), 337249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 338249259Sdim [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))], 339249259Sdim NoItinerary>; 340249259Sdim 341249259Sdim def w_sxtb : A64I_addsubext<sf, op, S, 0b00, 0b100, 342249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3), 343249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 344249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))], 345249259Sdim NoItinerary>; 346249259Sdim def w_sxth : A64I_addsubext<sf, op, S, 0b00, 0b101, 347249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3), 348249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 349249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))], 350249259Sdim NoItinerary>; 351249259Sdim def w_sxtw : A64I_addsubext<sf, op, S, 0b00, 0b110, 352249259Sdim outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3), 353249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 354249259Sdim [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))], 355249259Sdim NoItinerary>; 356249259Sdim} 357249259Sdim 358249259Sdim// These two could be merge in with the above, but their patterns aren't really 359249259Sdim// necessary and the naming-scheme would necessarily break: 360249259Sdimmulticlass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, 361249259Sdim dag outs> { 362249259Sdim def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011, 363249259Sdim outs, 364249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3), 365249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 366249259Sdim [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))], 367249259Sdim NoItinerary>; 368249259Sdim 369249259Sdim def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111, 370249259Sdim outs, 371249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3), 372249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 373249259Sdim [/* No Pattern: same as uxtx */], 374249259Sdim NoItinerary>; 375249259Sdim} 376249259Sdim 377249259Sdimmulticlass addsub_wxtx<bit op, bit S, string asmop, dag outs> { 378249259Sdim def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011, 379249259Sdim outs, 380249259Sdim (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3), 381249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 382249259Sdim [/* No pattern: probably same as uxtw */], 383249259Sdim NoItinerary>; 384249259Sdim 385249259Sdim def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111, 386249259Sdim outs, 387249259Sdim (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3), 388249259Sdim !strconcat(asmop, "$Rn, $Rm, $Imm3"), 389249259Sdim [/* No Pattern: probably same as uxtw */], 390249259Sdim NoItinerary>; 391249259Sdim} 392249259Sdim 393249259Sdimclass SetRD<RegisterClass RC, SDPatternOperator op> 394249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), (set RC:$Rd, (op node:$lhs, node:$rhs))>; 395249259Sdimclass SetNZCV<SDPatternOperator op> 396249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), (set NZCV, (op node:$lhs, node:$rhs))>; 397249259Sdim 398249259Sdimdefm ADDxx :addsub_exts<0b1, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 399249259Sdim (outs GPR64xsp:$Rd), extends_to_i64>, 400249259Sdim addsub_xxtx< 0b0, 0b0, "add\t$Rd, ", SetRD<GPR64xsp, add>, 401249259Sdim (outs GPR64xsp:$Rd)>; 402249259Sdimdefm ADDww :addsub_exts<0b0, 0b0, 0b0, "add\t$Rd, ", SetRD<GPR32wsp, add>, 403249259Sdim (outs GPR32wsp:$Rd), extends_to_i32>, 404249259Sdim addsub_wxtx< 0b0, 0b0, "add\t$Rd, ", 405249259Sdim (outs GPR32wsp:$Rd)>; 406249259Sdimdefm SUBxx :addsub_exts<0b1, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 407249259Sdim (outs GPR64xsp:$Rd), extends_to_i64>, 408249259Sdim addsub_xxtx< 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR64xsp, sub>, 409249259Sdim (outs GPR64xsp:$Rd)>; 410249259Sdimdefm SUBww :addsub_exts<0b0, 0b1, 0b0, "sub\t$Rd, ", SetRD<GPR32wsp, sub>, 411249259Sdim (outs GPR32wsp:$Rd), extends_to_i32>, 412249259Sdim addsub_wxtx< 0b1, 0b0, "sub\t$Rd, ", 413249259Sdim (outs GPR32wsp:$Rd)>; 414249259Sdim 415249259Sdimlet Defs = [NZCV] in { 416249259Sdimdefm ADDSxx :addsub_exts<0b1, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 417249259Sdim (outs GPR64:$Rd), extends_to_i64>, 418249259Sdim addsub_xxtx< 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR64, addc>, 419249259Sdim (outs GPR64:$Rd)>; 420249259Sdimdefm ADDSww :addsub_exts<0b0, 0b0, 0b1, "adds\t$Rd, ", SetRD<GPR32, addc>, 421249259Sdim (outs GPR32:$Rd), extends_to_i32>, 422249259Sdim addsub_wxtx< 0b0, 0b1, "adds\t$Rd, ", 423249259Sdim (outs GPR32:$Rd)>; 424249259Sdimdefm SUBSxx :addsub_exts<0b1, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 425249259Sdim (outs GPR64:$Rd), extends_to_i64>, 426249259Sdim addsub_xxtx< 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR64, subc>, 427249259Sdim (outs GPR64:$Rd)>; 428249259Sdimdefm SUBSww :addsub_exts<0b0, 0b1, 0b1, "subs\t$Rd, ", SetRD<GPR32, subc>, 429249259Sdim (outs GPR32:$Rd), extends_to_i32>, 430249259Sdim addsub_wxtx< 0b1, 0b1, "subs\t$Rd, ", 431249259Sdim (outs GPR32:$Rd)>; 432249259Sdim 433249259Sdim 434249259Sdimlet Rd = 0b11111, isCompare = 1 in { 435249259Sdimdefm CMNx : addsub_exts<0b1, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 436249259Sdim (outs), extends_to_i64>, 437249259Sdim addsub_xxtx< 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, (outs)>; 438249259Sdimdefm CMNw : addsub_exts<0b0, 0b0, 0b1, "cmn\t", SetNZCV<A64cmn>, 439249259Sdim (outs), extends_to_i32>, 440249259Sdim addsub_wxtx< 0b0, 0b1, "cmn\t", (outs)>; 441249259Sdimdefm CMPx : addsub_exts<0b1, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 442249259Sdim (outs), extends_to_i64>, 443249259Sdim addsub_xxtx< 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, (outs)>; 444249259Sdimdefm CMPw : addsub_exts<0b0, 0b1, 0b1, "cmp\t", SetNZCV<A64cmp>, 445249259Sdim (outs), extends_to_i32>, 446249259Sdim addsub_wxtx< 0b1, 0b1, "cmp\t", (outs)>; 447249259Sdim} 448249259Sdim} 449249259Sdim 450249259Sdim// Now patterns for the operation without a shift being needed. No patterns are 451249259Sdim// created for uxtx/sxtx since they're non-uniform and it's expected that 452249259Sdim// add/sub (shifted register) will handle those cases anyway. 453249259Sdimmulticlass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop, 454249259Sdim extend_types exts> { 455249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxtb), 456249259Sdim (!cast<Instruction>(prefix # "w_uxtb") $Rn, $Rm, 0)>; 457249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxth), 458249259Sdim (!cast<Instruction>(prefix # "w_uxth") $Rn, $Rm, 0)>; 459249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.uxtw), 460249259Sdim (!cast<Instruction>(prefix # "w_uxtw") $Rn, $Rm, 0)>; 461249259Sdim 462249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxtb), 463249259Sdim (!cast<Instruction>(prefix # "w_sxtb") $Rn, $Rm, 0)>; 464249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxth), 465249259Sdim (!cast<Instruction>(prefix # "w_sxth") $Rn, $Rm, 0)>; 466249259Sdim def : Pat<(nodeop exts.ty:$Rn, exts.sxtw), 467249259Sdim (!cast<Instruction>(prefix # "w_sxtw") $Rn, $Rm, 0)>; 468249259Sdim} 469249259Sdim 470249259Sdimdefm : addsubext_noshift_patterns<"ADDxx", add, extends_to_i64>; 471249259Sdimdefm : addsubext_noshift_patterns<"ADDww", add, extends_to_i32>; 472249259Sdimdefm : addsubext_noshift_patterns<"SUBxx", sub, extends_to_i64>; 473249259Sdimdefm : addsubext_noshift_patterns<"SUBww", sub, extends_to_i32>; 474249259Sdim 475249259Sdimdefm : addsubext_noshift_patterns<"CMNx", A64cmn, extends_to_i64>; 476249259Sdimdefm : addsubext_noshift_patterns<"CMNw", A64cmn, extends_to_i32>; 477249259Sdimdefm : addsubext_noshift_patterns<"CMPx", A64cmp, extends_to_i64>; 478249259Sdimdefm : addsubext_noshift_patterns<"CMPw", A64cmp, extends_to_i32>; 479249259Sdim 480249259Sdim// An extend of "lsl #imm" is valid if and only if one of Rn and Rd is 481249259Sdim// sp/wsp. It is synonymous with uxtx/uxtw depending on the size of the 482249259Sdim// operation. Also permitted in this case is complete omission of the argument, 483249259Sdim// which implies "lsl #0". 484249259Sdimmulticlass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd, 485249259Sdim RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 486249259Sdim def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 487249259Sdim (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 488249259Sdim 489249259Sdim def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm, $LSL"), 490249259Sdim (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 491249259Sdim 492249259Sdim} 493249259Sdim 494249259Sdimdefm : lsl_aliases<"add", ADDxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 495249259Sdimdefm : lsl_aliases<"add", ADDxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 496249259Sdimdefm : lsl_aliases<"add", ADDwww_uxtw, Rwsp, GPR32wsp, GPR32>; 497249259Sdimdefm : lsl_aliases<"add", ADDwww_uxtw, GPR32wsp, Rwsp, GPR32>; 498249259Sdimdefm : lsl_aliases<"sub", SUBxxx_uxtx, Rxsp, GPR64xsp, GPR64>; 499249259Sdimdefm : lsl_aliases<"sub", SUBxxx_uxtx, GPR64xsp, Rxsp, GPR64>; 500249259Sdimdefm : lsl_aliases<"sub", SUBwww_uxtw, Rwsp, GPR32wsp, GPR32>; 501249259Sdimdefm : lsl_aliases<"sub", SUBwww_uxtw, GPR32wsp, Rwsp, GPR32>; 502249259Sdim 503249259Sdim// Rd cannot be sp for flag-setting variants so only half of the aliases are 504249259Sdim// needed. 505249259Sdimdefm : lsl_aliases<"adds", ADDSxxx_uxtx, GPR64, Rxsp, GPR64>; 506249259Sdimdefm : lsl_aliases<"adds", ADDSwww_uxtw, GPR32, Rwsp, GPR32>; 507249259Sdimdefm : lsl_aliases<"subs", SUBSxxx_uxtx, GPR64, Rxsp, GPR64>; 508249259Sdimdefm : lsl_aliases<"subs", SUBSwww_uxtw, GPR32, Rwsp, GPR32>; 509249259Sdim 510249259Sdim// CMP unfortunately has to be different because the instruction doesn't have a 511249259Sdim// dest register. 512249259Sdimmulticlass cmp_lsl_aliases<string asmop, Instruction inst, 513249259Sdim RegisterClass GPR_Rn, RegisterClass GPR_Rm> { 514249259Sdim def : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 515249259Sdim (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>; 516249259Sdim 517249259Sdim def : InstAlias<!strconcat(asmop, " $Rn, $Rm, $LSL"), 518249259Sdim (inst GPR_Rn:$Rn, GPR_Rm:$Rm, LSL_extoperand:$LSL)>; 519249259Sdim} 520249259Sdim 521249259Sdimdefm : cmp_lsl_aliases<"cmp", CMPxx_uxtx, Rxsp, GPR64>; 522249259Sdimdefm : cmp_lsl_aliases<"cmp", CMPww_uxtw, Rwsp, GPR32>; 523249259Sdimdefm : cmp_lsl_aliases<"cmn", CMNxx_uxtx, Rxsp, GPR64>; 524249259Sdimdefm : cmp_lsl_aliases<"cmn", CMNww_uxtw, Rwsp, GPR32>; 525249259Sdim 526249259Sdim//===----------------------------------------------------------------------===// 527249259Sdim// Add-subtract (immediate) instructions 528249259Sdim//===----------------------------------------------------------------------===// 529249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, MOV 530249259Sdim 531249259Sdim// These instructions accept a 12-bit unsigned immediate, optionally shifted 532249259Sdim// left by 12 bits. Official assembly format specifies a 12 bit immediate with 533249259Sdim// one of "", "LSL #0", "LSL #12" supplementary operands. 534249259Sdim 535249259Sdim// There are surprisingly few ways to make this work with TableGen, so this 536249259Sdim// implementation has separate instructions for the "LSL #0" and "LSL #12" 537249259Sdim// variants. 538249259Sdim 539249259Sdim// If the MCInst retained a single combined immediate (which could be 0x123000, 540249259Sdim// for example) then both components (imm & shift) would have to be delegated to 541249259Sdim// a single assembly operand. This would entail a separate operand parser 542249259Sdim// (because the LSL would have to live in the same AArch64Operand as the 543249259Sdim// immediate to be accessible); assembly parsing is rather complex and 544249259Sdim// error-prone C++ code. 545249259Sdim// 546249259Sdim// By splitting the immediate, we can delegate handling this optional operand to 547249259Sdim// an InstAlias. Supporting functions to generate the correct MCInst are still 548249259Sdim// required, but these are essentially trivial and parsing can remain generic. 549249259Sdim// 550249259Sdim// Rejected plans with rationale: 551249259Sdim// ------------------------------ 552249259Sdim// 553249259Sdim// In an ideal world you'de have two first class immediate operands (in 554249259Sdim// InOperandList, specifying imm12 and shift). Unfortunately this is not 555249259Sdim// selectable by any means I could discover. 556249259Sdim// 557249259Sdim// An Instruction with two MCOperands hidden behind a single entry in 558249259Sdim// InOperandList (expanded by ComplexPatterns and MIOperandInfo) was functional, 559249259Sdim// but required more C++ code to handle encoding/decoding. Parsing (the intended 560249259Sdim// main beneficiary) ended up equally complex because of the optional nature of 561249259Sdim// "LSL #0". 562249259Sdim// 563249259Sdim// Attempting to circumvent the need for a custom OperandParser above by giving 564249259Sdim// InstAliases without the "lsl #0" failed. add/sub could be accommodated but 565249259Sdim// the cmp/cmn aliases didn't use the MIOperandInfo to determine how operands 566249259Sdim// should be parsed: there was no way to accommodate an "lsl #12". 567249259Sdim 568249259Sdimlet ParserMethod = "ParseImmWithLSLOperand", 569249259Sdim RenderMethod = "addImmWithLSLOperands" in { 570249259Sdim // Derived PredicateMethod fields are different for each 571249259Sdim def addsubimm_lsl0_asmoperand : AsmOperandClass { 572249259Sdim let Name = "AddSubImmLSL0"; 573249259Sdim // If an error is reported against this operand, instruction could also be a 574249259Sdim // register variant. 575249259Sdim let DiagnosticType = "AddSubSecondSource"; 576249259Sdim } 577249259Sdim 578249259Sdim def addsubimm_lsl12_asmoperand : AsmOperandClass { 579249259Sdim let Name = "AddSubImmLSL12"; 580249259Sdim let DiagnosticType = "AddSubSecondSource"; 581249259Sdim } 582249259Sdim} 583249259Sdim 584249259Sdimdef shr_12_XFORM : SDNodeXForm<imm, [{ 585249259Sdim return CurDAG->getTargetConstant(N->getSExtValue() >> 12, MVT::i32); 586249259Sdim}]>; 587249259Sdim 588249259Sdimdef shr_12_neg_XFORM : SDNodeXForm<imm, [{ 589249259Sdim return CurDAG->getTargetConstant((-N->getSExtValue()) >> 12, MVT::i32); 590249259Sdim}]>; 591249259Sdim 592249259Sdimdef neg_XFORM : SDNodeXForm<imm, [{ 593249259Sdim return CurDAG->getTargetConstant(-N->getSExtValue(), MVT::i32); 594249259Sdim}]>; 595249259Sdim 596249259Sdim 597249259Sdimmulticlass addsub_imm_operands<ValueType ty> { 598249259Sdim let PrintMethod = "printAddSubImmLSL0Operand", 599249259Sdim EncoderMethod = "getAddSubImmOpValue", 600249259Sdim ParserMatchClass = addsubimm_lsl0_asmoperand in { 601249259Sdim def _posimm_lsl0 : Operand<ty>, 602249259Sdim ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>; 603249259Sdim def _negimm_lsl0 : Operand<ty>, 604249259Sdim ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff) == 0; }], 605249259Sdim neg_XFORM>; 606249259Sdim } 607249259Sdim 608249259Sdim let PrintMethod = "printAddSubImmLSL12Operand", 609249259Sdim EncoderMethod = "getAddSubImmOpValue", 610249259Sdim ParserMatchClass = addsubimm_lsl12_asmoperand in { 611249259Sdim def _posimm_lsl12 : Operand<ty>, 612249259Sdim ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }], 613249259Sdim shr_12_XFORM>; 614249259Sdim 615249259Sdim def _negimm_lsl12 : Operand<ty>, 616249259Sdim ImmLeaf<ty, [{ return Imm < 0 && (-Imm & ~0xfff000) == 0; }], 617249259Sdim shr_12_neg_XFORM>; 618249259Sdim } 619249259Sdim} 620249259Sdim 621249259Sdim// The add operands don't need any transformation 622249259Sdimdefm addsubimm_operand_i32 : addsub_imm_operands<i32>; 623249259Sdimdefm addsubimm_operand_i64 : addsub_imm_operands<i64>; 624249259Sdim 625249259Sdimmulticlass addsubimm_varieties<string prefix, bit sf, bit op, bits<2> shift, 626249259Sdim string asmop, string cmpasmop, 627249259Sdim Operand imm_operand, Operand cmp_imm_operand, 628249259Sdim RegisterClass GPR, RegisterClass GPRsp, 629249259Sdim AArch64Reg ZR, ValueType Ty> { 630249259Sdim // All registers for non-S variants allow SP 631249259Sdim def _s : A64I_addsubimm<sf, op, 0b0, shift, 632249259Sdim (outs GPRsp:$Rd), 633249259Sdim (ins GPRsp:$Rn, imm_operand:$Imm12), 634249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm12"), 635249259Sdim [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))], 636249259Sdim NoItinerary>; 637249259Sdim 638249259Sdim 639249259Sdim // S variants can read SP but would write to ZR 640249259Sdim def _S : A64I_addsubimm<sf, op, 0b1, shift, 641249259Sdim (outs GPR:$Rd), 642249259Sdim (ins GPRsp:$Rn, imm_operand:$Imm12), 643249259Sdim !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"), 644249259Sdim [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))], 645249259Sdim NoItinerary> { 646249259Sdim let Defs = [NZCV]; 647249259Sdim } 648249259Sdim 649249259Sdim // Note that the pattern here for ADDS is subtle. Canonically CMP 650249259Sdim // a, b becomes SUBS a, b. If b < 0 then this is equivalent to 651249259Sdim // ADDS a, (-b). This is not true in general. 652249259Sdim def _cmp : A64I_addsubimm<sf, op, 0b1, shift, 653249259Sdim (outs), (ins GPRsp:$Rn, imm_operand:$Imm12), 654249259Sdim !strconcat(cmpasmop, " $Rn, $Imm12"), 655249259Sdim [(set NZCV, 656249259Sdim (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))], 657249259Sdim NoItinerary> { 658249259Sdim let Rd = 0b11111; 659249259Sdim let Defs = [NZCV]; 660249259Sdim let isCompare = 1; 661249259Sdim } 662249259Sdim} 663249259Sdim 664249259Sdim 665249259Sdimmulticlass addsubimm_shifts<string prefix, bit sf, bit op, 666249259Sdim string asmop, string cmpasmop, string operand, string cmpoperand, 667249259Sdim RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR, 668249259Sdim ValueType Ty> { 669249259Sdim defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00, 670249259Sdim asmop, cmpasmop, 671249259Sdim !cast<Operand>(operand # "_lsl0"), 672249259Sdim !cast<Operand>(cmpoperand # "_lsl0"), 673249259Sdim GPR, GPRsp, ZR, Ty>; 674249259Sdim 675249259Sdim defm _lsl12 : addsubimm_varieties<prefix # "_lsl12", sf, op, 0b01, 676249259Sdim asmop, cmpasmop, 677249259Sdim !cast<Operand>(operand # "_lsl12"), 678249259Sdim !cast<Operand>(cmpoperand # "_lsl12"), 679249259Sdim GPR, GPRsp, ZR, Ty>; 680249259Sdim} 681249259Sdim 682249259Sdimdefm ADDwwi : addsubimm_shifts<"ADDwi", 0b0, 0b0, "add", "cmn", 683249259Sdim "addsubimm_operand_i32_posimm", 684249259Sdim "addsubimm_operand_i32_negimm", 685249259Sdim GPR32, GPR32wsp, WZR, i32>; 686249259Sdimdefm ADDxxi : addsubimm_shifts<"ADDxi", 0b1, 0b0, "add", "cmn", 687249259Sdim "addsubimm_operand_i64_posimm", 688249259Sdim "addsubimm_operand_i64_negimm", 689249259Sdim GPR64, GPR64xsp, XZR, i64>; 690249259Sdimdefm SUBwwi : addsubimm_shifts<"SUBwi", 0b0, 0b1, "sub", "cmp", 691249259Sdim "addsubimm_operand_i32_negimm", 692249259Sdim "addsubimm_operand_i32_posimm", 693249259Sdim GPR32, GPR32wsp, WZR, i32>; 694249259Sdimdefm SUBxxi : addsubimm_shifts<"SUBxi", 0b1, 0b1, "sub", "cmp", 695249259Sdim "addsubimm_operand_i64_negimm", 696249259Sdim "addsubimm_operand_i64_posimm", 697249259Sdim GPR64, GPR64xsp, XZR, i64>; 698249259Sdim 699249259Sdimmulticlass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> { 700249259Sdim def _fromsp : InstAlias<"mov $Rd, $Rn", 701249259Sdim (addop GPRsp:$Rd, SP:$Rn, 0), 702249259Sdim 0b1>; 703249259Sdim 704249259Sdim def _tosp : InstAlias<"mov $Rd, $Rn", 705249259Sdim (addop SP:$Rd, GPRsp:$Rn, 0), 706249259Sdim 0b1>; 707249259Sdim} 708249259Sdim 709249259Sdim// Recall Rxsp is a RegisterClass containing *just* xsp. 710249259Sdimdefm MOVxx : MOVsp<GPR64xsp, Rxsp, ADDxxi_lsl0_s>; 711249259Sdimdefm MOVww : MOVsp<GPR32wsp, Rwsp, ADDwwi_lsl0_s>; 712249259Sdim 713249259Sdim//===----------------------------------------------------------------------===// 714249259Sdim// Add-subtract (shifted register) instructions 715249259Sdim//===----------------------------------------------------------------------===// 716249259Sdim// Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS 717249259Sdim 718249259Sdim//===------------------------------- 719249259Sdim// 1. The "shifed register" operands. Shared with logical insts. 720249259Sdim//===------------------------------- 721249259Sdim 722249259Sdimmulticlass shift_operands<string prefix, string form> { 723249259Sdim def _asmoperand_i32 : AsmOperandClass { 724249259Sdim let Name = "Shift" # form # "i32"; 725249259Sdim let RenderMethod = "addShiftOperands"; 726249259Sdim let PredicateMethod = "isShift<A64SE::" # form # ", false>"; 727249259Sdim let DiagnosticType = "AddSubRegShift32"; 728249259Sdim } 729249259Sdim 730249259Sdim // Note that the operand type is intentionally i64 because the DAGCombiner 731249259Sdim // puts these into a canonical form. 732249259Sdim def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 733249259Sdim let ParserMatchClass 734249259Sdim = !cast<AsmOperandClass>(prefix # "_asmoperand_i32"); 735249259Sdim let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 736249259Sdim let DecoderMethod = "Decode32BitShiftOperand"; 737249259Sdim } 738249259Sdim 739249259Sdim def _asmoperand_i64 : AsmOperandClass { 740249259Sdim let Name = "Shift" # form # "i64"; 741249259Sdim let RenderMethod = "addShiftOperands"; 742249259Sdim let PredicateMethod = "isShift<A64SE::" # form # ", true>"; 743249259Sdim let DiagnosticType = "AddSubRegShift64"; 744249259Sdim } 745249259Sdim 746249259Sdim def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 747249259Sdim let ParserMatchClass 748249259Sdim = !cast<AsmOperandClass>(prefix # "_asmoperand_i64"); 749249259Sdim let PrintMethod = "printShiftOperand<A64SE::" # form # ">"; 750249259Sdim } 751249259Sdim} 752249259Sdim 753249259Sdimdefm lsl_operand : shift_operands<"lsl_operand", "LSL">; 754249259Sdimdefm lsr_operand : shift_operands<"lsr_operand", "LSR">; 755249259Sdimdefm asr_operand : shift_operands<"asr_operand", "ASR">; 756249259Sdim 757249259Sdim// Not used for add/sub, but defined here for completeness. The "logical 758249259Sdim// (shifted register)" instructions *do* have an ROR variant. 759249259Sdimdefm ror_operand : shift_operands<"ror_operand", "ROR">; 760249259Sdim 761249259Sdim//===------------------------------- 762249259Sdim// 2. The basic 3.5-operand ADD/SUB/ADDS/SUBS instructions. 763249259Sdim//===------------------------------- 764249259Sdim 765249259Sdim// N.b. the commutable parameter is just !N. It will be first against the wall 766249259Sdim// when the revolution comes. 767249259Sdimmulticlass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable, 768249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 769249259Sdim RegisterClass GPR, list<Register> defs> { 770249259Sdim let isCommutable = commutable, Defs = defs in { 771249259Sdim def _lsl : A64I_addsubshift<sf, op, s, 0b00, 772249259Sdim (outs GPR:$Rd), 773249259Sdim (ins GPR:$Rn, GPR:$Rm, 774249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 775249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 776249259Sdim [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 777249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 778249259Sdim )], 779249259Sdim NoItinerary>; 780249259Sdim 781249259Sdim def _lsr : A64I_addsubshift<sf, op, s, 0b01, 782249259Sdim (outs GPR:$Rd), 783249259Sdim (ins GPR:$Rn, GPR:$Rm, 784249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 785249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 786249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 787249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 788249259Sdim )], 789249259Sdim NoItinerary>; 790249259Sdim 791249259Sdim def _asr : A64I_addsubshift<sf, op, s, 0b10, 792249259Sdim (outs GPR:$Rd), 793249259Sdim (ins GPR:$Rn, GPR:$Rm, 794249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 795249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 796249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 797249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 798249259Sdim )], 799249259Sdim NoItinerary>; 800249259Sdim } 801249259Sdim 802249259Sdim def _noshift 803249259Sdim : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 804249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 805249259Sdim GPR:$Rm, 0)>; 806249259Sdim 807249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 808249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 809249259Sdim} 810249259Sdim 811249259Sdimmulticlass addsub_sizes<string prefix, bit op, bit s, bit commutable, 812249259Sdim string asmop, SDPatternOperator opfrag, 813249259Sdim list<Register> defs> { 814249259Sdim defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s, 815249259Sdim commutable, asmop, opfrag, i64, GPR64, defs>; 816249259Sdim defm www : addsub_shifts<prefix # "www", 0b0, op, s, 817249259Sdim commutable, asmop, opfrag, i32, GPR32, defs>; 818249259Sdim} 819249259Sdim 820249259Sdim 821249259Sdimdefm ADD : addsub_sizes<"ADD", 0b0, 0b0, 0b1, "add", add, []>; 822249259Sdimdefm SUB : addsub_sizes<"SUB", 0b1, 0b0, 0b0, "sub", sub, []>; 823249259Sdim 824249259Sdimdefm ADDS : addsub_sizes<"ADDS", 0b0, 0b1, 0b1, "adds", addc, [NZCV]>; 825249259Sdimdefm SUBS : addsub_sizes<"SUBS", 0b1, 0b1, 0b0, "subs", subc, [NZCV]>; 826249259Sdim 827249259Sdim//===------------------------------- 828249259Sdim// 1. The NEG/NEGS aliases 829249259Sdim//===------------------------------- 830249259Sdim 831249259Sdimmulticlass neg_alias<Instruction INST, RegisterClass GPR, Register ZR, 832249259Sdim ValueType ty, Operand shift_operand, SDNode shiftop> { 833249259Sdim def : InstAlias<"neg $Rd, $Rm, $Imm6", 834249259Sdim (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 835249259Sdim 836249259Sdim def : Pat<(sub 0, (shiftop ty:$Rm, shift_operand:$Imm6)), 837249259Sdim (INST ZR, $Rm, shift_operand:$Imm6)>; 838249259Sdim} 839249259Sdim 840249259Sdimdefm : neg_alias<SUBwww_lsl, GPR32, WZR, i32, lsl_operand_i32, shl>; 841249259Sdimdefm : neg_alias<SUBwww_lsr, GPR32, WZR, i32, lsr_operand_i32, srl>; 842249259Sdimdefm : neg_alias<SUBwww_asr, GPR32, WZR, i32, asr_operand_i32, sra>; 843249259Sdimdef : InstAlias<"neg $Rd, $Rm", (SUBwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 844249259Sdimdef : Pat<(sub 0, i32:$Rm), (SUBwww_lsl WZR, $Rm, 0)>; 845249259Sdim 846249259Sdimdefm : neg_alias<SUBxxx_lsl, GPR64, XZR, i64, lsl_operand_i64, shl>; 847249259Sdimdefm : neg_alias<SUBxxx_lsr, GPR64, XZR, i64, lsr_operand_i64, srl>; 848249259Sdimdefm : neg_alias<SUBxxx_asr, GPR64, XZR, i64, asr_operand_i64, sra>; 849249259Sdimdef : InstAlias<"neg $Rd, $Rm", (SUBxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 850249259Sdimdef : Pat<(sub 0, i64:$Rm), (SUBxxx_lsl XZR, $Rm, 0)>; 851249259Sdim 852249259Sdim// NEGS doesn't get any patterns yet: defining multiple outputs means C++ has to 853249259Sdim// be involved. 854249259Sdimclass negs_alias<Instruction INST, RegisterClass GPR, 855249259Sdim Register ZR, Operand shift_operand, SDNode shiftop> 856249259Sdim : InstAlias<"negs $Rd, $Rm, $Imm6", 857249259Sdim (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>; 858249259Sdim 859249259Sdimdef : negs_alias<SUBSwww_lsl, GPR32, WZR, lsl_operand_i32, shl>; 860249259Sdimdef : negs_alias<SUBSwww_lsr, GPR32, WZR, lsr_operand_i32, srl>; 861249259Sdimdef : negs_alias<SUBSwww_asr, GPR32, WZR, asr_operand_i32, sra>; 862249259Sdimdef : InstAlias<"negs $Rd, $Rm", (SUBSwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 863249259Sdim 864249259Sdimdef : negs_alias<SUBSxxx_lsl, GPR64, XZR, lsl_operand_i64, shl>; 865249259Sdimdef : negs_alias<SUBSxxx_lsr, GPR64, XZR, lsr_operand_i64, srl>; 866249259Sdimdef : negs_alias<SUBSxxx_asr, GPR64, XZR, asr_operand_i64, sra>; 867249259Sdimdef : InstAlias<"negs $Rd, $Rm", (SUBSxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 868249259Sdim 869249259Sdim//===------------------------------- 870249259Sdim// 1. The CMP/CMN aliases 871249259Sdim//===------------------------------- 872249259Sdim 873249259Sdimmulticlass cmp_shifts<string prefix, bit sf, bit op, bit commutable, 874249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 875249259Sdim RegisterClass GPR> { 876249259Sdim let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in { 877249259Sdim def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00, 878249259Sdim (outs), 879249259Sdim (ins GPR:$Rn, GPR:$Rm, 880249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 881249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 882249259Sdim [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm, 883249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 884249259Sdim )], 885249259Sdim NoItinerary>; 886249259Sdim 887249259Sdim def _lsr : A64I_addsubshift<sf, op, 0b1, 0b01, 888249259Sdim (outs), 889249259Sdim (ins GPR:$Rn, GPR:$Rm, 890249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 891249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 892249259Sdim [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm, 893249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 894249259Sdim )], 895249259Sdim NoItinerary>; 896249259Sdim 897249259Sdim def _asr : A64I_addsubshift<sf, op, 0b1, 0b10, 898249259Sdim (outs), 899249259Sdim (ins GPR:$Rn, GPR:$Rm, 900249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 901249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $Imm6"), 902249259Sdim [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm, 903249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 904249259Sdim )], 905249259Sdim NoItinerary>; 906249259Sdim } 907249259Sdim 908249259Sdim def _noshift 909249259Sdim : InstAlias<!strconcat(asmop, " $Rn, $Rm"), 910249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 911249259Sdim 912249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 913249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 914249259Sdim} 915249259Sdim 916249259Sdimdefm CMPww : cmp_shifts<"CMPww", 0b0, 0b1, 0b0, "cmp", A64cmp, i32, GPR32>; 917249259Sdimdefm CMPxx : cmp_shifts<"CMPxx", 0b1, 0b1, 0b0, "cmp", A64cmp, i64, GPR64>; 918249259Sdim 919249259Sdimdefm CMNww : cmp_shifts<"CMNww", 0b0, 0b0, 0b1, "cmn", A64cmn, i32, GPR32>; 920249259Sdimdefm CMNxx : cmp_shifts<"CMNxx", 0b1, 0b0, 0b1, "cmn", A64cmn, i64, GPR64>; 921249259Sdim 922249259Sdim//===----------------------------------------------------------------------===// 923249259Sdim// Add-subtract (with carry) instructions 924249259Sdim//===----------------------------------------------------------------------===// 925249259Sdim// Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS 926249259Sdim 927249259Sdimmulticlass A64I_addsubcarrySizes<bit op, bit s, string asmop> { 928249259Sdim let Uses = [NZCV] in { 929249259Sdim def www : A64I_addsubcarry<0b0, op, s, 0b000000, 930249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm), 931249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 932249259Sdim [], NoItinerary>; 933249259Sdim 934249259Sdim def xxx : A64I_addsubcarry<0b1, op, s, 0b000000, 935249259Sdim (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm), 936249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 937249259Sdim [], NoItinerary>; 938249259Sdim } 939249259Sdim} 940249259Sdim 941249259Sdimlet isCommutable = 1 in { 942249259Sdim defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">; 943249259Sdim} 944249259Sdim 945249259Sdimdefm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">; 946249259Sdim 947249259Sdimlet Defs = [NZCV] in { 948249259Sdim let isCommutable = 1 in { 949249259Sdim defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">; 950249259Sdim } 951249259Sdim 952249259Sdim defm SBCS : A64I_addsubcarrySizes<0b1, 0b1, "sbcs">; 953249259Sdim} 954249259Sdim 955249259Sdimdef : InstAlias<"ngc $Rd, $Rm", (SBCwww GPR32:$Rd, WZR, GPR32:$Rm)>; 956249259Sdimdef : InstAlias<"ngc $Rd, $Rm", (SBCxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 957249259Sdimdef : InstAlias<"ngcs $Rd, $Rm", (SBCSwww GPR32:$Rd, WZR, GPR32:$Rm)>; 958249259Sdimdef : InstAlias<"ngcs $Rd, $Rm", (SBCSxxx GPR64:$Rd, XZR, GPR64:$Rm)>; 959249259Sdim 960249259Sdim// Note that adde and sube can form a chain longer than two (e.g. for 256-bit 961249259Sdim// addition). So the flag-setting instructions are appropriate. 962249259Sdimdef : Pat<(adde i32:$Rn, i32:$Rm), (ADCSwww $Rn, $Rm)>; 963249259Sdimdef : Pat<(adde i64:$Rn, i64:$Rm), (ADCSxxx $Rn, $Rm)>; 964249259Sdimdef : Pat<(sube i32:$Rn, i32:$Rm), (SBCSwww $Rn, $Rm)>; 965249259Sdimdef : Pat<(sube i64:$Rn, i64:$Rm), (SBCSxxx $Rn, $Rm)>; 966249259Sdim 967249259Sdim//===----------------------------------------------------------------------===// 968249259Sdim// Bitfield 969249259Sdim//===----------------------------------------------------------------------===// 970249259Sdim// Contains: SBFM, BFM, UBFM, [SU]XT[BHW], ASR, LSR, LSL, SBFI[ZX], BFI, BFXIL, 971249259Sdim// UBFIZ, UBFX 972249259Sdim 973249259Sdim// Because of the rather complicated nearly-overlapping aliases, the decoding of 974249259Sdim// this range of instructions is handled manually. The architectural 975249259Sdim// instructions are BFM, SBFM and UBFM but a disassembler should never produce 976249259Sdim// these. 977249259Sdim// 978249259Sdim// In the end, the best option was to use BFM instructions for decoding under 979249259Sdim// almost all circumstances, but to create aliasing *Instructions* for each of 980249259Sdim// the canonical forms and specify a completely custom decoder which would 981249259Sdim// substitute the correct MCInst as needed. 982249259Sdim// 983249259Sdim// This also simplifies instruction selection, parsing etc because the MCInsts 984249259Sdim// have a shape that's closer to their use in code. 985249259Sdim 986249259Sdim//===------------------------------- 987249259Sdim// 1. The architectural BFM instructions 988249259Sdim//===------------------------------- 989249259Sdim 990249259Sdimdef uimm5_asmoperand : AsmOperandClass { 991249259Sdim let Name = "UImm5"; 992249259Sdim let PredicateMethod = "isUImm<5>"; 993249259Sdim let RenderMethod = "addImmOperands"; 994249259Sdim let DiagnosticType = "UImm5"; 995249259Sdim} 996249259Sdim 997249259Sdimdef uimm6_asmoperand : AsmOperandClass { 998249259Sdim let Name = "UImm6"; 999249259Sdim let PredicateMethod = "isUImm<6>"; 1000249259Sdim let RenderMethod = "addImmOperands"; 1001249259Sdim let DiagnosticType = "UImm6"; 1002249259Sdim} 1003249259Sdim 1004249259Sdimdef bitfield32_imm : Operand<i64>, 1005249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> { 1006249259Sdim let ParserMatchClass = uimm5_asmoperand; 1007249259Sdim 1008249259Sdim let DecoderMethod = "DecodeBitfield32ImmOperand"; 1009249259Sdim} 1010249259Sdim 1011249259Sdim 1012249259Sdimdef bitfield64_imm : Operand<i64>, 1013249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> { 1014249259Sdim let ParserMatchClass = uimm6_asmoperand; 1015249259Sdim 1016249259Sdim // Default decoder works in 64-bit case: the 6-bit field can take any value. 1017249259Sdim} 1018249259Sdim 1019249259Sdimmulticlass A64I_bitfieldSizes<bits<2> opc, string asmop> { 1020249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1021249259Sdim (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1022249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1023249259Sdim [], NoItinerary> { 1024249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1025249259Sdim } 1026249259Sdim 1027249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1028249259Sdim (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1029249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1030249259Sdim [], NoItinerary> { 1031249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1032249259Sdim } 1033249259Sdim} 1034249259Sdim 1035249259Sdimdefm SBFM : A64I_bitfieldSizes<0b00, "sbfm">; 1036249259Sdimdefm UBFM : A64I_bitfieldSizes<0b10, "ubfm">; 1037249259Sdim 1038249259Sdim// BFM instructions modify the destination register rather than defining it 1039249259Sdim// completely. 1040249259Sdimdef BFMwwii : 1041249259Sdim A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1042249259Sdim (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS), 1043249259Sdim "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1044249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1045249259Sdim let Constraints = "$src = $Rd"; 1046249259Sdim} 1047249259Sdim 1048249259Sdimdef BFMxxii : 1049249259Sdim A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1050249259Sdim (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS), 1051249259Sdim "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1052249259Sdim let DecoderMethod = "DecodeBitfieldInstruction"; 1053249259Sdim let Constraints = "$src = $Rd"; 1054249259Sdim} 1055249259Sdim 1056249259Sdim 1057249259Sdim//===------------------------------- 1058249259Sdim// 2. Extend aliases to 64-bit dest 1059249259Sdim//===------------------------------- 1060249259Sdim 1061249259Sdim// Unfortunately the extensions that end up as 64-bits cannot be handled by an 1062249259Sdim// instruction alias: their syntax is (for example) "SXTB x0, w0", which needs 1063249259Sdim// to be mapped to "SBFM x0, x0, #0, 7" (changing the class of Rn). InstAlias is 1064249259Sdim// not capable of such a map as far as I'm aware 1065249259Sdim 1066249259Sdim// Note that these instructions are strictly more specific than the 1067249259Sdim// BFM ones (in ImmR) so they can handle their own decoding. 1068249259Sdimclass A64I_bf_ext<bit sf, bits<2> opc, RegisterClass GPRDest, ValueType dty, 1069249259Sdim string asmop, bits<6> imms, dag pattern> 1070249259Sdim : A64I_bitfield<sf, opc, sf, 1071249259Sdim (outs GPRDest:$Rd), (ins GPR32:$Rn), 1072249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), 1073249259Sdim [(set dty:$Rd, pattern)], NoItinerary> { 1074249259Sdim let ImmR = 0b000000; 1075249259Sdim let ImmS = imms; 1076249259Sdim} 1077249259Sdim 1078249259Sdim// Signed extensions 1079249259Sdimdef SXTBxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtb", 7, 1080249259Sdim (sext_inreg (anyext i32:$Rn), i8)>; 1081249259Sdimdef SXTBww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxtb", 7, 1082249259Sdim (sext_inreg i32:$Rn, i8)>; 1083249259Sdimdef SXTHxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxth", 15, 1084249259Sdim (sext_inreg (anyext i32:$Rn), i16)>; 1085249259Sdimdef SXTHww : A64I_bf_ext<0b0, 0b00, GPR32, i32, "sxth", 15, 1086249259Sdim (sext_inreg i32:$Rn, i16)>; 1087249259Sdimdef SXTWxw : A64I_bf_ext<0b1, 0b00, GPR64, i64, "sxtw", 31, (sext i32:$Rn)>; 1088249259Sdim 1089249259Sdim// Unsigned extensions 1090249259Sdimdef UXTBww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxtb", 7, 1091249259Sdim (and i32:$Rn, 255)>; 1092249259Sdimdef UXTHww : A64I_bf_ext<0b0, 0b10, GPR32, i32, "uxth", 15, 1093249259Sdim (and i32:$Rn, 65535)>; 1094249259Sdim 1095249259Sdim// The 64-bit unsigned variants are not strictly architectural but recommended 1096249259Sdim// for consistency. 1097249259Sdimlet isAsmParserOnly = 1 in { 1098249259Sdim def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxtb", 7, 1099249259Sdim (and (anyext i32:$Rn), 255)>; 1100249259Sdim def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, i64, "uxth", 15, 1101249259Sdim (and (anyext i32:$Rn), 65535)>; 1102249259Sdim} 1103249259Sdim 1104249259Sdim// Extra patterns for when the source register is actually 64-bits 1105249259Sdim// too. There's no architectural difference here, it's just LLVM 1106249259Sdim// shinanigans. There's no need for equivalent zero-extension patterns 1107249259Sdim// because they'll already be caught by logical (immediate) matching. 1108249259Sdimdef : Pat<(sext_inreg i64:$Rn, i8), 1109249259Sdim (SXTBxw (EXTRACT_SUBREG $Rn, sub_32))>; 1110249259Sdimdef : Pat<(sext_inreg i64:$Rn, i16), 1111249259Sdim (SXTHxw (EXTRACT_SUBREG $Rn, sub_32))>; 1112249259Sdimdef : Pat<(sext_inreg i64:$Rn, i32), 1113249259Sdim (SXTWxw (EXTRACT_SUBREG $Rn, sub_32))>; 1114249259Sdim 1115249259Sdim 1116249259Sdim//===------------------------------- 1117249259Sdim// 3. Aliases for ASR and LSR (the simple shifts) 1118249259Sdim//===------------------------------- 1119249259Sdim 1120249259Sdim// These also handle their own decoding because ImmS being set makes 1121249259Sdim// them take precedence over BFM. 1122249259Sdimmulticlass A64I_shift<bits<2> opc, string asmop, SDNode opnode> { 1123249259Sdim def wwi : A64I_bitfield<0b0, opc, 0b0, 1124249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR), 1125249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1126249259Sdim [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))], 1127249259Sdim NoItinerary> { 1128249259Sdim let ImmS = 31; 1129249259Sdim } 1130249259Sdim 1131249259Sdim def xxi : A64I_bitfield<0b1, opc, 0b1, 1132249259Sdim (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR), 1133249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR"), 1134249259Sdim [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))], 1135249259Sdim NoItinerary> { 1136249259Sdim let ImmS = 63; 1137249259Sdim } 1138249259Sdim 1139249259Sdim} 1140249259Sdim 1141249259Sdimdefm ASR : A64I_shift<0b00, "asr", sra>; 1142249259Sdimdefm LSR : A64I_shift<0b10, "lsr", srl>; 1143249259Sdim 1144249259Sdim//===------------------------------- 1145249259Sdim// 4. Aliases for LSL 1146249259Sdim//===------------------------------- 1147249259Sdim 1148249259Sdim// Unfortunately LSL and subsequent aliases are much more complicated. We need 1149249259Sdim// to be able to say certain output instruction fields depend in a complex 1150249259Sdim// manner on combinations of input assembly fields). 1151249259Sdim// 1152249259Sdim// MIOperandInfo *might* have been able to do it, but at the cost of 1153249259Sdim// significantly more C++ code. 1154249259Sdim 1155249259Sdim// N.b. contrary to usual practice these operands store the shift rather than 1156249259Sdim// the machine bits in an MCInst. The complexity overhead of consistency 1157249259Sdim// outweighed the benefits in this case (custom asmparser, printer and selection 1158249259Sdim// vs custom encoder). 1159249259Sdimdef bitfield32_lsl_imm : Operand<i64>, 1160249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1161249259Sdim let ParserMatchClass = uimm5_asmoperand; 1162249259Sdim let EncoderMethod = "getBitfield32LSLOpValue"; 1163249259Sdim} 1164249259Sdim 1165249259Sdimdef bitfield64_lsl_imm : Operand<i64>, 1166249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1167249259Sdim let ParserMatchClass = uimm6_asmoperand; 1168249259Sdim let EncoderMethod = "getBitfield64LSLOpValue"; 1169249259Sdim} 1170249259Sdim 1171249259Sdimclass A64I_bitfield_lsl<bit sf, RegisterClass GPR, ValueType ty, 1172249259Sdim Operand operand> 1173249259Sdim : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm), 1174249259Sdim "lsl\t$Rd, $Rn, $FullImm", 1175249259Sdim [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))], 1176249259Sdim NoItinerary> { 1177249259Sdim bits<12> FullImm; 1178249259Sdim let ImmR = FullImm{5-0}; 1179249259Sdim let ImmS = FullImm{11-6}; 1180249259Sdim 1181249259Sdim // No disassembler allowed because it would overlap with BFM which does the 1182249259Sdim // actual work. 1183249259Sdim let isAsmParserOnly = 1; 1184249259Sdim} 1185249259Sdim 1186249259Sdimdef LSLwwi : A64I_bitfield_lsl<0b0, GPR32, i32, bitfield32_lsl_imm>; 1187249259Sdimdef LSLxxi : A64I_bitfield_lsl<0b1, GPR64, i64, bitfield64_lsl_imm>; 1188249259Sdim 1189249259Sdim//===------------------------------- 1190249259Sdim// 5. Aliases for bitfield extract instructions 1191249259Sdim//===------------------------------- 1192249259Sdim 1193249259Sdimdef bfx32_width_asmoperand : AsmOperandClass { 1194249259Sdim let Name = "BFX32Width"; 1195249259Sdim let PredicateMethod = "isBitfieldWidth<32>"; 1196249259Sdim let RenderMethod = "addBFXWidthOperands"; 1197249259Sdim let DiagnosticType = "Width32"; 1198249259Sdim} 1199249259Sdim 1200249259Sdimdef bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> { 1201249259Sdim let PrintMethod = "printBFXWidthOperand"; 1202249259Sdim let ParserMatchClass = bfx32_width_asmoperand; 1203249259Sdim} 1204249259Sdim 1205249259Sdimdef bfx64_width_asmoperand : AsmOperandClass { 1206249259Sdim let Name = "BFX64Width"; 1207249259Sdim let PredicateMethod = "isBitfieldWidth<64>"; 1208249259Sdim let RenderMethod = "addBFXWidthOperands"; 1209249259Sdim let DiagnosticType = "Width64"; 1210249259Sdim} 1211249259Sdim 1212249259Sdimdef bfx64_width : Operand<i64> { 1213249259Sdim let PrintMethod = "printBFXWidthOperand"; 1214249259Sdim let ParserMatchClass = bfx64_width_asmoperand; 1215249259Sdim} 1216249259Sdim 1217249259Sdim 1218249259Sdimmulticlass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> { 1219249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1220249259Sdim (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1221249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1222249259Sdim [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))], 1223249259Sdim NoItinerary> { 1224249259Sdim // As above, no disassembler allowed. 1225249259Sdim let isAsmParserOnly = 1; 1226249259Sdim } 1227249259Sdim 1228249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1229249259Sdim (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1230249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1231249259Sdim [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))], 1232249259Sdim NoItinerary> { 1233249259Sdim // As above, no disassembler allowed. 1234249259Sdim let isAsmParserOnly = 1; 1235249259Sdim } 1236249259Sdim} 1237249259Sdim 1238249259Sdimdefm SBFX : A64I_bitfield_extract<0b00, "sbfx", A64Sbfx>; 1239249259Sdimdefm UBFX : A64I_bitfield_extract<0b10, "ubfx", A64Ubfx>; 1240249259Sdim 1241249259Sdim// Again, variants based on BFM modify Rd so need it as an input too. 1242249259Sdimdef BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1243249259Sdim (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS), 1244249259Sdim "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1245249259Sdim // As above, no disassembler allowed. 1246249259Sdim let isAsmParserOnly = 1; 1247249259Sdim let Constraints = "$src = $Rd"; 1248249259Sdim} 1249249259Sdim 1250249259Sdimdef BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1251249259Sdim (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS), 1252249259Sdim "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1253249259Sdim // As above, no disassembler allowed. 1254249259Sdim let isAsmParserOnly = 1; 1255249259Sdim let Constraints = "$src = $Rd"; 1256249259Sdim} 1257249259Sdim 1258249259Sdim// SBFX instructions can do a 1-instruction sign-extension of boolean values. 1259249259Sdimdef : Pat<(sext_inreg i64:$Rn, i1), (SBFXxxii $Rn, 0, 0)>; 1260249259Sdimdef : Pat<(sext_inreg i32:$Rn, i1), (SBFXwwii $Rn, 0, 0)>; 1261249259Sdimdef : Pat<(i64 (sext_inreg (anyext i32:$Rn), i1)), 1262249259Sdim (SBFXxxii (SUBREG_TO_REG (i64 0), $Rn, sub_32), 0, 0)>; 1263249259Sdim 1264249259Sdim// UBFX makes sense as an implementation of a 64-bit zero-extension too. Could 1265249259Sdim// use either 64-bit or 32-bit variant, but 32-bit might be more efficient. 1266249259Sdimdef : Pat<(zext i32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii $Rn, 0, 31), 1267249259Sdim sub_32)>; 1268249259Sdim 1269249259Sdim//===------------------------------- 1270249259Sdim// 6. Aliases for bitfield insert instructions 1271249259Sdim//===------------------------------- 1272249259Sdim 1273249259Sdimdef bfi32_lsb_asmoperand : AsmOperandClass { 1274249259Sdim let Name = "BFI32LSB"; 1275249259Sdim let PredicateMethod = "isUImm<5>"; 1276249259Sdim let RenderMethod = "addBFILSBOperands<32>"; 1277249259Sdim let DiagnosticType = "UImm5"; 1278249259Sdim} 1279249259Sdim 1280249259Sdimdef bfi32_lsb : Operand<i64>, 1281249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> { 1282249259Sdim let PrintMethod = "printBFILSBOperand<32>"; 1283249259Sdim let ParserMatchClass = bfi32_lsb_asmoperand; 1284249259Sdim} 1285249259Sdim 1286249259Sdimdef bfi64_lsb_asmoperand : AsmOperandClass { 1287249259Sdim let Name = "BFI64LSB"; 1288249259Sdim let PredicateMethod = "isUImm<6>"; 1289249259Sdim let RenderMethod = "addBFILSBOperands<64>"; 1290249259Sdim let DiagnosticType = "UImm6"; 1291249259Sdim} 1292249259Sdim 1293249259Sdimdef bfi64_lsb : Operand<i64>, 1294249259Sdim ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> { 1295249259Sdim let PrintMethod = "printBFILSBOperand<64>"; 1296249259Sdim let ParserMatchClass = bfi64_lsb_asmoperand; 1297249259Sdim} 1298249259Sdim 1299249259Sdim// Width verification is performed during conversion so width operand can be 1300249259Sdim// shared between 32/64-bit cases. Still needed for the print method though 1301249259Sdim// because ImmR encodes "width - 1". 1302249259Sdimdef bfi32_width_asmoperand : AsmOperandClass { 1303249259Sdim let Name = "BFI32Width"; 1304249259Sdim let PredicateMethod = "isBitfieldWidth<32>"; 1305249259Sdim let RenderMethod = "addBFIWidthOperands"; 1306249259Sdim let DiagnosticType = "Width32"; 1307249259Sdim} 1308249259Sdim 1309249259Sdimdef bfi32_width : Operand<i64>, 1310249259Sdim ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> { 1311249259Sdim let PrintMethod = "printBFIWidthOperand"; 1312249259Sdim let ParserMatchClass = bfi32_width_asmoperand; 1313249259Sdim} 1314249259Sdim 1315249259Sdimdef bfi64_width_asmoperand : AsmOperandClass { 1316249259Sdim let Name = "BFI64Width"; 1317249259Sdim let PredicateMethod = "isBitfieldWidth<64>"; 1318249259Sdim let RenderMethod = "addBFIWidthOperands"; 1319249259Sdim let DiagnosticType = "Width64"; 1320249259Sdim} 1321249259Sdim 1322249259Sdimdef bfi64_width : Operand<i64>, 1323249259Sdim ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> { 1324249259Sdim let PrintMethod = "printBFIWidthOperand"; 1325249259Sdim let ParserMatchClass = bfi64_width_asmoperand; 1326249259Sdim} 1327249259Sdim 1328249259Sdimmulticlass A64I_bitfield_insert<bits<2> opc, string asmop> { 1329249259Sdim def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd), 1330249259Sdim (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1331249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1332249259Sdim [], NoItinerary> { 1333249259Sdim // As above, no disassembler allowed. 1334249259Sdim let isAsmParserOnly = 1; 1335249259Sdim } 1336249259Sdim 1337249259Sdim def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd), 1338249259Sdim (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1339249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"), 1340249259Sdim [], NoItinerary> { 1341249259Sdim // As above, no disassembler allowed. 1342249259Sdim let isAsmParserOnly = 1; 1343249259Sdim } 1344249259Sdim} 1345249259Sdim 1346249259Sdimdefm SBFIZ : A64I_bitfield_insert<0b00, "sbfiz">; 1347249259Sdimdefm UBFIZ : A64I_bitfield_insert<0b10, "ubfiz">; 1348249259Sdim 1349249259Sdim 1350249259Sdimdef BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd), 1351249259Sdim (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS), 1352249259Sdim "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1353249259Sdim // As above, no disassembler allowed. 1354249259Sdim let isAsmParserOnly = 1; 1355249259Sdim let Constraints = "$src = $Rd"; 1356249259Sdim} 1357249259Sdim 1358249259Sdimdef BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd), 1359249259Sdim (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS), 1360249259Sdim "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> { 1361249259Sdim // As above, no disassembler allowed. 1362249259Sdim let isAsmParserOnly = 1; 1363249259Sdim let Constraints = "$src = $Rd"; 1364249259Sdim} 1365249259Sdim 1366249259Sdim//===----------------------------------------------------------------------===// 1367249259Sdim// Compare and branch (immediate) 1368249259Sdim//===----------------------------------------------------------------------===// 1369249259Sdim// Contains: CBZ, CBNZ 1370249259Sdim 1371249259Sdimclass label_asmoperand<int width, int scale> : AsmOperandClass { 1372249259Sdim let Name = "Label" # width # "_" # scale; 1373249259Sdim let PredicateMethod = "isLabel<" # width # "," # scale # ">"; 1374249259Sdim let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">"; 1375249259Sdim let DiagnosticType = "Label"; 1376249259Sdim} 1377249259Sdim 1378249259Sdimdef label_wid19_scal4_asmoperand : label_asmoperand<19, 4>; 1379249259Sdim 1380249259Sdim// All conditional immediate branches are the same really: 19 signed bits scaled 1381249259Sdim// by the instruction-size (4). 1382249259Sdimdef bcc_target : Operand<OtherVT> { 1383249259Sdim // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 1384249259Sdim let ParserMatchClass = label_wid19_scal4_asmoperand; 1385249259Sdim let PrintMethod = "printLabelOperand<19, 4>"; 1386249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_condbr>"; 1387249259Sdim let OperandType = "OPERAND_PCREL"; 1388249259Sdim} 1389249259Sdim 1390249259Sdimmulticlass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> { 1391249259Sdim let isBranch = 1, isTerminator = 1 in { 1392249259Sdim def x : A64I_cmpbr<0b1, op, 1393249259Sdim (outs), 1394249259Sdim (ins GPR64:$Rt, bcc_target:$Label), 1395249259Sdim !strconcat(asmop,"\t$Rt, $Label"), 1396249259Sdim [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)], 1397249259Sdim NoItinerary>; 1398249259Sdim 1399249259Sdim def w : A64I_cmpbr<0b0, op, 1400249259Sdim (outs), 1401249259Sdim (ins GPR32:$Rt, bcc_target:$Label), 1402249259Sdim !strconcat(asmop,"\t$Rt, $Label"), 1403249259Sdim [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)], 1404249259Sdim NoItinerary>; 1405249259Sdim } 1406249259Sdim} 1407249259Sdim 1408249259Sdimdefm CBZ : cmpbr_sizes<0b0, "cbz", ImmLeaf<i32, [{ 1409249259Sdim return Imm == A64CC::EQ; 1410249259Sdim}]> >; 1411249259Sdimdefm CBNZ : cmpbr_sizes<0b1, "cbnz", ImmLeaf<i32, [{ 1412249259Sdim return Imm == A64CC::NE; 1413249259Sdim}]> >; 1414249259Sdim 1415249259Sdim//===----------------------------------------------------------------------===// 1416249259Sdim// Conditional branch (immediate) instructions 1417249259Sdim//===----------------------------------------------------------------------===// 1418249259Sdim// Contains: B.cc 1419249259Sdim 1420249259Sdimdef cond_code_asmoperand : AsmOperandClass { 1421249259Sdim let Name = "CondCode"; 1422249259Sdim let DiagnosticType = "CondCode"; 1423249259Sdim} 1424249259Sdim 1425249259Sdimdef cond_code : Operand<i32>, ImmLeaf<i32, [{ 1426249259Sdim return Imm >= 0 && Imm <= 15; 1427249259Sdim}]> { 1428249259Sdim let PrintMethod = "printCondCodeOperand"; 1429249259Sdim let ParserMatchClass = cond_code_asmoperand; 1430249259Sdim} 1431249259Sdim 1432249259Sdimdef Bcc : A64I_condbr<0b0, 0b0, (outs), 1433249259Sdim (ins cond_code:$Cond, bcc_target:$Label), 1434249259Sdim "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)], 1435249259Sdim NoItinerary> { 1436249259Sdim let Uses = [NZCV]; 1437249259Sdim let isBranch = 1; 1438249259Sdim let isTerminator = 1; 1439249259Sdim} 1440249259Sdim 1441249259Sdim//===----------------------------------------------------------------------===// 1442249259Sdim// Conditional compare (immediate) instructions 1443249259Sdim//===----------------------------------------------------------------------===// 1444249259Sdim// Contains: CCMN, CCMP 1445249259Sdim 1446249259Sdimdef uimm4_asmoperand : AsmOperandClass { 1447249259Sdim let Name = "UImm4"; 1448249259Sdim let PredicateMethod = "isUImm<4>"; 1449249259Sdim let RenderMethod = "addImmOperands"; 1450249259Sdim let DiagnosticType = "UImm4"; 1451249259Sdim} 1452249259Sdim 1453249259Sdimdef uimm4 : Operand<i32> { 1454249259Sdim let ParserMatchClass = uimm4_asmoperand; 1455249259Sdim} 1456249259Sdim 1457249259Sdimdef uimm5 : Operand<i32> { 1458249259Sdim let ParserMatchClass = uimm5_asmoperand; 1459249259Sdim} 1460249259Sdim 1461249259Sdim// The only difference between this operand and the one for instructions like 1462249259Sdim// B.cc is that it's parsed manually. The other get parsed implicitly as part of 1463249259Sdim// the mnemonic handling. 1464249259Sdimdef cond_code_op_asmoperand : AsmOperandClass { 1465249259Sdim let Name = "CondCodeOp"; 1466249259Sdim let RenderMethod = "addCondCodeOperands"; 1467249259Sdim let PredicateMethod = "isCondCode"; 1468249259Sdim let ParserMethod = "ParseCondCodeOperand"; 1469249259Sdim let DiagnosticType = "CondCode"; 1470249259Sdim} 1471249259Sdim 1472249259Sdimdef cond_code_op : Operand<i32> { 1473249259Sdim let PrintMethod = "printCondCodeOperand"; 1474249259Sdim let ParserMatchClass = cond_code_op_asmoperand; 1475249259Sdim} 1476249259Sdim 1477249259Sdimclass A64I_condcmpimmImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1478249259Sdim : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs), 1479249259Sdim (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond), 1480249259Sdim !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"), 1481249259Sdim [], NoItinerary> { 1482249259Sdim let Defs = [NZCV]; 1483249259Sdim} 1484249259Sdim 1485249259Sdimdef CCMNwi : A64I_condcmpimmImpl<0b0, 0b0, GPR32, "ccmn">; 1486249259Sdimdef CCMNxi : A64I_condcmpimmImpl<0b1, 0b0, GPR64, "ccmn">; 1487249259Sdimdef CCMPwi : A64I_condcmpimmImpl<0b0, 0b1, GPR32, "ccmp">; 1488249259Sdimdef CCMPxi : A64I_condcmpimmImpl<0b1, 0b1, GPR64, "ccmp">; 1489249259Sdim 1490249259Sdim//===----------------------------------------------------------------------===// 1491249259Sdim// Conditional compare (register) instructions 1492249259Sdim//===----------------------------------------------------------------------===// 1493249259Sdim// Contains: CCMN, CCMP 1494249259Sdim 1495249259Sdimclass A64I_condcmpregImpl<bit sf, bit op, RegisterClass GPR, string asmop> 1496249259Sdim : A64I_condcmpreg<sf, op, 0b0, 0b0, 0b1, 1497249259Sdim (outs), 1498249259Sdim (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 1499249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 1500249259Sdim [], NoItinerary> { 1501249259Sdim let Defs = [NZCV]; 1502249259Sdim} 1503249259Sdim 1504249259Sdimdef CCMNww : A64I_condcmpregImpl<0b0, 0b0, GPR32, "ccmn">; 1505249259Sdimdef CCMNxx : A64I_condcmpregImpl<0b1, 0b0, GPR64, "ccmn">; 1506249259Sdimdef CCMPww : A64I_condcmpregImpl<0b0, 0b1, GPR32, "ccmp">; 1507249259Sdimdef CCMPxx : A64I_condcmpregImpl<0b1, 0b1, GPR64, "ccmp">; 1508249259Sdim 1509249259Sdim//===----------------------------------------------------------------------===// 1510249259Sdim// Conditional select instructions 1511249259Sdim//===----------------------------------------------------------------------===// 1512249259Sdim// Contains: CSEL, CSINC, CSINV, CSNEG + aliases CSET, CSETM, CINC, CINV, CNEG 1513249259Sdim 1514249259Sdim// Condition code which is encoded as the inversion (semantically rather than 1515249259Sdim// bitwise) in the instruction. 1516249259Sdimdef inv_cond_code_op_asmoperand : AsmOperandClass { 1517249259Sdim let Name = "InvCondCodeOp"; 1518249259Sdim let RenderMethod = "addInvCondCodeOperands"; 1519249259Sdim let PredicateMethod = "isCondCode"; 1520249259Sdim let ParserMethod = "ParseCondCodeOperand"; 1521249259Sdim let DiagnosticType = "CondCode"; 1522249259Sdim} 1523249259Sdim 1524249259Sdimdef inv_cond_code_op : Operand<i32> { 1525249259Sdim let ParserMatchClass = inv_cond_code_op_asmoperand; 1526249259Sdim} 1527249259Sdim 1528249259Sdim// Having a separate operand for the selectable use-case is debatable, but gives 1529249259Sdim// consistency with cond_code. 1530249259Sdimdef inv_cond_XFORM : SDNodeXForm<imm, [{ 1531249259Sdim A64CC::CondCodes CC = static_cast<A64CC::CondCodes>(N->getZExtValue()); 1532249259Sdim return CurDAG->getTargetConstant(A64InvertCondCode(CC), MVT::i32); 1533249259Sdim}]>; 1534249259Sdim 1535249259Sdimdef inv_cond_code 1536249259Sdim : ImmLeaf<i32, [{ return Imm >= 0 && Imm <= 15; }], inv_cond_XFORM>; 1537249259Sdim 1538249259Sdim 1539249259Sdimmulticlass A64I_condselSizes<bit op, bits<2> op2, string asmop, 1540249259Sdim SDPatternOperator select> { 1541249259Sdim let Uses = [NZCV] in { 1542249259Sdim def wwwc : A64I_condsel<0b0, op, 0b0, op2, 1543249259Sdim (outs GPR32:$Rd), 1544249259Sdim (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond), 1545249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1546249259Sdim [(set i32:$Rd, (select i32:$Rn, i32:$Rm))], 1547249259Sdim NoItinerary>; 1548249259Sdim 1549249259Sdim 1550249259Sdim def xxxc : A64I_condsel<0b1, op, 0b0, op2, 1551249259Sdim (outs GPR64:$Rd), 1552249259Sdim (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond), 1553249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"), 1554249259Sdim [(set i64:$Rd, (select i64:$Rn, i64:$Rm))], 1555249259Sdim NoItinerary>; 1556249259Sdim } 1557249259Sdim} 1558249259Sdim 1559249259Sdimdef simple_select 1560249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), 1561249259Sdim (A64select_cc NZCV, node:$lhs, node:$rhs, (i32 imm:$Cond))>; 1562249259Sdim 1563249259Sdimclass complex_select<SDPatternOperator opnode> 1564249259Sdim : PatFrag<(ops node:$lhs, node:$rhs), 1565249259Sdim (A64select_cc NZCV, node:$lhs, (opnode node:$rhs), (i32 imm:$Cond))>; 1566249259Sdim 1567249259Sdim 1568249259Sdimdefm CSEL : A64I_condselSizes<0b0, 0b00, "csel", simple_select>; 1569249259Sdimdefm CSINC : A64I_condselSizes<0b0, 0b01, "csinc", 1570249259Sdim complex_select<PatFrag<(ops node:$val), 1571249259Sdim (add node:$val, 1)>>>; 1572249259Sdimdefm CSINV : A64I_condselSizes<0b1, 0b00, "csinv", complex_select<not>>; 1573249259Sdimdefm CSNEG : A64I_condselSizes<0b1, 0b01, "csneg", complex_select<ineg>>; 1574249259Sdim 1575249259Sdim// Now the instruction aliases, which fit nicely into LLVM's model: 1576249259Sdim 1577249259Sdimdef : InstAlias<"cset $Rd, $Cond", 1578249259Sdim (CSINCwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1579249259Sdimdef : InstAlias<"cset $Rd, $Cond", 1580249259Sdim (CSINCxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1581249259Sdimdef : InstAlias<"csetm $Rd, $Cond", 1582249259Sdim (CSINVwwwc GPR32:$Rd, WZR, WZR, inv_cond_code_op:$Cond)>; 1583249259Sdimdef : InstAlias<"csetm $Rd, $Cond", 1584249259Sdim (CSINVxxxc GPR64:$Rd, XZR, XZR, inv_cond_code_op:$Cond)>; 1585249259Sdimdef : InstAlias<"cinc $Rd, $Rn, $Cond", 1586249259Sdim (CSINCwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1587249259Sdimdef : InstAlias<"cinc $Rd, $Rn, $Cond", 1588249259Sdim (CSINCxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1589249259Sdimdef : InstAlias<"cinv $Rd, $Rn, $Cond", 1590249259Sdim (CSINVwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1591249259Sdimdef : InstAlias<"cinv $Rd, $Rn, $Cond", 1592249259Sdim (CSINVxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1593249259Sdimdef : InstAlias<"cneg $Rd, $Rn, $Cond", 1594249259Sdim (CSNEGwwwc GPR32:$Rd, GPR32:$Rn, GPR32:$Rn, inv_cond_code_op:$Cond)>; 1595249259Sdimdef : InstAlias<"cneg $Rd, $Rn, $Cond", 1596249259Sdim (CSNEGxxxc GPR64:$Rd, GPR64:$Rn, GPR64:$Rn, inv_cond_code_op:$Cond)>; 1597249259Sdim 1598249259Sdim// Finally some helper patterns. 1599249259Sdim 1600249259Sdim// For CSET (a.k.a. zero-extension of icmp) 1601249259Sdimdef : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1602249259Sdim (CSINCwwwc WZR, WZR, cond_code:$Cond)>; 1603249259Sdimdef : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1604249259Sdim (CSINCwwwc WZR, WZR, inv_cond_code:$Cond)>; 1605249259Sdim 1606249259Sdimdef : Pat<(A64select_cc NZCV, 0, 1, cond_code:$Cond), 1607249259Sdim (CSINCxxxc XZR, XZR, cond_code:$Cond)>; 1608249259Sdimdef : Pat<(A64select_cc NZCV, 1, 0, inv_cond_code:$Cond), 1609249259Sdim (CSINCxxxc XZR, XZR, inv_cond_code:$Cond)>; 1610249259Sdim 1611249259Sdim// For CSETM (a.k.a. sign-extension of icmp) 1612249259Sdimdef : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1613249259Sdim (CSINVwwwc WZR, WZR, cond_code:$Cond)>; 1614249259Sdimdef : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1615249259Sdim (CSINVwwwc WZR, WZR, inv_cond_code:$Cond)>; 1616249259Sdim 1617249259Sdimdef : Pat<(A64select_cc NZCV, 0, -1, cond_code:$Cond), 1618249259Sdim (CSINVxxxc XZR, XZR, cond_code:$Cond)>; 1619249259Sdimdef : Pat<(A64select_cc NZCV, -1, 0, inv_cond_code:$Cond), 1620249259Sdim (CSINVxxxc XZR, XZR, inv_cond_code:$Cond)>; 1621249259Sdim 1622249259Sdim// CINC, CINV and CNEG get dealt with automatically, which leaves the issue of 1623249259Sdim// commutativity. The instructions are to complex for isCommutable to be used, 1624249259Sdim// so we have to create the patterns manually: 1625249259Sdim 1626249259Sdim// No commutable pattern for CSEL since the commuted version is isomorphic. 1627249259Sdim 1628249259Sdim// CSINC 1629249259Sdimdef :Pat<(A64select_cc NZCV, (add i32:$Rm, 1), i32:$Rn, inv_cond_code:$Cond), 1630249259Sdim (CSINCwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1631249259Sdimdef :Pat<(A64select_cc NZCV, (add i64:$Rm, 1), i64:$Rn, inv_cond_code:$Cond), 1632249259Sdim (CSINCxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1633249259Sdim 1634249259Sdim// CSINV 1635249259Sdimdef :Pat<(A64select_cc NZCV, (not i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1636249259Sdim (CSINVwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1637249259Sdimdef :Pat<(A64select_cc NZCV, (not i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1638249259Sdim (CSINVxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1639249259Sdim 1640249259Sdim// CSNEG 1641249259Sdimdef :Pat<(A64select_cc NZCV, (ineg i32:$Rm), i32:$Rn, inv_cond_code:$Cond), 1642249259Sdim (CSNEGwwwc $Rn, $Rm, inv_cond_code:$Cond)>; 1643249259Sdimdef :Pat<(A64select_cc NZCV, (ineg i64:$Rm), i64:$Rn, inv_cond_code:$Cond), 1644249259Sdim (CSNEGxxxc $Rn, $Rm, inv_cond_code:$Cond)>; 1645249259Sdim 1646249259Sdim//===----------------------------------------------------------------------===// 1647249259Sdim// Data Processing (1 source) instructions 1648249259Sdim//===----------------------------------------------------------------------===// 1649249259Sdim// Contains: RBIT, REV16, REV, REV32, CLZ, CLS. 1650249259Sdim 1651249259Sdim// We define an unary operator which always fails. We will use this to 1652249259Sdim// define unary operators that cannot be matched. 1653249259Sdim 1654249259Sdimclass A64I_dp_1src_impl<bit sf, bits<6> opcode, string asmop, 1655249259Sdim list<dag> patterns, RegisterClass GPRrc, 1656249259Sdim InstrItinClass itin>: 1657249259Sdim A64I_dp_1src<sf, 1658249259Sdim 0, 1659249259Sdim 0b00000, 1660249259Sdim opcode, 1661249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), 1662249259Sdim (outs GPRrc:$Rd), 1663249259Sdim (ins GPRrc:$Rn), 1664249259Sdim patterns, 1665249259Sdim itin>; 1666249259Sdim 1667249259Sdimmulticlass A64I_dp_1src <bits<6> opcode, string asmop> { 1668249259Sdim let hasSideEffects = 0 in { 1669249259Sdim def ww : A64I_dp_1src_impl<0b0, opcode, asmop, [], GPR32, NoItinerary>; 1670249259Sdim def xx : A64I_dp_1src_impl<0b1, opcode, asmop, [], GPR64, NoItinerary>; 1671249259Sdim } 1672249259Sdim} 1673249259Sdim 1674249259Sdimdefm RBIT : A64I_dp_1src<0b000000, "rbit">; 1675249259Sdimdefm CLS : A64I_dp_1src<0b000101, "cls">; 1676249259Sdimdefm CLZ : A64I_dp_1src<0b000100, "clz">; 1677249259Sdim 1678249259Sdimdef : Pat<(ctlz i32:$Rn), (CLZww $Rn)>; 1679249259Sdimdef : Pat<(ctlz i64:$Rn), (CLZxx $Rn)>; 1680249259Sdimdef : Pat<(ctlz_zero_undef i32:$Rn), (CLZww $Rn)>; 1681249259Sdimdef : Pat<(ctlz_zero_undef i64:$Rn), (CLZxx $Rn)>; 1682249259Sdim 1683249259Sdimdef : Pat<(cttz i32:$Rn), (CLZww (RBITww $Rn))>; 1684249259Sdimdef : Pat<(cttz i64:$Rn), (CLZxx (RBITxx $Rn))>; 1685249259Sdimdef : Pat<(cttz_zero_undef i32:$Rn), (CLZww (RBITww $Rn))>; 1686249259Sdimdef : Pat<(cttz_zero_undef i64:$Rn), (CLZxx (RBITxx $Rn))>; 1687249259Sdim 1688249259Sdim 1689249259Sdimdef REVww : A64I_dp_1src_impl<0b0, 0b000010, "rev", 1690249259Sdim [(set i32:$Rd, (bswap i32:$Rn))], 1691249259Sdim GPR32, NoItinerary>; 1692249259Sdimdef REVxx : A64I_dp_1src_impl<0b1, 0b000011, "rev", 1693249259Sdim [(set i64:$Rd, (bswap i64:$Rn))], 1694249259Sdim GPR64, NoItinerary>; 1695249259Sdimdef REV32xx : A64I_dp_1src_impl<0b1, 0b000010, "rev32", 1696249259Sdim [(set i64:$Rd, (bswap (rotr i64:$Rn, (i64 32))))], 1697249259Sdim GPR64, NoItinerary>; 1698249259Sdimdef REV16ww : A64I_dp_1src_impl<0b0, 0b000001, "rev16", 1699249259Sdim [(set i32:$Rd, (bswap (rotr i32:$Rn, (i64 16))))], 1700249259Sdim GPR32, 1701249259Sdim NoItinerary>; 1702249259Sdimdef REV16xx : A64I_dp_1src_impl<0b1, 0b000001, "rev16", [], GPR64, NoItinerary>; 1703249259Sdim 1704249259Sdim//===----------------------------------------------------------------------===// 1705249259Sdim// Data Processing (2 sources) instructions 1706249259Sdim//===----------------------------------------------------------------------===// 1707249259Sdim// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, 1708249259Sdim// LSR, ASR, ROR 1709249259Sdim 1710249259Sdim 1711249259Sdimclass dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns, 1712249259Sdim RegisterClass GPRsp, 1713249259Sdim InstrItinClass itin>: 1714249259Sdim A64I_dp_2src<sf, 1715249259Sdim opcode, 1716249259Sdim 0, 1717249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm"), 1718249259Sdim (outs GPRsp:$Rd), 1719249259Sdim (ins GPRsp:$Rn, GPRsp:$Rm), 1720249259Sdim patterns, 1721249259Sdim itin>; 1722249259Sdim 1723249259Sdimmulticlass dp_2src_crc<bit c, string asmop> { 1724249259Sdim def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0}, 1725249259Sdim !strconcat(asmop, "b"), [], GPR32, NoItinerary>; 1726249259Sdim def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1}, 1727249259Sdim !strconcat(asmop, "h"), [], GPR32, NoItinerary>; 1728249259Sdim def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0}, 1729249259Sdim !strconcat(asmop, "w"), [], GPR32, NoItinerary>; 1730249259Sdim def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0, 1731249259Sdim !strconcat(asmop, "x\t$Rd, $Rn, $Rm"), 1732249259Sdim (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [], 1733249259Sdim NoItinerary>; 1734249259Sdim} 1735249259Sdim 1736249259Sdimmulticlass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> { 1737249259Sdim def www : dp_2src_impl<0b0, 1738249259Sdim opcode, 1739249259Sdim asmop, 1740249259Sdim [(set i32:$Rd, 1741249259Sdim (op i32:$Rn, (i64 (zext i32:$Rm))))], 1742249259Sdim GPR32, 1743249259Sdim NoItinerary>; 1744249259Sdim def xxx : dp_2src_impl<0b1, 1745249259Sdim opcode, 1746249259Sdim asmop, 1747249259Sdim [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1748249259Sdim GPR64, 1749249259Sdim NoItinerary>; 1750249259Sdim} 1751249259Sdim 1752249259Sdim 1753249259Sdimmulticlass dp_2src <bits<6> opcode, string asmop, SDPatternOperator op> { 1754249259Sdim def www : dp_2src_impl<0b0, 1755249259Sdim opcode, 1756249259Sdim asmop, 1757249259Sdim [(set i32:$Rd, (op i32:$Rn, i32:$Rm))], 1758249259Sdim GPR32, 1759249259Sdim NoItinerary>; 1760249259Sdim def xxx : dp_2src_impl<0b1, 1761249259Sdim opcode, 1762249259Sdim asmop, 1763249259Sdim [(set i64:$Rd, (op i64:$Rn, i64:$Rm))], 1764249259Sdim GPR64, 1765249259Sdim NoItinerary>; 1766249259Sdim} 1767249259Sdim 1768249259Sdim// Here we define the data processing 2 source instructions. 1769249259Sdimdefm CRC32 : dp_2src_crc<0b0, "crc32">; 1770249259Sdimdefm CRC32C : dp_2src_crc<0b1, "crc32c">; 1771249259Sdim 1772249259Sdimdefm UDIV : dp_2src<0b000010, "udiv", udiv>; 1773249259Sdimdefm SDIV : dp_2src<0b000011, "sdiv", sdiv>; 1774249259Sdim 1775249259Sdimdefm LSLV : dp_2src_zext<0b001000, "lsl", shl>; 1776249259Sdimdefm LSRV : dp_2src_zext<0b001001, "lsr", srl>; 1777249259Sdimdefm ASRV : dp_2src_zext<0b001010, "asr", sra>; 1778249259Sdimdefm RORV : dp_2src_zext<0b001011, "ror", rotr>; 1779249259Sdim 1780249259Sdim// Extra patterns for an incoming 64-bit value for a 32-bit 1781249259Sdim// operation. Since the LLVM operations are undefined (as in C) if the 1782249259Sdim// RHS is out of range, it's perfectly permissible to discard the high 1783249259Sdim// bits of the GPR64. 1784249259Sdimdef : Pat<(shl i32:$Rn, i64:$Rm), 1785249259Sdim (LSLVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1786249259Sdimdef : Pat<(srl i32:$Rn, i64:$Rm), 1787249259Sdim (LSRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1788249259Sdimdef : Pat<(sra i32:$Rn, i64:$Rm), 1789249259Sdim (ASRVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1790249259Sdimdef : Pat<(rotr i32:$Rn, i64:$Rm), 1791249259Sdim (RORVwww $Rn, (EXTRACT_SUBREG $Rm, sub_32))>; 1792249259Sdim 1793249259Sdim// Here we define the aliases for the data processing 2 source instructions. 1794249259Sdimdef LSL_mnemonic : MnemonicAlias<"lslv", "lsl">; 1795249259Sdimdef LSR_mnemonic : MnemonicAlias<"lsrv", "lsr">; 1796249259Sdimdef ASR_menmonic : MnemonicAlias<"asrv", "asr">; 1797249259Sdimdef ROR_menmonic : MnemonicAlias<"rorv", "ror">; 1798249259Sdim 1799249259Sdim//===----------------------------------------------------------------------===// 1800249259Sdim// Data Processing (3 sources) instructions 1801249259Sdim//===----------------------------------------------------------------------===// 1802249259Sdim// Contains: MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL, UMULH 1803249259Sdim// + aliases MUL, MNEG, SMULL, SMNEGL, UMULL, UMNEGL 1804249259Sdim 1805249259Sdimclass A64I_dp3_4operand<bit sf, bits<6> opcode, RegisterClass AccReg, 1806249259Sdim ValueType AccTy, RegisterClass SrcReg, 1807249259Sdim string asmop, dag pattern> 1808249259Sdim : A64I_dp3<sf, opcode, 1809249259Sdim (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra), 1810249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"), 1811249259Sdim [(set AccTy:$Rd, pattern)], NoItinerary> { 1812249259Sdim RegisterClass AccGPR = AccReg; 1813249259Sdim RegisterClass SrcGPR = SrcReg; 1814249259Sdim} 1815249259Sdim 1816249259Sdimdef MADDwwww : A64I_dp3_4operand<0b0, 0b000000, GPR32, i32, GPR32, "madd", 1817249259Sdim (add i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1818249259Sdimdef MADDxxxx : A64I_dp3_4operand<0b1, 0b000000, GPR64, i64, GPR64, "madd", 1819249259Sdim (add i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1820249259Sdim 1821249259Sdimdef MSUBwwww : A64I_dp3_4operand<0b0, 0b000001, GPR32, i32, GPR32, "msub", 1822249259Sdim (sub i32:$Ra, (mul i32:$Rn, i32:$Rm))>; 1823249259Sdimdef MSUBxxxx : A64I_dp3_4operand<0b1, 0b000001, GPR64, i64, GPR64, "msub", 1824249259Sdim (sub i64:$Ra, (mul i64:$Rn, i64:$Rm))>; 1825249259Sdim 1826249259Sdimdef SMADDLxwwx : A64I_dp3_4operand<0b1, 0b000010, GPR64, i64, GPR32, "smaddl", 1827249259Sdim (add i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1828249259Sdimdef SMSUBLxwwx : A64I_dp3_4operand<0b1, 0b000011, GPR64, i64, GPR32, "smsubl", 1829249259Sdim (sub i64:$Ra, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1830249259Sdim 1831249259Sdimdef UMADDLxwwx : A64I_dp3_4operand<0b1, 0b001010, GPR64, i64, GPR32, "umaddl", 1832249259Sdim (add i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1833249259Sdimdef UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, i64, GPR32, "umsubl", 1834249259Sdim (sub i64:$Ra, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1835249259Sdim 1836249259Sdimlet isCommutable = 1, PostEncoderMethod = "fixMulHigh" in { 1837249259Sdim def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd), 1838249259Sdim (ins GPR64:$Rn, GPR64:$Rm), 1839249259Sdim "umulh\t$Rd, $Rn, $Rm", 1840249259Sdim [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))], 1841249259Sdim NoItinerary>; 1842249259Sdim 1843249259Sdim def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd), 1844249259Sdim (ins GPR64:$Rn, GPR64:$Rm), 1845249259Sdim "smulh\t$Rd, $Rn, $Rm", 1846249259Sdim [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))], 1847249259Sdim NoItinerary>; 1848249259Sdim} 1849249259Sdim 1850249259Sdimmulticlass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST, 1851249259Sdim Register ZR, dag pattern> { 1852249259Sdim def : InstAlias<asmop # " $Rd, $Rn, $Rm", 1853249259Sdim (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>; 1854249259Sdim 1855249259Sdim def : Pat<pattern, (INST $Rn, $Rm, ZR)>; 1856249259Sdim} 1857249259Sdim 1858249259Sdimdefm : A64I_dp3_3operand<"mul", MADDwwww, WZR, (mul i32:$Rn, i32:$Rm)>; 1859249259Sdimdefm : A64I_dp3_3operand<"mul", MADDxxxx, XZR, (mul i64:$Rn, i64:$Rm)>; 1860249259Sdim 1861249259Sdimdefm : A64I_dp3_3operand<"mneg", MSUBwwww, WZR, 1862249259Sdim (sub 0, (mul i32:$Rn, i32:$Rm))>; 1863249259Sdimdefm : A64I_dp3_3operand<"mneg", MSUBxxxx, XZR, 1864249259Sdim (sub 0, (mul i64:$Rn, i64:$Rm))>; 1865249259Sdim 1866249259Sdimdefm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR, 1867249259Sdim (mul (i64 (sext i32:$Rn)), (sext i32:$Rm))>; 1868249259Sdimdefm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR, 1869249259Sdim (sub 0, (mul (i64 (sext i32:$Rn)), (sext i32:$Rm)))>; 1870249259Sdim 1871249259Sdimdefm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR, 1872249259Sdim (mul (i64 (zext i32:$Rn)), (zext i32:$Rm))>; 1873249259Sdimdefm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR, 1874249259Sdim (sub 0, (mul (i64 (zext i32:$Rn)), (zext i32:$Rm)))>; 1875249259Sdim 1876249259Sdim 1877249259Sdim//===----------------------------------------------------------------------===// 1878249259Sdim// Exception generation 1879249259Sdim//===----------------------------------------------------------------------===// 1880249259Sdim// Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3 1881249259Sdim 1882249259Sdimdef uimm16_asmoperand : AsmOperandClass { 1883249259Sdim let Name = "UImm16"; 1884249259Sdim let PredicateMethod = "isUImm<16>"; 1885249259Sdim let RenderMethod = "addImmOperands"; 1886249259Sdim let DiagnosticType = "UImm16"; 1887249259Sdim} 1888249259Sdim 1889249259Sdimdef uimm16 : Operand<i32> { 1890249259Sdim let ParserMatchClass = uimm16_asmoperand; 1891249259Sdim} 1892249259Sdim 1893249259Sdimclass A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop> 1894249259Sdim : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16), 1895249259Sdim !strconcat(asmop, "\t$UImm16"), [], NoItinerary> { 1896249259Sdim let isBranch = 1; 1897249259Sdim let isTerminator = 1; 1898249259Sdim} 1899249259Sdim 1900249259Sdimdef SVCi : A64I_exceptImpl<0b000, 0b01, "svc">; 1901249259Sdimdef HVCi : A64I_exceptImpl<0b000, 0b10, "hvc">; 1902249259Sdimdef SMCi : A64I_exceptImpl<0b000, 0b11, "smc">; 1903249259Sdimdef BRKi : A64I_exceptImpl<0b001, 0b00, "brk">; 1904249259Sdimdef HLTi : A64I_exceptImpl<0b010, 0b00, "hlt">; 1905249259Sdim 1906249259Sdimdef DCPS1i : A64I_exceptImpl<0b101, 0b01, "dcps1">; 1907249259Sdimdef DCPS2i : A64I_exceptImpl<0b101, 0b10, "dcps2">; 1908249259Sdimdef DCPS3i : A64I_exceptImpl<0b101, 0b11, "dcps3">; 1909249259Sdim 1910249259Sdim// The immediate is optional for the DCPS instructions, defaulting to 0. 1911249259Sdimdef : InstAlias<"dcps1", (DCPS1i 0)>; 1912249259Sdimdef : InstAlias<"dcps2", (DCPS2i 0)>; 1913249259Sdimdef : InstAlias<"dcps3", (DCPS3i 0)>; 1914249259Sdim 1915249259Sdim//===----------------------------------------------------------------------===// 1916249259Sdim// Extract (immediate) 1917249259Sdim//===----------------------------------------------------------------------===// 1918249259Sdim// Contains: EXTR + alias ROR 1919249259Sdim 1920249259Sdimdef EXTRwwwi : A64I_extract<0b0, 0b000, 0b0, 1921249259Sdim (outs GPR32:$Rd), 1922249259Sdim (ins GPR32:$Rn, GPR32:$Rm, bitfield32_imm:$LSB), 1923249259Sdim "extr\t$Rd, $Rn, $Rm, $LSB", 1924249259Sdim [(set i32:$Rd, 1925249259Sdim (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))], 1926249259Sdim NoItinerary>; 1927249259Sdimdef EXTRxxxi : A64I_extract<0b1, 0b000, 0b1, 1928249259Sdim (outs GPR64:$Rd), 1929249259Sdim (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB), 1930249259Sdim "extr\t$Rd, $Rn, $Rm, $LSB", 1931249259Sdim [(set i64:$Rd, 1932249259Sdim (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))], 1933249259Sdim NoItinerary>; 1934249259Sdim 1935249259Sdimdef : InstAlias<"ror $Rd, $Rs, $LSB", 1936249259Sdim (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>; 1937249259Sdimdef : InstAlias<"ror $Rd, $Rs, $LSB", 1938249259Sdim (EXTRxxxi GPR64:$Rd, GPR64:$Rs, GPR64:$Rs, bitfield64_imm:$LSB)>; 1939249259Sdim 1940249259Sdimdef : Pat<(rotr i32:$Rn, bitfield32_imm:$LSB), 1941249259Sdim (EXTRwwwi $Rn, $Rn, bitfield32_imm:$LSB)>; 1942249259Sdimdef : Pat<(rotr i64:$Rn, bitfield64_imm:$LSB), 1943249259Sdim (EXTRxxxi $Rn, $Rn, bitfield64_imm:$LSB)>; 1944249259Sdim 1945249259Sdim//===----------------------------------------------------------------------===// 1946249259Sdim// Floating-point compare instructions 1947249259Sdim//===----------------------------------------------------------------------===// 1948249259Sdim// Contains: FCMP, FCMPE 1949249259Sdim 1950249259Sdimdef fpzero_asmoperand : AsmOperandClass { 1951249259Sdim let Name = "FPZero"; 1952249259Sdim let ParserMethod = "ParseFPImmOperand"; 1953249259Sdim let DiagnosticType = "FPZero"; 1954249259Sdim} 1955249259Sdim 1956249259Sdimdef fpz32 : Operand<f32>, 1957249259Sdim ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> { 1958249259Sdim let ParserMatchClass = fpzero_asmoperand; 1959249259Sdim let PrintMethod = "printFPZeroOperand"; 1960249259Sdim let DecoderMethod = "DecodeFPZeroOperand"; 1961249259Sdim} 1962249259Sdim 1963249259Sdimdef fpz64 : Operand<f64>, 1964249259Sdim ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> { 1965249259Sdim let ParserMatchClass = fpzero_asmoperand; 1966249259Sdim let PrintMethod = "printFPZeroOperand"; 1967249259Sdim let DecoderMethod = "DecodeFPZeroOperand"; 1968249259Sdim} 1969249259Sdim 1970249259Sdimmulticlass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, dag pattern> { 1971249259Sdim def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0}, 1972249259Sdim (outs), ins, "fcmp\t$Rn, $Rm", [pattern], 1973249259Sdim NoItinerary> { 1974249259Sdim let Defs = [NZCV]; 1975249259Sdim } 1976249259Sdim 1977249259Sdim def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0}, 1978249259Sdim (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> { 1979249259Sdim let Defs = [NZCV]; 1980249259Sdim } 1981249259Sdim} 1982249259Sdim 1983249259Sdimdefm FCMPss : A64I_fpcmpSignal<0b00, 0b0, (ins FPR32:$Rn, FPR32:$Rm), 1984249259Sdim (set NZCV, (A64cmp f32:$Rn, f32:$Rm))>; 1985249259Sdimdefm FCMPdd : A64I_fpcmpSignal<0b01, 0b0, (ins FPR64:$Rn, FPR64:$Rm), 1986249259Sdim (set NZCV, (A64cmp f64:$Rn, f64:$Rm))>; 1987249259Sdim 1988249259Sdim// What would be Rm should be written as 0; note that even though it's called 1989249259Sdim// "$Rm" here to fit in with the InstrFormats, it's actually an immediate. 1990249259Sdimdefm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Rm), 1991249259Sdim (set NZCV, (A64cmp f32:$Rn, fpz32:$Rm))>; 1992249259Sdim 1993249259Sdimdefm FCMPdi : A64I_fpcmpSignal<0b01, 0b1, (ins FPR64:$Rn, fpz64:$Rm), 1994249259Sdim (set NZCV, (A64cmp f64:$Rn, fpz64:$Rm))>; 1995249259Sdim 1996249259Sdim 1997249259Sdim//===----------------------------------------------------------------------===// 1998249259Sdim// Floating-point conditional compare instructions 1999249259Sdim//===----------------------------------------------------------------------===// 2000249259Sdim// Contains: FCCMP, FCCMPE 2001249259Sdim 2002249259Sdimclass A64I_fpccmpImpl<bits<2> type, bit op, RegisterClass FPR, string asmop> 2003249259Sdim : A64I_fpccmp<0b0, 0b0, type, op, 2004249259Sdim (outs), 2005249259Sdim (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond), 2006249259Sdim !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"), 2007249259Sdim [], NoItinerary> { 2008249259Sdim let Defs = [NZCV]; 2009249259Sdim} 2010249259Sdim 2011249259Sdimdef FCCMPss : A64I_fpccmpImpl<0b00, 0b0, FPR32, "fccmp">; 2012249259Sdimdef FCCMPEss : A64I_fpccmpImpl<0b00, 0b1, FPR32, "fccmpe">; 2013249259Sdimdef FCCMPdd : A64I_fpccmpImpl<0b01, 0b0, FPR64, "fccmp">; 2014249259Sdimdef FCCMPEdd : A64I_fpccmpImpl<0b01, 0b1, FPR64, "fccmpe">; 2015249259Sdim 2016249259Sdim//===----------------------------------------------------------------------===// 2017249259Sdim// Floating-point conditional select instructions 2018249259Sdim//===----------------------------------------------------------------------===// 2019249259Sdim// Contains: FCSEL 2020249259Sdim 2021249259Sdimlet Uses = [NZCV] in { 2022249259Sdim def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd), 2023249259Sdim (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond), 2024249259Sdim "fcsel\t$Rd, $Rn, $Rm, $Cond", 2025249259Sdim [(set f32:$Rd, 2026249259Sdim (simple_select f32:$Rn, f32:$Rm))], 2027249259Sdim NoItinerary>; 2028249259Sdim 2029249259Sdim 2030249259Sdim def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd), 2031249259Sdim (ins FPR64:$Rn, FPR64:$Rm, cond_code_op:$Cond), 2032249259Sdim "fcsel\t$Rd, $Rn, $Rm, $Cond", 2033249259Sdim [(set f64:$Rd, 2034249259Sdim (simple_select f64:$Rn, f64:$Rm))], 2035249259Sdim NoItinerary>; 2036249259Sdim} 2037249259Sdim 2038249259Sdim//===----------------------------------------------------------------------===// 2039249259Sdim// Floating-point data-processing (1 source) 2040249259Sdim//===----------------------------------------------------------------------===// 2041249259Sdim// Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI]. 2042249259Sdim 2043249259Sdimdef FPNoUnop : PatFrag<(ops node:$val), (fneg node:$val), 2044249259Sdim [{ (void)N; return false; }]>; 2045249259Sdim 2046249259Sdim// First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d" 2047249259Sdim// syntax. Default to no pattern because most are odd enough not to have one. 2048249259Sdimmulticlass A64I_fpdp1sizes<bits<6> opcode, string asmstr, 2049249259Sdim SDPatternOperator opnode = FPNoUnop> { 2050249259Sdim def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn), 2051249259Sdim !strconcat(asmstr, "\t$Rd, $Rn"), 2052249259Sdim [(set f32:$Rd, (opnode f32:$Rn))], 2053249259Sdim NoItinerary>; 2054249259Sdim 2055249259Sdim def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn), 2056249259Sdim !strconcat(asmstr, "\t$Rd, $Rn"), 2057249259Sdim [(set f64:$Rd, (opnode f64:$Rn))], 2058249259Sdim NoItinerary>; 2059249259Sdim} 2060249259Sdim 2061249259Sdimdefm FMOV : A64I_fpdp1sizes<0b000000, "fmov">; 2062249259Sdimdefm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>; 2063249259Sdimdefm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>; 2064249259Sdimdefm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>; 2065249259Sdim 2066249259Sdimdefm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">; 2067249259Sdimdefm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>; 2068249259Sdimdefm FRINTM : A64I_fpdp1sizes<0b001010, "frintm", ffloor>; 2069249259Sdimdefm FRINTZ : A64I_fpdp1sizes<0b001011, "frintz", ftrunc>; 2070249259Sdimdefm FRINTA : A64I_fpdp1sizes<0b001100, "frinta">; 2071249259Sdimdefm FRINTX : A64I_fpdp1sizes<0b001110, "frintx", frint>; 2072249259Sdimdefm FRINTI : A64I_fpdp1sizes<0b001111, "frinti", fnearbyint>; 2073249259Sdim 2074249259Sdim// The FCVT instrucitons have different source and destination register-types, 2075249259Sdim// but the fields are uniform everywhere a D-register (say) crops up. Package 2076249259Sdim// this information in a Record. 2077249259Sdimclass FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> { 2078249259Sdim RegisterClass Class = rc; 2079249259Sdim ValueType VT = vt; 2080249259Sdim bit t1 = fld{1}; 2081249259Sdim bit t0 = fld{0}; 2082249259Sdim} 2083249259Sdim 2084249259Sdimdef FCVT16 : FCVTRegType<FPR16, 0b11, f16>; 2085249259Sdimdef FCVT32 : FCVTRegType<FPR32, 0b00, f32>; 2086249259Sdimdef FCVT64 : FCVTRegType<FPR64, 0b01, f64>; 2087249259Sdim 2088249259Sdimclass A64I_fpdp1_fcvt<FCVTRegType DestReg, FCVTRegType SrcReg, SDNode opnode> 2089249259Sdim : A64I_fpdp1<0b0, 0b0, {SrcReg.t1, SrcReg.t0}, 2090249259Sdim {0,0,0,1, DestReg.t1, DestReg.t0}, 2091249259Sdim (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn), 2092249259Sdim "fcvt\t$Rd, $Rn", 2093249259Sdim [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>; 2094249259Sdim 2095249259Sdimdef FCVTds : A64I_fpdp1_fcvt<FCVT64, FCVT32, fextend>; 2096249259Sdimdef FCVThs : A64I_fpdp1_fcvt<FCVT16, FCVT32, fround>; 2097249259Sdimdef FCVTsd : A64I_fpdp1_fcvt<FCVT32, FCVT64, fround>; 2098249259Sdimdef FCVThd : A64I_fpdp1_fcvt<FCVT16, FCVT64, fround>; 2099249259Sdimdef FCVTsh : A64I_fpdp1_fcvt<FCVT32, FCVT16, fextend>; 2100249259Sdimdef FCVTdh : A64I_fpdp1_fcvt<FCVT64, FCVT16, fextend>; 2101249259Sdim 2102249259Sdim 2103249259Sdim//===----------------------------------------------------------------------===// 2104249259Sdim// Floating-point data-processing (2 sources) instructions 2105249259Sdim//===----------------------------------------------------------------------===// 2106249259Sdim// Contains: FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL 2107249259Sdim 2108249259Sdimdef FPNoBinop : PatFrag<(ops node:$lhs, node:$rhs), (fadd node:$lhs, node:$rhs), 2109249259Sdim [{ (void)N; return false; }]>; 2110249259Sdim 2111249259Sdimmulticlass A64I_fpdp2sizes<bits<4> opcode, string asmstr, 2112249259Sdim SDPatternOperator opnode> { 2113249259Sdim def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode, 2114249259Sdim (outs FPR32:$Rd), 2115249259Sdim (ins FPR32:$Rn, FPR32:$Rm), 2116249259Sdim !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2117249259Sdim [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))], 2118249259Sdim NoItinerary>; 2119249259Sdim 2120249259Sdim def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode, 2121249259Sdim (outs FPR64:$Rd), 2122249259Sdim (ins FPR64:$Rn, FPR64:$Rm), 2123249259Sdim !strconcat(asmstr, "\t$Rd, $Rn, $Rm"), 2124249259Sdim [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))], 2125249259Sdim NoItinerary>; 2126249259Sdim} 2127249259Sdim 2128249259Sdimlet isCommutable = 1 in { 2129249259Sdim defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>; 2130249259Sdim defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>; 2131249259Sdim 2132249259Sdim // No patterns for these. 2133249259Sdim defm FMAX : A64I_fpdp2sizes<0b0100, "fmax", FPNoBinop>; 2134249259Sdim defm FMIN : A64I_fpdp2sizes<0b0101, "fmin", FPNoBinop>; 2135249259Sdim defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>; 2136249259Sdim defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>; 2137249259Sdim 2138249259Sdim defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul", 2139249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 2140249259Sdim (fneg (fmul node:$lhs, node:$rhs))> >; 2141249259Sdim} 2142249259Sdim 2143249259Sdimdefm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>; 2144249259Sdimdefm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>; 2145249259Sdim 2146249259Sdim//===----------------------------------------------------------------------===// 2147249259Sdim// Floating-point data-processing (3 sources) instructions 2148249259Sdim//===----------------------------------------------------------------------===// 2149249259Sdim// Contains: FMADD, FMSUB, FNMADD, FNMSUB 2150249259Sdim 2151249259Sdimdef fmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2152249259Sdim (fma (fneg node:$Rn), node:$Rm, node:$Ra)>; 2153249259Sdimdef fnmadd : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2154249259Sdim (fma node:$Rn, node:$Rm, (fneg node:$Ra))>; 2155249259Sdimdef fnmsub : PatFrag<(ops node:$Rn, node:$Rm, node:$Ra), 2156249259Sdim (fma (fneg node:$Rn), node:$Rm, (fneg node:$Ra))>; 2157249259Sdim 2158249259Sdimclass A64I_fpdp3Impl<string asmop, RegisterClass FPR, ValueType VT, 2159249259Sdim bits<2> type, bit o1, bit o0, SDPatternOperator fmakind> 2160249259Sdim : A64I_fpdp3<0b0, 0b0, type, o1, o0, (outs FPR:$Rd), 2161249259Sdim (ins FPR:$Rn, FPR:$Rm, FPR:$Ra), 2162249259Sdim !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"), 2163249259Sdim [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))], 2164249259Sdim NoItinerary>; 2165249259Sdim 2166249259Sdimdef FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>; 2167249259Sdimdef FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>; 2168249259Sdimdef FNMADDssss : A64I_fpdp3Impl<"fnmadd", FPR32, f32, 0b00, 0b1, 0b0, fnmadd>; 2169249259Sdimdef FNMSUBssss : A64I_fpdp3Impl<"fnmsub", FPR32, f32, 0b00, 0b1, 0b1, fnmsub>; 2170249259Sdim 2171249259Sdimdef FMADDdddd : A64I_fpdp3Impl<"fmadd", FPR64, f64, 0b01, 0b0, 0b0, fma>; 2172249259Sdimdef FMSUBdddd : A64I_fpdp3Impl<"fmsub", FPR64, f64, 0b01, 0b0, 0b1, fmsub>; 2173249259Sdimdef FNMADDdddd : A64I_fpdp3Impl<"fnmadd", FPR64, f64, 0b01, 0b1, 0b0, fnmadd>; 2174249259Sdimdef FNMSUBdddd : A64I_fpdp3Impl<"fnmsub", FPR64, f64, 0b01, 0b1, 0b1, fnmsub>; 2175249259Sdim 2176249259Sdim//===----------------------------------------------------------------------===// 2177249259Sdim// Floating-point <-> fixed-point conversion instructions 2178249259Sdim//===----------------------------------------------------------------------===// 2179249259Sdim// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2180249259Sdim 2181249259Sdim// #1-#32 allowed, encoded as "64 - <specified imm> 2182249259Sdimdef fixedpos_asmoperand_i32 : AsmOperandClass { 2183249259Sdim let Name = "CVTFixedPos32"; 2184249259Sdim let RenderMethod = "addCVTFixedPosOperands"; 2185249259Sdim let PredicateMethod = "isCVTFixedPos<32>"; 2186249259Sdim let DiagnosticType = "CVTFixedPos32"; 2187249259Sdim} 2188249259Sdim 2189249259Sdim// Also encoded as "64 - <specified imm>" but #1-#64 allowed. 2190249259Sdimdef fixedpos_asmoperand_i64 : AsmOperandClass { 2191249259Sdim let Name = "CVTFixedPos64"; 2192249259Sdim let RenderMethod = "addCVTFixedPosOperands"; 2193249259Sdim let PredicateMethod = "isCVTFixedPos<64>"; 2194249259Sdim let DiagnosticType = "CVTFixedPos64"; 2195249259Sdim} 2196249259Sdim 2197249259Sdim// We need the cartesian product of f32/f64 i32/i64 operands for 2198249259Sdim// conversions: 2199249259Sdim// + Selection needs to use operands of correct floating type 2200249259Sdim// + Assembly parsing and decoding depend on integer width 2201249259Sdimclass cvtfix_i32_op<ValueType FloatVT> 2202249259Sdim : Operand<FloatVT>, 2203249259Sdim ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> { 2204249259Sdim let ParserMatchClass = fixedpos_asmoperand_i32; 2205249259Sdim let DecoderMethod = "DecodeCVT32FixedPosOperand"; 2206249259Sdim let PrintMethod = "printCVTFixedPosOperand"; 2207249259Sdim} 2208249259Sdim 2209249259Sdimclass cvtfix_i64_op<ValueType FloatVT> 2210249259Sdim : Operand<FloatVT>, 2211249259Sdim ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> { 2212249259Sdim let ParserMatchClass = fixedpos_asmoperand_i64; 2213249259Sdim let PrintMethod = "printCVTFixedPosOperand"; 2214249259Sdim} 2215249259Sdim 2216249259Sdim// Because of the proliferation of weird operands, it's not really 2217249259Sdim// worth going for a multiclass here. Oh well. 2218249259Sdim 2219249259Sdimclass A64I_fptofix<bit sf, bits<2> type, bits<3> opcode, 2220249259Sdim RegisterClass GPR, RegisterClass FPR, 2221249259Sdim ValueType DstTy, ValueType SrcTy, 2222249259Sdim Operand scale_op, string asmop, SDNode cvtop> 2223249259Sdim : A64I_fpfixed<sf, 0b0, type, 0b11, opcode, 2224249259Sdim (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale), 2225249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2226249259Sdim [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))], 2227249259Sdim NoItinerary>; 2228249259Sdim 2229249259Sdimdef FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32, 2230249259Sdim cvtfix_i32_op<f32>, "fcvtzs", fp_to_sint>; 2231249259Sdimdef FCVTZSxsi : A64I_fptofix<0b1, 0b00, 0b000, GPR64, FPR32, i64, f32, 2232249259Sdim cvtfix_i64_op<f32>, "fcvtzs", fp_to_sint>; 2233249259Sdimdef FCVTZUwsi : A64I_fptofix<0b0, 0b00, 0b001, GPR32, FPR32, i32, f32, 2234249259Sdim cvtfix_i32_op<f32>, "fcvtzu", fp_to_uint>; 2235249259Sdimdef FCVTZUxsi : A64I_fptofix<0b1, 0b00, 0b001, GPR64, FPR32, i64, f32, 2236249259Sdim cvtfix_i64_op<f32>, "fcvtzu", fp_to_uint>; 2237249259Sdim 2238249259Sdimdef FCVTZSwdi : A64I_fptofix<0b0, 0b01, 0b000, GPR32, FPR64, i32, f64, 2239249259Sdim cvtfix_i32_op<f64>, "fcvtzs", fp_to_sint>; 2240249259Sdimdef FCVTZSxdi : A64I_fptofix<0b1, 0b01, 0b000, GPR64, FPR64, i64, f64, 2241249259Sdim cvtfix_i64_op<f64>, "fcvtzs", fp_to_sint>; 2242249259Sdimdef FCVTZUwdi : A64I_fptofix<0b0, 0b01, 0b001, GPR32, FPR64, i32, f64, 2243249259Sdim cvtfix_i32_op<f64>, "fcvtzu", fp_to_uint>; 2244249259Sdimdef FCVTZUxdi : A64I_fptofix<0b1, 0b01, 0b001, GPR64, FPR64, i64, f64, 2245249259Sdim cvtfix_i64_op<f64>, "fcvtzu", fp_to_uint>; 2246249259Sdim 2247249259Sdim 2248249259Sdimclass A64I_fixtofp<bit sf, bits<2> type, bits<3> opcode, 2249249259Sdim RegisterClass FPR, RegisterClass GPR, 2250249259Sdim ValueType DstTy, ValueType SrcTy, 2251249259Sdim Operand scale_op, string asmop, SDNode cvtop> 2252249259Sdim : A64I_fpfixed<sf, 0b0, type, 0b00, opcode, 2253249259Sdim (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale), 2254249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Scale"), 2255249259Sdim [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))], 2256249259Sdim NoItinerary>; 2257249259Sdim 2258249259Sdimdef SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32, 2259249259Sdim cvtfix_i32_op<f32>, "scvtf", sint_to_fp>; 2260249259Sdimdef SCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b010, FPR32, GPR64, f32, i64, 2261249259Sdim cvtfix_i64_op<f32>, "scvtf", sint_to_fp>; 2262249259Sdimdef UCVTFswi : A64I_fixtofp<0b0, 0b00, 0b011, FPR32, GPR32, f32, i32, 2263249259Sdim cvtfix_i32_op<f32>, "ucvtf", uint_to_fp>; 2264249259Sdimdef UCVTFsxi : A64I_fixtofp<0b1, 0b00, 0b011, FPR32, GPR64, f32, i64, 2265249259Sdim cvtfix_i64_op<f32>, "ucvtf", uint_to_fp>; 2266249259Sdimdef SCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b010, FPR64, GPR32, f64, i32, 2267249259Sdim cvtfix_i32_op<f64>, "scvtf", sint_to_fp>; 2268249259Sdimdef SCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b010, FPR64, GPR64, f64, i64, 2269249259Sdim cvtfix_i64_op<f64>, "scvtf", sint_to_fp>; 2270249259Sdimdef UCVTFdwi : A64I_fixtofp<0b0, 0b01, 0b011, FPR64, GPR32, f64, i32, 2271249259Sdim cvtfix_i32_op<f64>, "ucvtf", uint_to_fp>; 2272249259Sdimdef UCVTFdxi : A64I_fixtofp<0b1, 0b01, 0b011, FPR64, GPR64, f64, i64, 2273249259Sdim cvtfix_i64_op<f64>, "ucvtf", uint_to_fp>; 2274249259Sdim 2275249259Sdim//===----------------------------------------------------------------------===// 2276249259Sdim// Floating-point <-> integer conversion instructions 2277249259Sdim//===----------------------------------------------------------------------===// 2278249259Sdim// Contains: FCVTZS, FCVTZU, SCVTF, UCVTF 2279249259Sdim 2280249259Sdimclass A64I_fpintI<bit sf, bits<2> type, bits<2> rmode, bits<3> opcode, 2281249259Sdim RegisterClass DestPR, RegisterClass SrcPR, string asmop> 2282249259Sdim : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn), 2283249259Sdim !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>; 2284249259Sdim 2285249259Sdimmulticlass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> { 2286249259Sdim def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, 2287249259Sdim GPR32, FPR32, asmop # "s">; 2288249259Sdim def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, 2289249259Sdim GPR64, FPR32, asmop # "s">; 2290249259Sdim def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, 2291249259Sdim GPR32, FPR32, asmop # "u">; 2292249259Sdim def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, 2293249259Sdim GPR64, FPR32, asmop # "u">; 2294249259Sdim 2295249259Sdim def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, 2296249259Sdim GPR32, FPR64, asmop # "s">; 2297249259Sdim def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, 2298249259Sdim GPR64, FPR64, asmop # "s">; 2299249259Sdim def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, 2300249259Sdim GPR32, FPR64, asmop # "u">; 2301249259Sdim def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, 2302249259Sdim GPR64, FPR64, asmop # "u">; 2303249259Sdim} 2304249259Sdim 2305249259Sdimdefm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">; 2306249259Sdimdefm FCVTP : A64I_fptointRM<0b01, 0b0, "fcvtp">; 2307249259Sdimdefm FCVTM : A64I_fptointRM<0b10, 0b0, "fcvtm">; 2308249259Sdimdefm FCVTZ : A64I_fptointRM<0b11, 0b0, "fcvtz">; 2309249259Sdimdefm FCVTA : A64I_fptointRM<0b00, 0b1, "fcvta">; 2310249259Sdim 2311249259Sdimdef : Pat<(i32 (fp_to_sint f32:$Rn)), (FCVTZSws $Rn)>; 2312249259Sdimdef : Pat<(i64 (fp_to_sint f32:$Rn)), (FCVTZSxs $Rn)>; 2313249259Sdimdef : Pat<(i32 (fp_to_uint f32:$Rn)), (FCVTZUws $Rn)>; 2314249259Sdimdef : Pat<(i64 (fp_to_uint f32:$Rn)), (FCVTZUxs $Rn)>; 2315249259Sdimdef : Pat<(i32 (fp_to_sint f64:$Rn)), (FCVTZSwd $Rn)>; 2316249259Sdimdef : Pat<(i64 (fp_to_sint f64:$Rn)), (FCVTZSxd $Rn)>; 2317249259Sdimdef : Pat<(i32 (fp_to_uint f64:$Rn)), (FCVTZUwd $Rn)>; 2318249259Sdimdef : Pat<(i64 (fp_to_uint f64:$Rn)), (FCVTZUxd $Rn)>; 2319249259Sdim 2320249259Sdimmulticlass A64I_inttofp<bit o0, string asmop> { 2321249259Sdim def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>; 2322249259Sdim def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>; 2323249259Sdim def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>; 2324249259Sdim def CVTFdx : A64I_fpintI<0b1, 0b01, 0b00, {0, 1, o0}, FPR64, GPR64, asmop>; 2325249259Sdim} 2326249259Sdim 2327249259Sdimdefm S : A64I_inttofp<0b0, "scvtf">; 2328249259Sdimdefm U : A64I_inttofp<0b1, "ucvtf">; 2329249259Sdim 2330249259Sdimdef : Pat<(f32 (sint_to_fp i32:$Rn)), (SCVTFsw $Rn)>; 2331249259Sdimdef : Pat<(f32 (sint_to_fp i64:$Rn)), (SCVTFsx $Rn)>; 2332249259Sdimdef : Pat<(f64 (sint_to_fp i32:$Rn)), (SCVTFdw $Rn)>; 2333249259Sdimdef : Pat<(f64 (sint_to_fp i64:$Rn)), (SCVTFdx $Rn)>; 2334249259Sdimdef : Pat<(f32 (uint_to_fp i32:$Rn)), (UCVTFsw $Rn)>; 2335249259Sdimdef : Pat<(f32 (uint_to_fp i64:$Rn)), (UCVTFsx $Rn)>; 2336249259Sdimdef : Pat<(f64 (uint_to_fp i32:$Rn)), (UCVTFdw $Rn)>; 2337249259Sdimdef : Pat<(f64 (uint_to_fp i64:$Rn)), (UCVTFdx $Rn)>; 2338249259Sdim 2339249259Sdimdef FMOVws : A64I_fpintI<0b0, 0b00, 0b00, 0b110, GPR32, FPR32, "fmov">; 2340249259Sdimdef FMOVsw : A64I_fpintI<0b0, 0b00, 0b00, 0b111, FPR32, GPR32, "fmov">; 2341249259Sdimdef FMOVxd : A64I_fpintI<0b1, 0b01, 0b00, 0b110, GPR64, FPR64, "fmov">; 2342249259Sdimdef FMOVdx : A64I_fpintI<0b1, 0b01, 0b00, 0b111, FPR64, GPR64, "fmov">; 2343249259Sdim 2344249259Sdimdef : Pat<(i32 (bitconvert f32:$Rn)), (FMOVws $Rn)>; 2345249259Sdimdef : Pat<(f32 (bitconvert i32:$Rn)), (FMOVsw $Rn)>; 2346249259Sdimdef : Pat<(i64 (bitconvert f64:$Rn)), (FMOVxd $Rn)>; 2347249259Sdimdef : Pat<(f64 (bitconvert i64:$Rn)), (FMOVdx $Rn)>; 2348249259Sdim 2349249259Sdimdef lane1_asmoperand : AsmOperandClass { 2350249259Sdim let Name = "Lane1"; 2351249259Sdim let RenderMethod = "addImmOperands"; 2352249259Sdim let DiagnosticType = "Lane1"; 2353249259Sdim} 2354249259Sdim 2355249259Sdimdef lane1 : Operand<i32> { 2356249259Sdim let ParserMatchClass = lane1_asmoperand; 2357249259Sdim let PrintMethod = "printBareImmOperand"; 2358249259Sdim} 2359249259Sdim 2360249259Sdimlet DecoderMethod = "DecodeFMOVLaneInstruction" in { 2361249259Sdim def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110, 2362249259Sdim (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane), 2363249259Sdim "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>; 2364249259Sdim 2365249259Sdim def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111, 2366249259Sdim (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane), 2367249259Sdim "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>; 2368249259Sdim} 2369249259Sdim 2370249259Sdimdef : InstAlias<"fmov $Rd, $Rn.2d[$Lane]", 2371249259Sdim (FMOVxv GPR64:$Rd, VPR128:$Rn, lane1:$Lane), 0b0>; 2372249259Sdim 2373249259Sdimdef : InstAlias<"fmov $Rd.2d[$Lane], $Rn", 2374249259Sdim (FMOVvx VPR128:$Rd, GPR64:$Rn, lane1:$Lane), 0b0>; 2375249259Sdim 2376249259Sdim//===----------------------------------------------------------------------===// 2377249259Sdim// Floating-point immediate instructions 2378249259Sdim//===----------------------------------------------------------------------===// 2379249259Sdim// Contains: FMOV 2380249259Sdim 2381249259Sdimdef fpimm_asmoperand : AsmOperandClass { 2382249259Sdim let Name = "FMOVImm"; 2383249259Sdim let ParserMethod = "ParseFPImmOperand"; 2384249259Sdim let DiagnosticType = "FPImm"; 2385249259Sdim} 2386249259Sdim 2387249259Sdim// The MCOperand for these instructions are the encoded 8-bit values. 2388249259Sdimdef SDXF_fpimm : SDNodeXForm<fpimm, [{ 2389249259Sdim uint32_t Imm8; 2390249259Sdim A64Imms::isFPImm(N->getValueAPF(), Imm8); 2391249259Sdim return CurDAG->getTargetConstant(Imm8, MVT::i32); 2392249259Sdim}]>; 2393249259Sdim 2394249259Sdimclass fmov_operand<ValueType FT> 2395249259Sdim : Operand<i32>, 2396249259Sdim PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }], 2397249259Sdim SDXF_fpimm> { 2398249259Sdim let PrintMethod = "printFPImmOperand"; 2399249259Sdim let ParserMatchClass = fpimm_asmoperand; 2400249259Sdim} 2401249259Sdim 2402249259Sdimdef fmov32_operand : fmov_operand<f32>; 2403249259Sdimdef fmov64_operand : fmov_operand<f64>; 2404249259Sdim 2405249259Sdimclass A64I_fpimm_impl<bits<2> type, RegisterClass Reg, ValueType VT, 2406249259Sdim Operand fmov_operand> 2407249259Sdim : A64I_fpimm<0b0, 0b0, type, 0b00000, 2408249259Sdim (outs Reg:$Rd), 2409249259Sdim (ins fmov_operand:$Imm8), 2410249259Sdim "fmov\t$Rd, $Imm8", 2411249259Sdim [(set VT:$Rd, fmov_operand:$Imm8)], 2412249259Sdim NoItinerary>; 2413249259Sdim 2414249259Sdimdef FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>; 2415249259Sdimdef FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>; 2416249259Sdim 2417249259Sdim//===----------------------------------------------------------------------===// 2418249259Sdim// Load-register (literal) instructions 2419249259Sdim//===----------------------------------------------------------------------===// 2420249259Sdim// Contains: LDR, LDRSW, PRFM 2421249259Sdim 2422249259Sdimdef ldrlit_label_asmoperand : AsmOperandClass { 2423249259Sdim let Name = "LoadLitLabel"; 2424249259Sdim let RenderMethod = "addLabelOperands<19, 4>"; 2425249259Sdim let DiagnosticType = "Label"; 2426249259Sdim} 2427249259Sdim 2428249259Sdimdef ldrlit_label : Operand<i64> { 2429249259Sdim let EncoderMethod = "getLoadLitLabelOpValue"; 2430249259Sdim 2431249259Sdim // This label is a 19-bit offset from PC, scaled by the instruction-width: 4. 2432249259Sdim let PrintMethod = "printLabelOperand<19, 4>"; 2433249259Sdim let ParserMatchClass = ldrlit_label_asmoperand; 2434249259Sdim let OperandType = "OPERAND_PCREL"; 2435249259Sdim} 2436249259Sdim 2437249259Sdim// Various instructions take an immediate value (which can always be used), 2438249259Sdim// where some numbers have a symbolic name to make things easier. These operands 2439249259Sdim// and the associated functions abstract away the differences. 2440249259Sdimmulticlass namedimm<string prefix, string mapper> { 2441249259Sdim def _asmoperand : AsmOperandClass { 2442249259Sdim let Name = "NamedImm" # prefix; 2443249259Sdim let PredicateMethod = "isUImm"; 2444249259Sdim let RenderMethod = "addImmOperands"; 2445249259Sdim let ParserMethod = "ParseNamedImmOperand<" # mapper # ">"; 2446249259Sdim let DiagnosticType = "NamedImm_" # prefix; 2447249259Sdim } 2448249259Sdim 2449249259Sdim def _op : Operand<i32> { 2450249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 2451249259Sdim let PrintMethod = "printNamedImmOperand<" # mapper # ">"; 2452249259Sdim let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">"; 2453249259Sdim } 2454249259Sdim} 2455249259Sdim 2456249259Sdimdefm prefetch : namedimm<"prefetch", "A64PRFM::PRFMMapper">; 2457249259Sdim 2458249259Sdimclass A64I_LDRlitSimple<bits<2> opc, bit v, RegisterClass OutReg, 2459249259Sdim list<dag> patterns = []> 2460249259Sdim : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19), 2461249259Sdim "ldr\t$Rt, $Imm19", patterns, NoItinerary>; 2462249259Sdim 2463249259Sdimlet mayLoad = 1 in { 2464249259Sdim def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>; 2465249259Sdim def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>; 2466249259Sdim} 2467249259Sdim 2468249259Sdimdef LDRs_lit : A64I_LDRlitSimple<0b00, 0b1, FPR32>; 2469249259Sdimdef LDRd_lit : A64I_LDRlitSimple<0b01, 0b1, FPR64>; 2470249259Sdim 2471249259Sdimlet mayLoad = 1 in { 2472249259Sdim def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>; 2473249259Sdim 2474249259Sdim 2475249259Sdim def LDRSWx_lit : A64I_LDRlit<0b10, 0b0, 2476249259Sdim (outs GPR64:$Rt), 2477249259Sdim (ins ldrlit_label:$Imm19), 2478249259Sdim "ldrsw\t$Rt, $Imm19", 2479249259Sdim [], NoItinerary>; 2480249259Sdim 2481249259Sdim def PRFM_lit : A64I_LDRlit<0b11, 0b0, 2482249259Sdim (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19), 2483249259Sdim "prfm\t$Rt, $Imm19", 2484249259Sdim [], NoItinerary>; 2485249259Sdim} 2486249259Sdim 2487249259Sdim//===----------------------------------------------------------------------===// 2488249259Sdim// Load-store exclusive instructions 2489249259Sdim//===----------------------------------------------------------------------===// 2490249259Sdim// Contains: STXRB, STXRH, STXR, LDXRB, LDXRH, LDXR. STXP, LDXP, STLXRB, 2491249259Sdim// STLXRH, STLXR, LDAXRB, LDAXRH, LDAXR, STLXP, LDAXP, STLRB, 2492249259Sdim// STLRH, STLR, LDARB, LDARH, LDAR 2493249259Sdim 2494249259Sdim// Since these instructions have the undefined register bits set to 1 in 2495249259Sdim// their canonical form, we need a post encoder method to set those bits 2496249259Sdim// to 1 when encoding these instructions. We do this using the 2497249259Sdim// fixLoadStoreExclusive function. This function has template parameters: 2498249259Sdim// 2499249259Sdim// fixLoadStoreExclusive<int hasRs, int hasRt2> 2500249259Sdim// 2501249259Sdim// hasRs indicates that the instruction uses the Rs field, so we won't set 2502249259Sdim// it to 1 (and the same for Rt2). We don't need template parameters for 2503249259Sdim// the other register fiels since Rt and Rn are always used. 2504249259Sdim 2505249259Sdim// This operand parses a GPR64xsp register, followed by an optional immediate 2506249259Sdim// #0. 2507249259Sdimdef GPR64xsp0_asmoperand : AsmOperandClass { 2508249259Sdim let Name = "GPR64xsp0"; 2509249259Sdim let PredicateMethod = "isWrappedReg"; 2510249259Sdim let RenderMethod = "addRegOperands"; 2511249259Sdim let ParserMethod = "ParseLSXAddressOperand"; 2512249259Sdim // Diagnostics are provided by ParserMethod 2513249259Sdim} 2514249259Sdim 2515249259Sdimdef GPR64xsp0 : RegisterOperand<GPR64xsp> { 2516249259Sdim let ParserMatchClass = GPR64xsp0_asmoperand; 2517249259Sdim} 2518249259Sdim 2519249259Sdim//===---------------------------------- 2520249259Sdim// Store-exclusive (releasing & normal) 2521249259Sdim//===---------------------------------- 2522249259Sdim 2523249259Sdimclass A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2524249259Sdim dag ins, list<dag> pat, 2525249259Sdim InstrItinClass itin> : 2526249259Sdim A64I_LDSTex_stn <size, 2527249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2528249259Sdim outs, ins, 2529249259Sdim !strconcat(asm, "\t$Rs, $Rt, [$Rn]"), 2530249259Sdim pat, itin> { 2531249259Sdim let mayStore = 1; 2532249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; 2533249259Sdim} 2534249259Sdim 2535249259Sdimmulticlass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { 2536249259Sdim def _byte: A64I_SRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2537249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2538249259Sdim [], NoItinerary>; 2539249259Sdim 2540249259Sdim def _hword: A64I_SRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2541249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2542249259Sdim [],NoItinerary>; 2543249259Sdim 2544249259Sdim def _word: A64I_SRexs_impl<0b10, opcode, asmstr, 2545249259Sdim (outs GPR32:$Rs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2546249259Sdim [], NoItinerary>; 2547249259Sdim 2548249259Sdim def _dword: A64I_SRexs_impl<0b11, opcode, asmstr, 2549249259Sdim (outs GPR32:$Rs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2550249259Sdim [], NoItinerary>; 2551249259Sdim} 2552249259Sdim 2553249259Sdimdefm STXR : A64I_SRex<"stxr", 0b000, "STXR">; 2554249259Sdimdefm STLXR : A64I_SRex<"stlxr", 0b001, "STLXR">; 2555249259Sdim 2556249259Sdim//===---------------------------------- 2557249259Sdim// Loads 2558249259Sdim//===---------------------------------- 2559249259Sdim 2560249259Sdimclass A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2561249259Sdim dag ins, list<dag> pat, 2562249259Sdim InstrItinClass itin> : 2563249259Sdim A64I_LDSTex_tn <size, 2564249259Sdim opcode{2}, 1, opcode{1}, opcode{0}, 2565249259Sdim outs, ins, 2566249259Sdim !strconcat(asm, "\t$Rt, [$Rn]"), 2567249259Sdim pat, itin> { 2568249259Sdim let mayLoad = 1; 2569249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2570249259Sdim} 2571249259Sdim 2572249259Sdimmulticlass A64I_LRex<string asmstr, bits<3> opcode> { 2573249259Sdim def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2574249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2575249259Sdim [], NoItinerary>; 2576249259Sdim 2577249259Sdim def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2578249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2579249259Sdim [], NoItinerary>; 2580249259Sdim 2581249259Sdim def _word: A64I_LRexs_impl<0b10, opcode, asmstr, 2582249259Sdim (outs GPR32:$Rt), (ins GPR64xsp0:$Rn), 2583249259Sdim [], NoItinerary>; 2584249259Sdim 2585249259Sdim def _dword: A64I_LRexs_impl<0b11, opcode, asmstr, 2586249259Sdim (outs GPR64:$Rt), (ins GPR64xsp0:$Rn), 2587249259Sdim [], NoItinerary>; 2588249259Sdim} 2589249259Sdim 2590249259Sdimdefm LDXR : A64I_LRex<"ldxr", 0b000>; 2591249259Sdimdefm LDAXR : A64I_LRex<"ldaxr", 0b001>; 2592249259Sdimdefm LDAR : A64I_LRex<"ldar", 0b101>; 2593249259Sdim 2594249259Sdimclass acquiring_load<PatFrag base> 2595249259Sdim : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 2596251662Sdim AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2597251662Sdim return Ordering == Acquire || Ordering == SequentiallyConsistent; 2598249259Sdim}]>; 2599249259Sdim 2600249259Sdimdef atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 2601249259Sdimdef atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 2602249259Sdimdef atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 2603249259Sdimdef atomic_load_acquire_64 : acquiring_load<atomic_load_64>; 2604249259Sdim 2605249259Sdimdef : Pat<(atomic_load_acquire_8 i64:$Rn), (LDAR_byte $Rn)>; 2606249259Sdimdef : Pat<(atomic_load_acquire_16 i64:$Rn), (LDAR_hword $Rn)>; 2607249259Sdimdef : Pat<(atomic_load_acquire_32 i64:$Rn), (LDAR_word $Rn)>; 2608249259Sdimdef : Pat<(atomic_load_acquire_64 i64:$Rn), (LDAR_dword $Rn)>; 2609249259Sdim 2610249259Sdim//===---------------------------------- 2611249259Sdim// Store-release (no exclusivity) 2612249259Sdim//===---------------------------------- 2613249259Sdim 2614249259Sdimclass A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2615249259Sdim dag ins, list<dag> pat, 2616249259Sdim InstrItinClass itin> : 2617249259Sdim A64I_LDSTex_tn <size, 2618249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2619249259Sdim outs, ins, 2620249259Sdim !strconcat(asm, "\t$Rt, [$Rn]"), 2621249259Sdim pat, itin> { 2622249259Sdim let mayStore = 1; 2623249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,0>"; 2624249259Sdim} 2625249259Sdim 2626249259Sdimclass releasing_store<PatFrag base> 2627249259Sdim : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 2628251662Sdim AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 2629251662Sdim return Ordering == Release || Ordering == SequentiallyConsistent; 2630249259Sdim}]>; 2631249259Sdim 2632249259Sdimdef atomic_store_release_8 : releasing_store<atomic_store_8>; 2633249259Sdimdef atomic_store_release_16 : releasing_store<atomic_store_16>; 2634249259Sdimdef atomic_store_release_32 : releasing_store<atomic_store_32>; 2635249259Sdimdef atomic_store_release_64 : releasing_store<atomic_store_64>; 2636249259Sdim 2637249259Sdimmulticlass A64I_SLex<string asmstr, bits<3> opcode, string prefix> { 2638249259Sdim def _byte: A64I_SLexs_impl<0b00, opcode, !strconcat(asmstr, "b"), 2639249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2640249259Sdim [(atomic_store_release_8 i64:$Rn, i32:$Rt)], 2641249259Sdim NoItinerary>; 2642249259Sdim 2643249259Sdim def _hword: A64I_SLexs_impl<0b01, opcode, !strconcat(asmstr, "h"), 2644249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2645249259Sdim [(atomic_store_release_16 i64:$Rn, i32:$Rt)], 2646249259Sdim NoItinerary>; 2647249259Sdim 2648249259Sdim def _word: A64I_SLexs_impl<0b10, opcode, asmstr, 2649249259Sdim (outs), (ins GPR32:$Rt, GPR64xsp0:$Rn), 2650249259Sdim [(atomic_store_release_32 i64:$Rn, i32:$Rt)], 2651249259Sdim NoItinerary>; 2652249259Sdim 2653249259Sdim def _dword: A64I_SLexs_impl<0b11, opcode, asmstr, 2654249259Sdim (outs), (ins GPR64:$Rt, GPR64xsp0:$Rn), 2655249259Sdim [(atomic_store_release_64 i64:$Rn, i64:$Rt)], 2656249259Sdim NoItinerary>; 2657249259Sdim} 2658249259Sdim 2659249259Sdimdefm STLR : A64I_SLex<"stlr", 0b101, "STLR">; 2660249259Sdim 2661249259Sdim//===---------------------------------- 2662249259Sdim// Store-exclusive pair (releasing & normal) 2663249259Sdim//===---------------------------------- 2664249259Sdim 2665249259Sdimclass A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2666249259Sdim dag ins, list<dag> pat, 2667249259Sdim InstrItinClass itin> : 2668249259Sdim A64I_LDSTex_stt2n <size, 2669249259Sdim opcode{2}, 0, opcode{1}, opcode{0}, 2670249259Sdim outs, ins, 2671249259Sdim !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"), 2672249259Sdim pat, itin> { 2673249259Sdim let mayStore = 1; 2674249259Sdim} 2675249259Sdim 2676249259Sdim 2677249259Sdimmulticlass A64I_SPex<string asmstr, bits<3> opcode> { 2678249259Sdim def _word: A64I_SPexs_impl<0b10, opcode, asmstr, (outs), 2679249259Sdim (ins GPR32:$Rs, GPR32:$Rt, GPR32:$Rt2, 2680249259Sdim GPR64xsp0:$Rn), 2681249259Sdim [], NoItinerary>; 2682249259Sdim 2683249259Sdim def _dword: A64I_SPexs_impl<0b11, opcode, asmstr, (outs), 2684249259Sdim (ins GPR32:$Rs, GPR64:$Rt, GPR64:$Rt2, 2685249259Sdim GPR64xsp0:$Rn), 2686249259Sdim [], NoItinerary>; 2687249259Sdim} 2688249259Sdim 2689249259Sdimdefm STXP : A64I_SPex<"stxp", 0b010>; 2690249259Sdimdefm STLXP : A64I_SPex<"stlxp", 0b011>; 2691249259Sdim 2692249259Sdim//===---------------------------------- 2693249259Sdim// Load-exclusive pair (acquiring & normal) 2694249259Sdim//===---------------------------------- 2695249259Sdim 2696249259Sdimclass A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, 2697249259Sdim dag ins, list<dag> pat, 2698249259Sdim InstrItinClass itin> : 2699249259Sdim A64I_LDSTex_tt2n <size, 2700249259Sdim opcode{2}, 1, opcode{1}, opcode{0}, 2701249259Sdim outs, ins, 2702249259Sdim !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"), 2703249259Sdim pat, itin>{ 2704249259Sdim let mayLoad = 1; 2705249259Sdim let DecoderMethod = "DecodeLoadPairExclusiveInstruction"; 2706249259Sdim let PostEncoderMethod = "fixLoadStoreExclusive<0,1>"; 2707249259Sdim} 2708249259Sdim 2709249259Sdimmulticlass A64I_LPex<string asmstr, bits<3> opcode> { 2710249259Sdim def _word: A64I_LPexs_impl<0b10, opcode, asmstr, 2711249259Sdim (outs GPR32:$Rt, GPR32:$Rt2), 2712249259Sdim (ins GPR64xsp0:$Rn), 2713249259Sdim [], NoItinerary>; 2714249259Sdim 2715249259Sdim def _dword: A64I_LPexs_impl<0b11, opcode, asmstr, 2716249259Sdim (outs GPR64:$Rt, GPR64:$Rt2), 2717249259Sdim (ins GPR64xsp0:$Rn), 2718249259Sdim [], NoItinerary>; 2719249259Sdim} 2720249259Sdim 2721249259Sdimdefm LDXP : A64I_LPex<"ldxp", 0b010>; 2722249259Sdimdefm LDAXP : A64I_LPex<"ldaxp", 0b011>; 2723249259Sdim 2724249259Sdim//===----------------------------------------------------------------------===// 2725249259Sdim// Load-store register (unscaled immediate) instructions 2726249259Sdim//===----------------------------------------------------------------------===// 2727249259Sdim// Contains: LDURB, LDURH, LDRUSB, LDRUSH, LDRUSW, STUR, STURB, STURH and PRFUM 2728249259Sdim// 2729249259Sdim// and 2730249259Sdim// 2731249259Sdim//===----------------------------------------------------------------------===// 2732249259Sdim// Load-store register (register offset) instructions 2733249259Sdim//===----------------------------------------------------------------------===// 2734249259Sdim// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2735249259Sdim// 2736249259Sdim// and 2737249259Sdim// 2738249259Sdim//===----------------------------------------------------------------------===// 2739249259Sdim// Load-store register (unsigned immediate) instructions 2740249259Sdim//===----------------------------------------------------------------------===// 2741249259Sdim// Contains: LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH and PRFM 2742249259Sdim// 2743249259Sdim// and 2744249259Sdim// 2745249259Sdim//===----------------------------------------------------------------------===// 2746249259Sdim// Load-store register (immediate post-indexed) instructions 2747249259Sdim//===----------------------------------------------------------------------===// 2748249259Sdim// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2749249259Sdim// 2750249259Sdim// and 2751249259Sdim// 2752249259Sdim//===----------------------------------------------------------------------===// 2753249259Sdim// Load-store register (immediate pre-indexed) instructions 2754249259Sdim//===----------------------------------------------------------------------===// 2755249259Sdim// Contains: STRB, STRH, STR, LDRB, LDRH, LDR, LDRSB, LDRSH, LDRSW 2756249259Sdim 2757249259Sdim// Note that patterns are much later on in a completely separate section (they 2758249259Sdim// need ADRPxi to be defined). 2759249259Sdim 2760249259Sdim//===------------------------------- 2761249259Sdim// 1. Various operands needed 2762249259Sdim//===------------------------------- 2763249259Sdim 2764249259Sdim//===------------------------------- 2765249259Sdim// 1.1 Unsigned 12-bit immediate operands 2766249259Sdim//===------------------------------- 2767249259Sdim// The addressing mode for these instructions consists of an unsigned 12-bit 2768249259Sdim// immediate which is scaled by the size of the memory access. 2769249259Sdim// 2770249259Sdim// We represent this in the MC layer by two operands: 2771249259Sdim// 1. A base register. 2772249259Sdim// 2. A 12-bit immediate: not multiplied by access size, so "LDR x0,[x0,#8]" 2773249259Sdim// would have '1' in this field. 2774249259Sdim// This means that separate functions are needed for converting representations 2775249259Sdim// which *are* aware of the intended access size. 2776249259Sdim 2777249259Sdim// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 2778249259Sdim// know the access size via some means. An isolated operand does not have this 2779249259Sdim// information unless told from here, which means we need separate tablegen 2780249259Sdim// Operands for each access size. This multiclass takes care of instantiating 2781249259Sdim// the correct template functions in the rest of the backend. 2782249259Sdim 2783249259Sdim//===------------------------------- 2784249259Sdim// 1.1 Unsigned 12-bit immediate operands 2785249259Sdim//===------------------------------- 2786249259Sdim 2787249259Sdimmulticlass offsets_uimm12<int MemSize, string prefix> { 2788249259Sdim def uimm12_asmoperand : AsmOperandClass { 2789249259Sdim let Name = "OffsetUImm12_" # MemSize; 2790249259Sdim let PredicateMethod = "isOffsetUImm12<" # MemSize # ">"; 2791249259Sdim let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">"; 2792249259Sdim let DiagnosticType = "LoadStoreUImm12_" # MemSize; 2793249259Sdim } 2794249259Sdim 2795249259Sdim // Pattern is really no more than an ImmLeaf, but predicated on MemSize which 2796249259Sdim // complicates things beyond TableGen's ken. 2797249259Sdim def uimm12 : Operand<i64>, 2798249259Sdim ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> { 2799249259Sdim let ParserMatchClass 2800249259Sdim = !cast<AsmOperandClass>(prefix # uimm12_asmoperand); 2801249259Sdim 2802249259Sdim let PrintMethod = "printOffsetUImm12Operand<" # MemSize # ">"; 2803249259Sdim let EncoderMethod = "getOffsetUImm12OpValue<" # MemSize # ">"; 2804249259Sdim } 2805249259Sdim} 2806249259Sdim 2807249259Sdimdefm byte_ : offsets_uimm12<1, "byte_">; 2808249259Sdimdefm hword_ : offsets_uimm12<2, "hword_">; 2809249259Sdimdefm word_ : offsets_uimm12<4, "word_">; 2810249259Sdimdefm dword_ : offsets_uimm12<8, "dword_">; 2811249259Sdimdefm qword_ : offsets_uimm12<16, "qword_">; 2812249259Sdim 2813249259Sdim//===------------------------------- 2814249259Sdim// 1.1 Signed 9-bit immediate operands 2815249259Sdim//===------------------------------- 2816249259Sdim 2817249259Sdim// The MCInst is expected to store the bit-wise encoding of the value, 2818249259Sdim// which amounts to lopping off the extended sign bits. 2819249259Sdimdef SDXF_simm9 : SDNodeXForm<imm, [{ 2820249259Sdim return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32); 2821249259Sdim}]>; 2822249259Sdim 2823249259Sdimdef simm9_asmoperand : AsmOperandClass { 2824249259Sdim let Name = "SImm9"; 2825249259Sdim let PredicateMethod = "isSImm<9>"; 2826249259Sdim let RenderMethod = "addSImmOperands<9>"; 2827249259Sdim let DiagnosticType = "LoadStoreSImm9"; 2828249259Sdim} 2829249259Sdim 2830249259Sdimdef simm9 : Operand<i64>, 2831249259Sdim ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }], 2832249259Sdim SDXF_simm9> { 2833249259Sdim let PrintMethod = "printOffsetSImm9Operand"; 2834249259Sdim let ParserMatchClass = simm9_asmoperand; 2835249259Sdim} 2836249259Sdim 2837249259Sdim 2838249259Sdim//===------------------------------- 2839249259Sdim// 1.3 Register offset extensions 2840249259Sdim//===------------------------------- 2841249259Sdim 2842249259Sdim// The assembly-syntax for these addressing-modes is: 2843249259Sdim// [<Xn|SP>, <R><m> {, <extend> {<amount>}}] 2844249259Sdim// 2845249259Sdim// The essential semantics are: 2846249259Sdim// + <amount> is a shift: #<log(transfer size)> or #0 2847249259Sdim// + <R> can be W or X. 2848249259Sdim// + If <R> is W, <extend> can be UXTW or SXTW 2849249259Sdim// + If <R> is X, <extend> can be LSL or SXTX 2850249259Sdim// 2851249259Sdim// The trickiest of those constraints is that Rm can be either GPR32 or GPR64, 2852249259Sdim// which will need separate instructions for LLVM type-consistency. We'll also 2853249259Sdim// need separate operands, of course. 2854249259Sdimmulticlass regexts<int MemSize, int RmSize, RegisterClass GPR, 2855249259Sdim string Rm, string prefix> { 2856249259Sdim def regext_asmoperand : AsmOperandClass { 2857249259Sdim let Name = "AddrRegExtend_" # MemSize # "_" # Rm; 2858249259Sdim let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">"; 2859249259Sdim let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">"; 2860249259Sdim let DiagnosticType = "LoadStoreExtend" # RmSize # "_" # MemSize; 2861249259Sdim } 2862249259Sdim 2863249259Sdim def regext : Operand<i64> { 2864249259Sdim let PrintMethod 2865249259Sdim = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">"; 2866249259Sdim 2867249259Sdim let DecoderMethod = "DecodeAddrRegExtendOperand"; 2868249259Sdim let ParserMatchClass 2869249259Sdim = !cast<AsmOperandClass>(prefix # regext_asmoperand); 2870249259Sdim } 2871249259Sdim} 2872249259Sdim 2873249259Sdimmulticlass regexts_wx<int MemSize, string prefix> { 2874249259Sdim // Rm is an X-register if LSL or SXTX are specified as the shift. 2875249259Sdim defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">; 2876249259Sdim 2877249259Sdim // Rm is a W-register if UXTW or SXTW are specified as the shift. 2878249259Sdim defm Wm_ : regexts<MemSize, 32, GPR32, "Wm", prefix # "Wm_">; 2879249259Sdim} 2880249259Sdim 2881249259Sdimdefm byte_ : regexts_wx<1, "byte_">; 2882249259Sdimdefm hword_ : regexts_wx<2, "hword_">; 2883249259Sdimdefm word_ : regexts_wx<4, "word_">; 2884249259Sdimdefm dword_ : regexts_wx<8, "dword_">; 2885249259Sdimdefm qword_ : regexts_wx<16, "qword_">; 2886249259Sdim 2887249259Sdim 2888249259Sdim//===------------------------------ 2889249259Sdim// 2. The instructions themselves. 2890249259Sdim//===------------------------------ 2891249259Sdim 2892249259Sdim// We have the following instructions to implement: 2893249259Sdim// | | B | H | W | X | 2894249259Sdim// |-----------------+-------+-------+-------+--------| 2895249259Sdim// | unsigned str | STRB | STRH | STR | STR | 2896249259Sdim// | unsigned ldr | LDRB | LDRH | LDR | LDR | 2897249259Sdim// | signed ldr to W | LDRSB | LDRSH | - | - | 2898249259Sdim// | signed ldr to X | LDRSB | LDRSH | LDRSW | (PRFM) | 2899249259Sdim 2900249259Sdim// This will instantiate the LDR/STR instructions you'd expect to use for an 2901249259Sdim// unsigned datatype (first two rows above) or floating-point register, which is 2902249259Sdim// reasonably uniform across all access sizes. 2903249259Sdim 2904249259Sdim 2905249259Sdim//===------------------------------ 2906249259Sdim// 2.1 Regular instructions 2907249259Sdim//===------------------------------ 2908249259Sdim 2909249259Sdim// This class covers the basic unsigned or irrelevantly-signed loads and stores, 2910249259Sdim// to general-purpose and floating-point registers. 2911249259Sdim 2912249259Sdimclass AddrParams<string prefix> { 2913249259Sdim Operand uimm12 = !cast<Operand>(prefix # "_uimm12"); 2914249259Sdim 2915249259Sdim Operand regextWm = !cast<Operand>(prefix # "_Wm_regext"); 2916249259Sdim Operand regextXm = !cast<Operand>(prefix # "_Xm_regext"); 2917249259Sdim} 2918249259Sdim 2919249259Sdimdef byte_addrparams : AddrParams<"byte">; 2920249259Sdimdef hword_addrparams : AddrParams<"hword">; 2921249259Sdimdef word_addrparams : AddrParams<"word">; 2922249259Sdimdef dword_addrparams : AddrParams<"dword">; 2923249259Sdimdef qword_addrparams : AddrParams<"qword">; 2924249259Sdim 2925249259Sdimmulticlass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v, 2926249259Sdim bit high_opc, string asmsuffix, 2927249259Sdim RegisterClass GPR, AddrParams params> { 2928249259Sdim // Unsigned immediate 2929249259Sdim def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0}, 2930249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12), 2931249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2932249259Sdim [], NoItinerary> { 2933249259Sdim let mayStore = 1; 2934249259Sdim } 2935249259Sdim def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]", 2936249259Sdim (!cast<Instruction>(prefix # "_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2937249259Sdim 2938249259Sdim def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1}, 2939249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 2940249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]", 2941249259Sdim [], NoItinerary> { 2942249259Sdim let mayLoad = 1; 2943249259Sdim } 2944249259Sdim def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]", 2945249259Sdim (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2946249259Sdim 2947249259Sdim // Register offset (four of these: load/store and Wm/Xm). 2948249259Sdim let mayLoad = 1 in { 2949249259Sdim def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0, 2950249259Sdim (outs GPR:$Rt), 2951249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 2952249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2953249259Sdim [], NoItinerary>; 2954249259Sdim 2955249259Sdim def _Xm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b1, 2956249259Sdim (outs GPR:$Rt), 2957249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 2958249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2959249259Sdim [], NoItinerary>; 2960249259Sdim } 2961249259Sdim def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]", 2962249259Sdim (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn, 2963249259Sdim GPR64:$Rm, 2)>; 2964249259Sdim 2965249259Sdim let mayStore = 1 in { 2966249259Sdim def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0, 2967249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm, 2968249259Sdim params.regextWm:$Ext), 2969249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2970249259Sdim [], NoItinerary>; 2971249259Sdim 2972249259Sdim def _Xm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b1, 2973249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2974249259Sdim params.regextXm:$Ext), 2975249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]", 2976249259Sdim [], NoItinerary>; 2977249259Sdim } 2978249259Sdim def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn, $Rm]", 2979249259Sdim (!cast<Instruction>(prefix # "_Xm_RegOffset_STR") GPR:$Rt, GPR64xsp:$Rn, 2980249259Sdim GPR64:$Rm, 2)>; 2981249259Sdim 2982249259Sdim // Unaligned immediate 2983249259Sdim def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0}, 2984249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 2985249259Sdim "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 2986249259Sdim [], NoItinerary> { 2987249259Sdim let mayStore = 1; 2988249259Sdim } 2989249259Sdim def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]", 2990249259Sdim (!cast<Instruction>(prefix # "_STUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 2991249259Sdim 2992249259Sdim def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1}, 2993249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 2994249259Sdim "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 2995249259Sdim [], NoItinerary> { 2996249259Sdim let mayLoad = 1; 2997249259Sdim } 2998249259Sdim def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]", 2999249259Sdim (!cast<Instruction>(prefix # "_LDUR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3000249259Sdim 3001249259Sdim // Post-indexed 3002249259Sdim def _PostInd_STR : A64I_LSpostind<size, v, {high_opc, 0b0}, 3003249259Sdim (outs GPR64xsp:$Rn_wb), 3004249259Sdim (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3005249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3006249259Sdim [], NoItinerary> { 3007249259Sdim let Constraints = "$Rn = $Rn_wb"; 3008249259Sdim let mayStore = 1; 3009249259Sdim 3010249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3011249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3012249259Sdim } 3013249259Sdim 3014249259Sdim def _PostInd_LDR : A64I_LSpostind<size, v, {high_opc, 0b1}, 3015249259Sdim (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3016249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3017249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9", 3018249259Sdim [], NoItinerary> { 3019249259Sdim let mayLoad = 1; 3020249259Sdim let Constraints = "$Rn = $Rn_wb"; 3021249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3022249259Sdim } 3023249259Sdim 3024249259Sdim // Pre-indexed 3025249259Sdim def _PreInd_STR : A64I_LSpreind<size, v, {high_opc, 0b0}, 3026249259Sdim (outs GPR64xsp:$Rn_wb), 3027249259Sdim (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3028249259Sdim "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3029249259Sdim [], NoItinerary> { 3030249259Sdim let Constraints = "$Rn = $Rn_wb"; 3031249259Sdim let mayStore = 1; 3032249259Sdim 3033249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3034249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3035249259Sdim } 3036249259Sdim 3037249259Sdim def _PreInd_LDR : A64I_LSpreind<size, v, {high_opc, 0b1}, 3038249259Sdim (outs GPR:$Rt, GPR64xsp:$Rn_wb), 3039249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3040249259Sdim "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!", 3041249259Sdim [], NoItinerary> { 3042249259Sdim let mayLoad = 1; 3043249259Sdim let Constraints = "$Rn = $Rn_wb"; 3044249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3045249259Sdim } 3046249259Sdim 3047249259Sdim} 3048249259Sdim 3049249259Sdim// STRB/LDRB: First define the instructions 3050249259Sdimdefm LS8 3051249259Sdim : A64I_LDRSTR_unsigned<"LS8", 0b00, 0b0, 0b0, "b", GPR32, byte_addrparams>; 3052249259Sdim 3053249259Sdim// STRH/LDRH 3054249259Sdimdefm LS16 3055249259Sdim : A64I_LDRSTR_unsigned<"LS16", 0b01, 0b0, 0b0, "h", GPR32, hword_addrparams>; 3056249259Sdim 3057249259Sdim 3058249259Sdim// STR/LDR to/from a W register 3059249259Sdimdefm LS32 3060249259Sdim : A64I_LDRSTR_unsigned<"LS32", 0b10, 0b0, 0b0, "", GPR32, word_addrparams>; 3061249259Sdim 3062249259Sdim// STR/LDR to/from an X register 3063249259Sdimdefm LS64 3064249259Sdim : A64I_LDRSTR_unsigned<"LS64", 0b11, 0b0, 0b0, "", GPR64, dword_addrparams>; 3065249259Sdim 3066249259Sdim// STR/LDR to/from a B register 3067249259Sdimdefm LSFP8 3068249259Sdim : A64I_LDRSTR_unsigned<"LSFP8", 0b00, 0b1, 0b0, "", FPR8, byte_addrparams>; 3069249259Sdim 3070249259Sdim// STR/LDR to/from an H register 3071249259Sdimdefm LSFP16 3072249259Sdim : A64I_LDRSTR_unsigned<"LSFP16", 0b01, 0b1, 0b0, "", FPR16, hword_addrparams>; 3073249259Sdim 3074249259Sdim// STR/LDR to/from an S register 3075249259Sdimdefm LSFP32 3076249259Sdim : A64I_LDRSTR_unsigned<"LSFP32", 0b10, 0b1, 0b0, "", FPR32, word_addrparams>; 3077249259Sdim// STR/LDR to/from a D register 3078249259Sdimdefm LSFP64 3079249259Sdim : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>; 3080249259Sdim// STR/LDR to/from a Q register 3081249259Sdimdefm LSFP128 3082249259Sdim : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, 3083249259Sdim qword_addrparams>; 3084249259Sdim 3085249259Sdim//===------------------------------ 3086249259Sdim// 2.3 Signed loads 3087249259Sdim//===------------------------------ 3088249259Sdim 3089249259Sdim// Byte and half-word signed loads can both go into either an X or a W register, 3090249259Sdim// so it's worth factoring out. Signed word loads don't fit because there is no 3091249259Sdim// W version. 3092249259Sdimmulticlass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params, 3093249259Sdim string prefix> { 3094249259Sdim // Unsigned offset 3095249259Sdim def w : A64I_LSunsigimm<size, 0b0, 0b11, 3096249259Sdim (outs GPR32:$Rt), 3097249259Sdim (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3098249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3099249259Sdim [], NoItinerary> { 3100249259Sdim let mayLoad = 1; 3101249259Sdim } 3102249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3103249259Sdim (!cast<Instruction>(prefix # w) GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3104249259Sdim 3105249259Sdim def x : A64I_LSunsigimm<size, 0b0, 0b10, 3106249259Sdim (outs GPR64:$Rt), 3107249259Sdim (ins GPR64xsp:$Rn, params.uimm12:$UImm12), 3108249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]", 3109249259Sdim [], NoItinerary> { 3110249259Sdim let mayLoad = 1; 3111249259Sdim } 3112249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]", 3113249259Sdim (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3114249259Sdim 3115249259Sdim // Register offset 3116249259Sdim let mayLoad = 1 in { 3117249259Sdim def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0, 3118249259Sdim (outs GPR32:$Rt), 3119249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3120249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3121249259Sdim [], NoItinerary>; 3122249259Sdim 3123249259Sdim def w_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b1, 3124249259Sdim (outs GPR32:$Rt), 3125249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3126249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3127249259Sdim [], NoItinerary>; 3128249259Sdim 3129249259Sdim def x_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b0, 3130249259Sdim (outs GPR64:$Rt), 3131249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext), 3132249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3133249259Sdim [], NoItinerary>; 3134249259Sdim 3135249259Sdim def x_Xm_RegOffset : A64I_LSregoff<size, 0b0, 0b10, 0b1, 3136249259Sdim (outs GPR64:$Rt), 3137249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext), 3138249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]", 3139249259Sdim [], NoItinerary>; 3140249259Sdim } 3141249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3142249259Sdim (!cast<Instruction>(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn, 3143249259Sdim GPR64:$Rm, 2)>; 3144249259Sdim 3145249259Sdim def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]", 3146249259Sdim (!cast<Instruction>(prefix # "x_Xm_RegOffset") GPR64:$Rt, GPR64xsp:$Rn, 3147249259Sdim GPR64:$Rm, 2)>; 3148249259Sdim 3149249259Sdim 3150249259Sdim let mayLoad = 1 in { 3151249259Sdim // Unaligned offset 3152249259Sdim def w_U : A64I_LSunalimm<size, 0b0, 0b11, 3153249259Sdim (outs GPR32:$Rt), 3154249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3155249259Sdim "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3156249259Sdim [], NoItinerary>; 3157249259Sdim 3158249259Sdim def x_U : A64I_LSunalimm<size, 0b0, 0b10, 3159249259Sdim (outs GPR64:$Rt), 3160249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3161249259Sdim "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3162249259Sdim [], NoItinerary>; 3163249259Sdim 3164249259Sdim 3165249259Sdim // Post-indexed 3166249259Sdim def w_PostInd : A64I_LSpostind<size, 0b0, 0b11, 3167249259Sdim (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3168249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3169249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3170249259Sdim [], NoItinerary> { 3171249259Sdim let Constraints = "$Rn = $Rn_wb"; 3172249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3173249259Sdim } 3174249259Sdim 3175249259Sdim def x_PostInd : A64I_LSpostind<size, 0b0, 0b10, 3176249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3177249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3178249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9", 3179249259Sdim [], NoItinerary> { 3180249259Sdim let Constraints = "$Rn = $Rn_wb"; 3181249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3182249259Sdim } 3183249259Sdim 3184249259Sdim // Pre-indexed 3185249259Sdim def w_PreInd : A64I_LSpreind<size, 0b0, 0b11, 3186249259Sdim (outs GPR32:$Rt, GPR64xsp:$Rn_wb), 3187249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3188249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3189249259Sdim [], NoItinerary> { 3190249259Sdim let Constraints = "$Rn = $Rn_wb"; 3191249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3192249259Sdim } 3193249259Sdim 3194249259Sdim def x_PreInd : A64I_LSpreind<size, 0b0, 0b10, 3195249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3196249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3197249259Sdim "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!", 3198249259Sdim [], NoItinerary> { 3199249259Sdim let Constraints = "$Rn = $Rn_wb"; 3200249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3201249259Sdim } 3202249259Sdim } // let mayLoad = 1 3203249259Sdim} 3204249259Sdim 3205249259Sdim// LDRSB 3206249259Sdimdefm LDRSB : A64I_LDR_signed<0b00, "b", byte_addrparams, "LDRSB">; 3207249259Sdim// LDRSH 3208249259Sdimdefm LDRSH : A64I_LDR_signed<0b01, "h", hword_addrparams, "LDRSH">; 3209249259Sdim 3210249259Sdim// LDRSW: load a 32-bit register, sign-extending to 64-bits. 3211249259Sdimdef LDRSWx 3212249259Sdim : A64I_LSunsigimm<0b10, 0b0, 0b10, 3213249259Sdim (outs GPR64:$Rt), 3214249259Sdim (ins GPR64xsp:$Rn, word_uimm12:$UImm12), 3215249259Sdim "ldrsw\t$Rt, [$Rn, $UImm12]", 3216249259Sdim [], NoItinerary> { 3217249259Sdim let mayLoad = 1; 3218249259Sdim} 3219249259Sdimdef : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3220249259Sdim 3221249259Sdimlet mayLoad = 1 in { 3222249259Sdim def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0, 3223249259Sdim (outs GPR64:$Rt), 3224249259Sdim (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext), 3225249259Sdim "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3226249259Sdim [], NoItinerary>; 3227249259Sdim 3228249259Sdim def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1, 3229249259Sdim (outs GPR64:$Rt), 3230249259Sdim (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext), 3231249259Sdim "ldrsw\t$Rt, [$Rn, $Rm, $Ext]", 3232249259Sdim [], NoItinerary>; 3233249259Sdim} 3234249259Sdimdef : InstAlias<"ldrsw $Rt, [$Rn, $Rm]", 3235249259Sdim (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>; 3236249259Sdim 3237249259Sdim 3238249259Sdimdef LDURSWx 3239249259Sdim : A64I_LSunalimm<0b10, 0b0, 0b10, 3240249259Sdim (outs GPR64:$Rt), 3241249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3242249259Sdim "ldursw\t$Rt, [$Rn, $SImm9]", 3243249259Sdim [], NoItinerary> { 3244249259Sdim let mayLoad = 1; 3245249259Sdim} 3246249259Sdimdef : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3247249259Sdim 3248249259Sdimdef LDRSWx_PostInd 3249249259Sdim : A64I_LSpostind<0b10, 0b0, 0b10, 3250249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3251249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3252249259Sdim "ldrsw\t$Rt, [$Rn], $SImm9", 3253249259Sdim [], NoItinerary> { 3254249259Sdim let mayLoad = 1; 3255249259Sdim let Constraints = "$Rn = $Rn_wb"; 3256249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3257249259Sdim} 3258249259Sdim 3259249259Sdimdef LDRSWx_PreInd : A64I_LSpreind<0b10, 0b0, 0b10, 3260249259Sdim (outs GPR64:$Rt, GPR64xsp:$Rn_wb), 3261249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3262249259Sdim "ldrsw\t$Rt, [$Rn, $SImm9]!", 3263249259Sdim [], NoItinerary> { 3264249259Sdim let mayLoad = 1; 3265249259Sdim let Constraints = "$Rn = $Rn_wb"; 3266249259Sdim let DecoderMethod = "DecodeSingleIndexedInstruction"; 3267249259Sdim} 3268249259Sdim 3269249259Sdim//===------------------------------ 3270249259Sdim// 2.4 Prefetch operations 3271249259Sdim//===------------------------------ 3272249259Sdim 3273249259Sdimdef PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs), 3274249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12), 3275249259Sdim "prfm\t$Rt, [$Rn, $UImm12]", 3276249259Sdim [], NoItinerary> { 3277249259Sdim let mayLoad = 1; 3278249259Sdim} 3279249259Sdimdef : InstAlias<"prfm $Rt, [$Rn]", 3280249259Sdim (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3281249259Sdim 3282249259Sdimlet mayLoad = 1 in { 3283249259Sdim def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs), 3284249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3285249259Sdim GPR32:$Rm, dword_Wm_regext:$Ext), 3286249259Sdim "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3287249259Sdim [], NoItinerary>; 3288249259Sdim def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs), 3289249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, 3290249259Sdim GPR64:$Rm, dword_Xm_regext:$Ext), 3291249259Sdim "prfm\t$Rt, [$Rn, $Rm, $Ext]", 3292249259Sdim [], NoItinerary>; 3293249259Sdim} 3294249259Sdim 3295249259Sdimdef : InstAlias<"prfm $Rt, [$Rn, $Rm]", 3296249259Sdim (PRFM_Xm_RegOffset prefetch_op:$Rt, GPR64xsp:$Rn, 3297249259Sdim GPR64:$Rm, 2)>; 3298249259Sdim 3299249259Sdim 3300249259Sdimdef PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs), 3301249259Sdim (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3302249259Sdim "prfum\t$Rt, [$Rn, $SImm9]", 3303249259Sdim [], NoItinerary> { 3304249259Sdim let mayLoad = 1; 3305249259Sdim} 3306249259Sdimdef : InstAlias<"prfum $Rt, [$Rn]", 3307249259Sdim (PRFUM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>; 3308249259Sdim 3309249259Sdim//===----------------------------------------------------------------------===// 3310249259Sdim// Load-store register (unprivileged) instructions 3311249259Sdim//===----------------------------------------------------------------------===// 3312249259Sdim// Contains: LDTRB, LDTRH, LDTRSB, LDTRSH, LDTRSW, STTR, STTRB and STTRH 3313249259Sdim 3314249259Sdim// These instructions very much mirror the "unscaled immediate" loads, but since 3315249259Sdim// there are no floating-point variants we need to split them out into their own 3316249259Sdim// section to avoid instantiation of "ldtr d0, [sp]" etc. 3317249259Sdim 3318249259Sdimmulticlass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR, 3319249259Sdim string prefix> { 3320249259Sdim def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00, 3321249259Sdim (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9), 3322249259Sdim "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3323249259Sdim [], NoItinerary> { 3324249259Sdim let mayStore = 1; 3325249259Sdim } 3326249259Sdim 3327249259Sdim def : InstAlias<"sttr" # asmsuffix # " $Rt, [$Rn]", 3328249259Sdim (!cast<Instruction>(prefix # "_UnPriv_STR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3329249259Sdim 3330249259Sdim def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01, 3331249259Sdim (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9), 3332249259Sdim "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]", 3333249259Sdim [], NoItinerary> { 3334249259Sdim let mayLoad = 1; 3335249259Sdim } 3336249259Sdim 3337249259Sdim def : InstAlias<"ldtr" # asmsuffix # " $Rt, [$Rn]", 3338249259Sdim (!cast<Instruction>(prefix # "_UnPriv_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>; 3339249259Sdim 3340249259Sdim} 3341249259Sdim 3342249259Sdim// STTRB/LDTRB: First define the instructions 3343249259Sdimdefm LS8 : A64I_LDTRSTTR<0b00, "b", GPR32, "LS8">; 3344249259Sdim 3345249259Sdim// STTRH/LDTRH 3346249259Sdimdefm LS16 : A64I_LDTRSTTR<0b01, "h", GPR32, "LS16">; 3347249259Sdim 3348249259Sdim// STTR/LDTR to/from a W register 3349249259Sdimdefm LS32 : A64I_LDTRSTTR<0b10, "", GPR32, "LS32">; 3350249259Sdim 3351249259Sdim// STTR/LDTR to/from an X register 3352249259Sdimdefm LS64 : A64I_LDTRSTTR<0b11, "", GPR64, "LS64">; 3353249259Sdim 3354249259Sdim// Now a class for the signed instructions that can go to either 32 or 64 3355249259Sdim// bits... 3356249259Sdimmulticlass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> { 3357249259Sdim let mayLoad = 1 in { 3358249259Sdim def w : A64I_LSunpriv<size, 0b0, 0b11, 3359249259Sdim (outs GPR32:$Rt), 3360249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3361249259Sdim "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3362249259Sdim [], NoItinerary>; 3363249259Sdim 3364249259Sdim def x : A64I_LSunpriv<size, 0b0, 0b10, 3365249259Sdim (outs GPR64:$Rt), 3366249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3367249259Sdim "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]", 3368249259Sdim [], NoItinerary>; 3369249259Sdim } 3370249259Sdim 3371249259Sdim def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3372249259Sdim (!cast<Instruction>(prefix # "w") GPR32:$Rt, GPR64xsp:$Rn, 0)>; 3373249259Sdim 3374249259Sdim def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]", 3375249259Sdim (!cast<Instruction>(prefix # "x") GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3376249259Sdim 3377249259Sdim} 3378249259Sdim 3379249259Sdim// LDTRSB 3380249259Sdimdefm LDTRSB : A64I_LDTR_signed<0b00, "b", "LDTRSB">; 3381249259Sdim// LDTRSH 3382249259Sdimdefm LDTRSH : A64I_LDTR_signed<0b01, "h", "LDTRSH">; 3383249259Sdim 3384249259Sdim// And finally LDTRSW which only goes to 64 bits. 3385249259Sdimdef LDTRSWx : A64I_LSunpriv<0b10, 0b0, 0b10, 3386249259Sdim (outs GPR64:$Rt), 3387249259Sdim (ins GPR64xsp:$Rn, simm9:$SImm9), 3388249259Sdim "ldtrsw\t$Rt, [$Rn, $SImm9]", 3389249259Sdim [], NoItinerary> { 3390249259Sdim let mayLoad = 1; 3391249259Sdim} 3392249259Sdimdef : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>; 3393249259Sdim 3394249259Sdim//===----------------------------------------------------------------------===// 3395249259Sdim// Load-store register pair (offset) instructions 3396249259Sdim//===----------------------------------------------------------------------===// 3397249259Sdim// 3398249259Sdim// and 3399249259Sdim// 3400249259Sdim//===----------------------------------------------------------------------===// 3401249259Sdim// Load-store register pair (post-indexed) instructions 3402249259Sdim//===----------------------------------------------------------------------===// 3403249259Sdim// Contains: STP, LDP, LDPSW 3404249259Sdim// 3405249259Sdim// and 3406249259Sdim// 3407249259Sdim//===----------------------------------------------------------------------===// 3408249259Sdim// Load-store register pair (pre-indexed) instructions 3409249259Sdim//===----------------------------------------------------------------------===// 3410249259Sdim// Contains: STP, LDP, LDPSW 3411249259Sdim// 3412249259Sdim// and 3413249259Sdim// 3414249259Sdim//===----------------------------------------------------------------------===// 3415249259Sdim// Load-store non-temporal register pair (offset) instructions 3416249259Sdim//===----------------------------------------------------------------------===// 3417249259Sdim// Contains: STNP, LDNP 3418249259Sdim 3419249259Sdim 3420249259Sdim// Anything that creates an MCInst (Decoding, selection and AsmParsing) has to 3421249259Sdim// know the access size via some means. An isolated operand does not have this 3422249259Sdim// information unless told from here, which means we need separate tablegen 3423249259Sdim// Operands for each access size. This multiclass takes care of instantiating 3424249259Sdim// the correct template functions in the rest of the backend. 3425249259Sdim 3426249259Sdimmulticlass offsets_simm7<string MemSize, string prefix> { 3427249259Sdim // The bare signed 7-bit immediate is used in post-indexed instructions, but 3428249259Sdim // because of the scaling performed a generic "simm7" operand isn't 3429249259Sdim // appropriate here either. 3430249259Sdim def simm7_asmoperand : AsmOperandClass { 3431249259Sdim let Name = "SImm7_Scaled" # MemSize; 3432249259Sdim let PredicateMethod = "isSImm7Scaled<" # MemSize # ">"; 3433249259Sdim let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">"; 3434249259Sdim let DiagnosticType = "LoadStoreSImm7_" # MemSize; 3435249259Sdim } 3436249259Sdim 3437249259Sdim def simm7 : Operand<i64> { 3438249259Sdim let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">"; 3439249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand"); 3440249259Sdim } 3441249259Sdim} 3442249259Sdim 3443249259Sdimdefm word_ : offsets_simm7<"4", "word_">; 3444249259Sdimdefm dword_ : offsets_simm7<"8", "dword_">; 3445249259Sdimdefm qword_ : offsets_simm7<"16", "qword_">; 3446249259Sdim 3447249259Sdimmulticlass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg, 3448249259Sdim Operand simm7, string prefix> { 3449249259Sdim def _STR : A64I_LSPoffset<opc, v, 0b0, (outs), 3450249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3451249259Sdim "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3452249259Sdim let mayStore = 1; 3453249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3454249259Sdim } 3455249259Sdim def : InstAlias<"stp $Rt, $Rt2, [$Rn]", 3456249259Sdim (!cast<Instruction>(prefix # "_STR") SomeReg:$Rt, 3457249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3458249259Sdim 3459249259Sdim def _LDR : A64I_LSPoffset<opc, v, 0b1, 3460249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2), 3461249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3462249259Sdim "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3463249259Sdim let mayLoad = 1; 3464249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3465249259Sdim } 3466249259Sdim def : InstAlias<"ldp $Rt, $Rt2, [$Rn]", 3467249259Sdim (!cast<Instruction>(prefix # "_LDR") SomeReg:$Rt, 3468249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3469249259Sdim 3470249259Sdim def _PostInd_STR : A64I_LSPpostind<opc, v, 0b0, 3471249259Sdim (outs GPR64xsp:$Rn_wb), 3472249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, 3473249259Sdim GPR64xsp:$Rn, 3474249259Sdim simm7:$SImm7), 3475249259Sdim "stp\t$Rt, $Rt2, [$Rn], $SImm7", 3476249259Sdim [], NoItinerary> { 3477249259Sdim let mayStore = 1; 3478249259Sdim let Constraints = "$Rn = $Rn_wb"; 3479249259Sdim 3480249259Sdim // Decoder only needed for unpredictability checking (FIXME). 3481249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3482249259Sdim } 3483249259Sdim 3484249259Sdim def _PostInd_LDR : A64I_LSPpostind<opc, v, 0b1, 3485249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3486249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3487249259Sdim "ldp\t$Rt, $Rt2, [$Rn], $SImm7", 3488249259Sdim [], NoItinerary> { 3489249259Sdim let mayLoad = 1; 3490249259Sdim let Constraints = "$Rn = $Rn_wb"; 3491249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3492249259Sdim } 3493249259Sdim 3494249259Sdim def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb), 3495249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3496249259Sdim "stp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3497249259Sdim [], NoItinerary> { 3498249259Sdim let mayStore = 1; 3499249259Sdim let Constraints = "$Rn = $Rn_wb"; 3500249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3501249259Sdim } 3502249259Sdim 3503249259Sdim def _PreInd_LDR : A64I_LSPpreind<opc, v, 0b1, 3504249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb), 3505249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3506249259Sdim "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!", 3507249259Sdim [], NoItinerary> { 3508249259Sdim let mayLoad = 1; 3509249259Sdim let Constraints = "$Rn = $Rn_wb"; 3510249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3511249259Sdim } 3512249259Sdim 3513249259Sdim def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs), 3514249259Sdim (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7), 3515249259Sdim "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3516249259Sdim let mayStore = 1; 3517249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3518249259Sdim } 3519249259Sdim def : InstAlias<"stnp $Rt, $Rt2, [$Rn]", 3520249259Sdim (!cast<Instruction>(prefix # "_NonTemp_STR") SomeReg:$Rt, 3521249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3522249259Sdim 3523249259Sdim def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1, 3524249259Sdim (outs SomeReg:$Rt, SomeReg:$Rt2), 3525249259Sdim (ins GPR64xsp:$Rn, simm7:$SImm7), 3526249259Sdim "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3527249259Sdim let mayLoad = 1; 3528249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3529249259Sdim } 3530249259Sdim def : InstAlias<"ldnp $Rt, $Rt2, [$Rn]", 3531249259Sdim (!cast<Instruction>(prefix # "_NonTemp_LDR") SomeReg:$Rt, 3532249259Sdim SomeReg:$Rt2, GPR64xsp:$Rn, 0)>; 3533249259Sdim 3534249259Sdim} 3535249259Sdim 3536249259Sdim 3537249259Sdimdefm LSPair32 : A64I_LSPsimple<0b00, 0b0, GPR32, word_simm7, "LSPair32">; 3538249259Sdimdefm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">; 3539249259Sdimdefm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">; 3540249259Sdimdefm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64, dword_simm7, "LSFPPair64">; 3541249259Sdimdefm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, 3542249259Sdim "LSFPPair128">; 3543249259Sdim 3544249259Sdim 3545249259Sdimdef LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1, 3546249259Sdim (outs GPR64:$Rt, GPR64:$Rt2), 3547249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3548249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> { 3549249259Sdim let mayLoad = 1; 3550249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3551249259Sdim} 3552249259Sdimdef : InstAlias<"ldpsw $Rt, $Rt2, [$Rn]", 3553249259Sdim (LDPSWx GPR64:$Rt, GPR64:$Rt2, GPR64xsp:$Rn, 0)>; 3554249259Sdim 3555249259Sdimdef LDPSWx_PostInd : A64I_LSPpostind<0b01, 0b0, 0b1, 3556249259Sdim (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3557249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3558249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7", 3559249259Sdim [], NoItinerary> { 3560249259Sdim let mayLoad = 1; 3561249259Sdim let Constraints = "$Rn = $Rn_wb"; 3562249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3563249259Sdim} 3564249259Sdim 3565249259Sdimdef LDPSWx_PreInd : A64I_LSPpreind<0b01, 0b0, 0b1, 3566249259Sdim (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb), 3567249259Sdim (ins GPR64xsp:$Rn, word_simm7:$SImm7), 3568249259Sdim "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!", 3569249259Sdim [], NoItinerary> { 3570249259Sdim let mayLoad = 1; 3571249259Sdim let Constraints = "$Rn = $Rn_wb"; 3572249259Sdim let DecoderMethod = "DecodeLDSTPairInstruction"; 3573249259Sdim} 3574249259Sdim 3575249259Sdim//===----------------------------------------------------------------------===// 3576249259Sdim// Logical (immediate) instructions 3577249259Sdim//===----------------------------------------------------------------------===// 3578249259Sdim// Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV 3579249259Sdim 3580249259Sdimmulticlass logical_imm_operands<string prefix, string note, 3581249259Sdim int size, ValueType VT> { 3582249259Sdim def _asmoperand : AsmOperandClass { 3583249259Sdim let Name = "LogicalImm" # note # size; 3584249259Sdim let PredicateMethod = "isLogicalImm" # note # "<" # size # ">"; 3585249259Sdim let RenderMethod = "addLogicalImmOperands<" # size # ">"; 3586249259Sdim let DiagnosticType = "LogicalSecondSource"; 3587249259Sdim } 3588249259Sdim 3589249259Sdim def _operand 3590249259Sdim : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> { 3591249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3592249259Sdim let PrintMethod = "printLogicalImmOperand<" # size # ">"; 3593249259Sdim let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">"; 3594249259Sdim } 3595249259Sdim} 3596249259Sdim 3597249259Sdimdefm logical_imm32 : logical_imm_operands<"logical_imm32", "", 32, i32>; 3598249259Sdimdefm logical_imm64 : logical_imm_operands<"logical_imm64", "", 64, i64>; 3599249259Sdim 3600249259Sdim// The mov versions only differ in assembly parsing, where they 3601249259Sdim// exclude values representable with either MOVZ or MOVN. 3602249259Sdimdefm logical_imm32_mov 3603249259Sdim : logical_imm_operands<"logical_imm32_mov", "MOV", 32, i32>; 3604249259Sdimdefm logical_imm64_mov 3605249259Sdim : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>; 3606249259Sdim 3607249259Sdim 3608249259Sdimmulticlass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> { 3609249259Sdim def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd), 3610249259Sdim (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3611249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3612249259Sdim [(set i32:$Rd, 3613249259Sdim (opnode i32:$Rn, logical_imm32_operand:$Imm))], 3614249259Sdim NoItinerary>; 3615249259Sdim 3616249259Sdim def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd), 3617249259Sdim (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3618249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Imm"), 3619249259Sdim [(set i64:$Rd, 3620249259Sdim (opnode i64:$Rn, logical_imm64_operand:$Imm))], 3621249259Sdim NoItinerary>; 3622249259Sdim} 3623249259Sdim 3624249259Sdimdefm AND : A64I_logimmSizes<0b00, "and", and>; 3625249259Sdimdefm ORR : A64I_logimmSizes<0b01, "orr", or>; 3626249259Sdimdefm EOR : A64I_logimmSizes<0b10, "eor", xor>; 3627249259Sdim 3628249259Sdimlet Defs = [NZCV] in { 3629249259Sdim def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd), 3630249259Sdim (ins GPR32:$Rn, logical_imm32_operand:$Imm), 3631249259Sdim "ands\t$Rd, $Rn, $Imm", 3632249259Sdim [], NoItinerary>; 3633249259Sdim 3634249259Sdim def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd), 3635249259Sdim (ins GPR64:$Rn, logical_imm64_operand:$Imm), 3636249259Sdim "ands\t$Rd, $Rn, $Imm", 3637249259Sdim [], NoItinerary>; 3638249259Sdim} 3639249259Sdim 3640249259Sdim 3641249259Sdimdef : InstAlias<"tst $Rn, $Imm", 3642249259Sdim (ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>; 3643249259Sdimdef : InstAlias<"tst $Rn, $Imm", 3644249259Sdim (ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>; 3645249259Sdimdef : InstAlias<"mov $Rd, $Imm", 3646249259Sdim (ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>; 3647249259Sdimdef : InstAlias<"mov $Rd, $Imm", 3648249259Sdim (ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>; 3649249259Sdim 3650249259Sdim//===----------------------------------------------------------------------===// 3651249259Sdim// Logical (shifted register) instructions 3652249259Sdim//===----------------------------------------------------------------------===// 3653249259Sdim// Contains: AND, BIC, ORR, ORN, EOR, EON, ANDS, BICS + aliases TST, MVN, MOV 3654249259Sdim 3655249259Sdim// Operand for optimizing (icmp (and LHS, RHS), 0, SomeCode). In theory "ANDS" 3656249259Sdim// behaves differently for unsigned comparisons, so we defensively only allow 3657249259Sdim// signed or n/a as the operand. In practice "unsigned greater than 0" is "not 3658249259Sdim// equal to 0" and LLVM gives us this. 3659249259Sdimdef signed_cond : PatLeaf<(cond), [{ 3660249259Sdim return !isUnsignedIntSetCC(N->get()); 3661249259Sdim}]>; 3662249259Sdim 3663249259Sdim 3664249259Sdim// These instructions share their "shift" operands with add/sub (shifted 3665249259Sdim// register instructions). They are defined there. 3666249259Sdim 3667249259Sdim// N.b. the commutable parameter is just !N. It will be first against the wall 3668249259Sdim// when the revolution comes. 3669249259Sdimmulticlass logical_shifts<string prefix, bit sf, bits<2> opc, 3670249259Sdim bit N, bit commutable, 3671249259Sdim string asmop, SDPatternOperator opfrag, ValueType ty, 3672249259Sdim RegisterClass GPR, list<Register> defs> { 3673249259Sdim let isCommutable = commutable, Defs = defs in { 3674249259Sdim def _lsl : A64I_logicalshift<sf, opc, 0b00, N, 3675249259Sdim (outs GPR:$Rd), 3676249259Sdim (ins GPR:$Rn, GPR:$Rm, 3677249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3678249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3679249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm, 3680249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)) 3681249259Sdim )], 3682249259Sdim NoItinerary>; 3683249259Sdim 3684249259Sdim def _lsr : A64I_logicalshift<sf, opc, 0b01, N, 3685249259Sdim (outs GPR:$Rd), 3686249259Sdim (ins GPR:$Rn, GPR:$Rm, 3687249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3688249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3689249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm, 3690249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)) 3691249259Sdim )], 3692249259Sdim NoItinerary>; 3693249259Sdim 3694249259Sdim def _asr : A64I_logicalshift<sf, opc, 0b10, N, 3695249259Sdim (outs GPR:$Rd), 3696249259Sdim (ins GPR:$Rn, GPR:$Rm, 3697249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3698249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3699249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm, 3700249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)) 3701249259Sdim )], 3702249259Sdim NoItinerary>; 3703249259Sdim 3704249259Sdim def _ror : A64I_logicalshift<sf, opc, 0b11, N, 3705249259Sdim (outs GPR:$Rd), 3706249259Sdim (ins GPR:$Rn, GPR:$Rm, 3707249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3708249259Sdim !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Imm6"), 3709249259Sdim [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm, 3710249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6)) 3711249259Sdim )], 3712249259Sdim NoItinerary>; 3713249259Sdim } 3714249259Sdim 3715249259Sdim def _noshift 3716249259Sdim : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"), 3717249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rd, GPR:$Rn, 3718249259Sdim GPR:$Rm, 0)>; 3719249259Sdim 3720249259Sdim def : Pat<(opfrag ty:$Rn, ty:$Rm), 3721249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3722249259Sdim} 3723249259Sdim 3724249259Sdimmulticlass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable, 3725249259Sdim string asmop, SDPatternOperator opfrag, 3726249259Sdim list<Register> defs> { 3727249259Sdim defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N, 3728249259Sdim commutable, asmop, opfrag, i64, GPR64, defs>; 3729249259Sdim defm www : logical_shifts<prefix # "www", 0b0, opc, N, 3730249259Sdim commutable, asmop, opfrag, i32, GPR32, defs>; 3731249259Sdim} 3732249259Sdim 3733249259Sdim 3734249259Sdimdefm AND : logical_sizes<"AND", 0b00, 0b0, 0b1, "and", and, []>; 3735249259Sdimdefm ORR : logical_sizes<"ORR", 0b01, 0b0, 0b1, "orr", or, []>; 3736249259Sdimdefm EOR : logical_sizes<"EOR", 0b10, 0b0, 0b1, "eor", xor, []>; 3737249259Sdimdefm ANDS : logical_sizes<"ANDS", 0b11, 0b0, 0b1, "ands", 3738249259Sdim PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), 3739249259Sdim [{ (void)N; return false; }]>, 3740249259Sdim [NZCV]>; 3741249259Sdim 3742249259Sdimdefm BIC : logical_sizes<"BIC", 0b00, 0b1, 0b0, "bic", 3743249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3744249259Sdim (and node:$lhs, (not node:$rhs))>, []>; 3745249259Sdimdefm ORN : logical_sizes<"ORN", 0b01, 0b1, 0b0, "orn", 3746249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3747249259Sdim (or node:$lhs, (not node:$rhs))>, []>; 3748249259Sdimdefm EON : logical_sizes<"EON", 0b10, 0b1, 0b0, "eon", 3749249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3750249259Sdim (xor node:$lhs, (not node:$rhs))>, []>; 3751249259Sdimdefm BICS : logical_sizes<"BICS", 0b11, 0b1, 0b0, "bics", 3752249259Sdim PatFrag<(ops node:$lhs, node:$rhs), 3753249259Sdim (and node:$lhs, (not node:$rhs)), 3754249259Sdim [{ (void)N; return false; }]>, 3755249259Sdim [NZCV]>; 3756249259Sdim 3757249259Sdimmulticlass tst_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3758249259Sdim let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in { 3759249259Sdim def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0, 3760249259Sdim (outs), 3761249259Sdim (ins GPR:$Rn, GPR:$Rm, 3762249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3763249259Sdim "tst\t$Rn, $Rm, $Imm6", 3764249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm, 3765249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)), 3766249259Sdim 0, signed_cond))], 3767249259Sdim NoItinerary>; 3768249259Sdim 3769249259Sdim 3770249259Sdim def _lsr : A64I_logicalshift<sf, 0b11, 0b01, 0b0, 3771249259Sdim (outs), 3772249259Sdim (ins GPR:$Rn, GPR:$Rm, 3773249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3774249259Sdim "tst\t$Rn, $Rm, $Imm6", 3775249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm, 3776249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)), 3777249259Sdim 0, signed_cond))], 3778249259Sdim NoItinerary>; 3779249259Sdim 3780249259Sdim def _asr : A64I_logicalshift<sf, 0b11, 0b10, 0b0, 3781249259Sdim (outs), 3782249259Sdim (ins GPR:$Rn, GPR:$Rm, 3783249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3784249259Sdim "tst\t$Rn, $Rm, $Imm6", 3785249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm, 3786249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)), 3787249259Sdim 0, signed_cond))], 3788249259Sdim NoItinerary>; 3789249259Sdim 3790249259Sdim def _ror : A64I_logicalshift<sf, 0b11, 0b11, 0b0, 3791249259Sdim (outs), 3792249259Sdim (ins GPR:$Rn, GPR:$Rm, 3793249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3794249259Sdim "tst\t$Rn, $Rm, $Imm6", 3795249259Sdim [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm, 3796249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6)), 3797249259Sdim 0, signed_cond))], 3798249259Sdim NoItinerary>; 3799249259Sdim } 3800249259Sdim 3801249259Sdim def _noshift : InstAlias<"tst $Rn, $Rm", 3802249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3803249259Sdim 3804249259Sdim def : Pat<(A64setcc (and ty:$Rn, ty:$Rm), 0, signed_cond), 3805249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rn, $Rm, 0)>; 3806249259Sdim} 3807249259Sdim 3808249259Sdimdefm TSTxx : tst_shifts<"TSTxx", 0b1, i64, GPR64>; 3809249259Sdimdefm TSTww : tst_shifts<"TSTww", 0b0, i32, GPR32>; 3810249259Sdim 3811249259Sdim 3812249259Sdimmulticlass mvn_shifts<string prefix, bit sf, ValueType ty, RegisterClass GPR> { 3813249259Sdim let isCommutable = 0, Rn = 0b11111 in { 3814249259Sdim def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1, 3815249259Sdim (outs GPR:$Rd), 3816249259Sdim (ins GPR:$Rm, 3817249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6), 3818249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3819249259Sdim [(set ty:$Rd, (not (shl ty:$Rm, 3820249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3821249259Sdim NoItinerary>; 3822249259Sdim 3823249259Sdim 3824249259Sdim def _lsr : A64I_logicalshift<sf, 0b01, 0b01, 0b1, 3825249259Sdim (outs GPR:$Rd), 3826249259Sdim (ins GPR:$Rm, 3827249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6), 3828249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3829249259Sdim [(set ty:$Rd, (not (srl ty:$Rm, 3830249259Sdim !cast<Operand>("lsr_operand_" # ty):$Imm6)))], 3831249259Sdim NoItinerary>; 3832249259Sdim 3833249259Sdim def _asr : A64I_logicalshift<sf, 0b01, 0b10, 0b1, 3834249259Sdim (outs GPR:$Rd), 3835249259Sdim (ins GPR:$Rm, 3836249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6), 3837249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3838249259Sdim [(set ty:$Rd, (not (sra ty:$Rm, 3839249259Sdim !cast<Operand>("asr_operand_" # ty):$Imm6)))], 3840249259Sdim NoItinerary>; 3841249259Sdim 3842249259Sdim def _ror : A64I_logicalshift<sf, 0b01, 0b11, 0b1, 3843249259Sdim (outs GPR:$Rd), 3844249259Sdim (ins GPR:$Rm, 3845249259Sdim !cast<Operand>("ror_operand_" # ty):$Imm6), 3846249259Sdim "mvn\t$Rd, $Rm, $Imm6", 3847249259Sdim [(set ty:$Rd, (not (rotr ty:$Rm, 3848249259Sdim !cast<Operand>("lsl_operand_" # ty):$Imm6)))], 3849249259Sdim NoItinerary>; 3850249259Sdim } 3851249259Sdim 3852249259Sdim def _noshift : InstAlias<"mvn $Rn, $Rm", 3853249259Sdim (!cast<Instruction>(prefix # "_lsl") GPR:$Rn, GPR:$Rm, 0)>; 3854249259Sdim 3855249259Sdim def : Pat<(not ty:$Rm), 3856249259Sdim (!cast<Instruction>(prefix # "_lsl") $Rm, 0)>; 3857249259Sdim} 3858249259Sdim 3859249259Sdimdefm MVNxx : mvn_shifts<"MVNxx", 0b1, i64, GPR64>; 3860249259Sdimdefm MVNww : mvn_shifts<"MVNww", 0b0, i32, GPR32>; 3861249259Sdim 3862249259Sdimdef MOVxx :InstAlias<"mov $Rd, $Rm", (ORRxxx_lsl GPR64:$Rd, XZR, GPR64:$Rm, 0)>; 3863249259Sdimdef MOVww :InstAlias<"mov $Rd, $Rm", (ORRwww_lsl GPR32:$Rd, WZR, GPR32:$Rm, 0)>; 3864249259Sdim 3865249259Sdim//===----------------------------------------------------------------------===// 3866249259Sdim// Move wide (immediate) instructions 3867249259Sdim//===----------------------------------------------------------------------===// 3868249259Sdim// Contains: MOVN, MOVZ, MOVK + MOV aliases 3869249259Sdim 3870249259Sdim// A wide variety of different relocations are needed for variants of these 3871249259Sdim// instructions, so it turns out that we need a different operand for all of 3872249259Sdim// them. 3873249259Sdimmulticlass movw_operands<string prefix, string instname, int width> { 3874249259Sdim def _imm_asmoperand : AsmOperandClass { 3875249259Sdim let Name = instname # width # "Shifted" # shift; 3876249259Sdim let PredicateMethod = "is" # instname # width # "Imm"; 3877249259Sdim let RenderMethod = "addMoveWideImmOperands"; 3878249259Sdim let ParserMethod = "ParseImmWithLSLOperand"; 3879249259Sdim let DiagnosticType = "MOVWUImm16"; 3880249259Sdim } 3881249259Sdim 3882251662Sdim def _imm : Operand<i64> { 3883249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand"); 3884249259Sdim let PrintMethod = "printMoveWideImmOperand"; 3885249259Sdim let EncoderMethod = "getMoveWideImmOpValue"; 3886249259Sdim let DecoderMethod = "DecodeMoveWideImmOperand<" # width # ">"; 3887249259Sdim 3888249259Sdim let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3889249259Sdim } 3890249259Sdim} 3891249259Sdim 3892249259Sdimdefm movn32 : movw_operands<"movn32", "MOVN", 32>; 3893249259Sdimdefm movn64 : movw_operands<"movn64", "MOVN", 64>; 3894249259Sdimdefm movz32 : movw_operands<"movz32", "MOVZ", 32>; 3895249259Sdimdefm movz64 : movw_operands<"movz64", "MOVZ", 64>; 3896249259Sdimdefm movk32 : movw_operands<"movk32", "MOVK", 32>; 3897249259Sdimdefm movk64 : movw_operands<"movk64", "MOVK", 64>; 3898249259Sdim 3899249259Sdimmulticlass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, 3900249259Sdim dag ins64bit> { 3901249259Sdim 3902249259Sdim def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit, 3903249259Sdim !strconcat(asmop, "\t$Rd, $FullImm"), 3904249259Sdim [], NoItinerary> { 3905249259Sdim bits<18> FullImm; 3906249259Sdim let UImm16 = FullImm{15-0}; 3907249259Sdim let Shift = FullImm{17-16}; 3908249259Sdim } 3909249259Sdim 3910249259Sdim def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit, 3911249259Sdim !strconcat(asmop, "\t$Rd, $FullImm"), 3912249259Sdim [], NoItinerary> { 3913249259Sdim bits<18> FullImm; 3914249259Sdim let UImm16 = FullImm{15-0}; 3915249259Sdim let Shift = FullImm{17-16}; 3916249259Sdim } 3917249259Sdim} 3918249259Sdim 3919249259Sdimlet isMoveImm = 1, isReMaterializable = 1, 3920249259Sdim isAsCheapAsAMove = 1, hasSideEffects = 0 in { 3921249259Sdim defm MOVN : A64I_movwSizes<0b00, "movn", 3922249259Sdim (ins movn32_imm:$FullImm), 3923249259Sdim (ins movn64_imm:$FullImm)>; 3924249259Sdim 3925249259Sdim // Some relocations are able to convert between a MOVZ and a MOVN. If these 3926249259Sdim // are applied the instruction must be emitted with the corresponding bits as 3927249259Sdim // 0, which means a MOVZ needs to override that bit from the default. 3928249259Sdim let PostEncoderMethod = "fixMOVZ" in 3929249259Sdim defm MOVZ : A64I_movwSizes<0b10, "movz", 3930249259Sdim (ins movz32_imm:$FullImm), 3931249259Sdim (ins movz64_imm:$FullImm)>; 3932249259Sdim} 3933249259Sdim 3934249259Sdimlet Constraints = "$src = $Rd" in 3935249259Sdimdefm MOVK : A64I_movwSizes<0b11, "movk", 3936249259Sdim (ins GPR32:$src, movk32_imm:$FullImm), 3937249259Sdim (ins GPR64:$src, movk64_imm:$FullImm)>; 3938249259Sdim 3939249259Sdim 3940249259Sdim// And now the "MOV" aliases. These also need their own operands because what 3941249259Sdim// they accept is completely different to what the base instructions accept. 3942249259Sdimmulticlass movalias_operand<string prefix, string basename, 3943249259Sdim string immpredicate, int width> { 3944249259Sdim def _asmoperand : AsmOperandClass { 3945249259Sdim let Name = basename # width # "MovAlias"; 3946249259Sdim let PredicateMethod 3947249259Sdim = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">"; 3948249259Sdim let RenderMethod 3949249259Sdim = "addMoveWideMovAliasOperands<" # width # ", " 3950249259Sdim # "A64Imms::" # immpredicate # ">"; 3951249259Sdim } 3952249259Sdim 3953251662Sdim def _movimm : Operand<i64> { 3954249259Sdim let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand"); 3955249259Sdim 3956249259Sdim let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift); 3957249259Sdim } 3958249259Sdim} 3959249259Sdim 3960249259Sdimdefm movz32 : movalias_operand<"movz32", "MOVZ", "isMOVZImm", 32>; 3961249259Sdimdefm movz64 : movalias_operand<"movz64", "MOVZ", "isMOVZImm", 64>; 3962249259Sdimdefm movn32 : movalias_operand<"movn32", "MOVN", "isOnlyMOVNImm", 32>; 3963249259Sdimdefm movn64 : movalias_operand<"movn64", "MOVN", "isOnlyMOVNImm", 64>; 3964249259Sdim 3965249259Sdim// FIXME: these are officially canonical aliases, but TableGen is too limited to 3966249259Sdim// print them at the moment. I believe in this case an "AliasPredicate" method 3967249259Sdim// will need to be implemented. to allow it, as well as the more generally 3968249259Sdim// useful handling of non-register, non-constant operands. 3969249259Sdimclass movalias<Instruction INST, RegisterClass GPR, Operand operand> 3970249259Sdim : InstAlias<"mov $Rd, $FullImm", (INST GPR:$Rd, operand:$FullImm)>; 3971249259Sdim 3972249259Sdimdef : movalias<MOVZwii, GPR32, movz32_movimm>; 3973249259Sdimdef : movalias<MOVZxii, GPR64, movz64_movimm>; 3974249259Sdimdef : movalias<MOVNwii, GPR32, movn32_movimm>; 3975249259Sdimdef : movalias<MOVNxii, GPR64, movn64_movimm>; 3976249259Sdim 3977251662Sdimdef movw_addressref : ComplexPattern<i64, 2, "SelectMOVWAddressRef">; 3978251662Sdim 3979251662Sdimdef : Pat<(A64WrapperLarge movw_addressref:$G3, movw_addressref:$G2, 3980251662Sdim movw_addressref:$G1, movw_addressref:$G0), 3981251662Sdim (MOVKxii (MOVKxii (MOVKxii (MOVZxii movw_addressref:$G3), 3982251662Sdim movw_addressref:$G2), 3983251662Sdim movw_addressref:$G1), 3984251662Sdim movw_addressref:$G0)>; 3985251662Sdim 3986249259Sdim//===----------------------------------------------------------------------===// 3987249259Sdim// PC-relative addressing instructions 3988249259Sdim//===----------------------------------------------------------------------===// 3989249259Sdim// Contains: ADR, ADRP 3990249259Sdim 3991249259Sdimdef adr_label : Operand<i64> { 3992249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_adr_prel>"; 3993249259Sdim 3994249259Sdim // This label is a 21-bit offset from PC, unscaled 3995249259Sdim let PrintMethod = "printLabelOperand<21, 1>"; 3996249259Sdim let ParserMatchClass = label_asmoperand<21, 1>; 3997249259Sdim let OperandType = "OPERAND_PCREL"; 3998249259Sdim} 3999249259Sdim 4000249259Sdimdef adrp_label_asmoperand : AsmOperandClass { 4001249259Sdim let Name = "AdrpLabel"; 4002249259Sdim let RenderMethod = "addLabelOperands<21, 4096>"; 4003249259Sdim let DiagnosticType = "Label"; 4004249259Sdim} 4005249259Sdim 4006249259Sdimdef adrp_label : Operand<i64> { 4007249259Sdim let EncoderMethod = "getAdrpLabelOpValue"; 4008249259Sdim 4009249259Sdim // This label is a 21-bit offset from PC, scaled by the page-size: 4096. 4010249259Sdim let PrintMethod = "printLabelOperand<21, 4096>"; 4011249259Sdim let ParserMatchClass = adrp_label_asmoperand; 4012249259Sdim let OperandType = "OPERAND_PCREL"; 4013249259Sdim} 4014249259Sdim 4015249259Sdimlet hasSideEffects = 0 in { 4016249259Sdim def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label), 4017249259Sdim "adr\t$Rd, $Label", [], NoItinerary>; 4018249259Sdim 4019249259Sdim def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label), 4020249259Sdim "adrp\t$Rd, $Label", [], NoItinerary>; 4021249259Sdim} 4022249259Sdim 4023249259Sdim//===----------------------------------------------------------------------===// 4024249259Sdim// System instructions 4025249259Sdim//===----------------------------------------------------------------------===// 4026249259Sdim// Contains: HINT, CLREX, DSB, DMB, ISB, MSR, SYS, SYSL, MRS 4027249259Sdim// + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL 4028249259Sdim 4029249259Sdim// Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values. 4030249259Sdimdef uimm3_asmoperand : AsmOperandClass { 4031249259Sdim let Name = "UImm3"; 4032249259Sdim let PredicateMethod = "isUImm<3>"; 4033249259Sdim let RenderMethod = "addImmOperands"; 4034249259Sdim let DiagnosticType = "UImm3"; 4035249259Sdim} 4036249259Sdim 4037249259Sdimdef uimm3 : Operand<i32> { 4038249259Sdim let ParserMatchClass = uimm3_asmoperand; 4039249259Sdim} 4040249259Sdim 4041249259Sdim// The HINT alias can accept a simple unsigned 7-bit immediate. 4042249259Sdimdef uimm7_asmoperand : AsmOperandClass { 4043249259Sdim let Name = "UImm7"; 4044249259Sdim let PredicateMethod = "isUImm<7>"; 4045249259Sdim let RenderMethod = "addImmOperands"; 4046249259Sdim let DiagnosticType = "UImm7"; 4047249259Sdim} 4048249259Sdim 4049249259Sdimdef uimm7 : Operand<i32> { 4050249259Sdim let ParserMatchClass = uimm7_asmoperand; 4051249259Sdim} 4052249259Sdim 4053249259Sdim// Multiclass namedimm is defined with the prefetch operands. Most of these fit 4054249259Sdim// into the NamedImmMapper scheme well: they either accept a named operand or 4055249259Sdim// any immediate under a particular value (which may be 0, implying no immediate 4056249259Sdim// is allowed). 4057249259Sdimdefm dbarrier : namedimm<"dbarrier", "A64DB::DBarrierMapper">; 4058249259Sdimdefm isb : namedimm<"isb", "A64ISB::ISBMapper">; 4059249259Sdimdefm ic : namedimm<"ic", "A64IC::ICMapper">; 4060249259Sdimdefm dc : namedimm<"dc", "A64DC::DCMapper">; 4061249259Sdimdefm at : namedimm<"at", "A64AT::ATMapper">; 4062249259Sdimdefm tlbi : namedimm<"tlbi", "A64TLBI::TLBIMapper">; 4063249259Sdim 4064249259Sdim// However, MRS and MSR are more complicated for a few reasons: 4065249259Sdim// * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an 4066249259Sdim// implementation-defined effect 4067249259Sdim// * Most registers are shared, but some are read-only or write-only. 4068249259Sdim// * There is a variant of MSR which accepts the same register name (SPSel), 4069249259Sdim// but which would have a different encoding. 4070249259Sdim 4071249259Sdim// In principle these could be resolved in with more complicated subclasses of 4072249259Sdim// NamedImmMapper, however that imposes an overhead on other "named 4073249259Sdim// immediates". Both in concrete terms with virtual tables and in unnecessary 4074249259Sdim// abstraction. 4075249259Sdim 4076249259Sdim// The solution adopted here is to take the MRS/MSR Mappers out of the usual 4077249259Sdim// hierarchy (they're not derived from NamedImmMapper) and to add logic for 4078249259Sdim// their special situation. 4079249259Sdimdef mrs_asmoperand : AsmOperandClass { 4080249259Sdim let Name = "MRS"; 4081249259Sdim let ParserMethod = "ParseSysRegOperand"; 4082249259Sdim let DiagnosticType = "MRS"; 4083249259Sdim} 4084249259Sdim 4085249259Sdimdef mrs_op : Operand<i32> { 4086249259Sdim let ParserMatchClass = mrs_asmoperand; 4087249259Sdim let PrintMethod = "printMRSOperand"; 4088249259Sdim let DecoderMethod = "DecodeMRSOperand"; 4089249259Sdim} 4090249259Sdim 4091249259Sdimdef msr_asmoperand : AsmOperandClass { 4092249259Sdim let Name = "MSRWithReg"; 4093249259Sdim 4094249259Sdim // Note that SPSel is valid for both this and the pstate operands, but with 4095249259Sdim // different immediate encodings. This is why these operands provide a string 4096249259Sdim // AArch64Operand rather than an immediate. The overlap is small enough that 4097249259Sdim // it could be resolved with hackery now, but who can say in future? 4098249259Sdim let ParserMethod = "ParseSysRegOperand"; 4099249259Sdim let DiagnosticType = "MSR"; 4100249259Sdim} 4101249259Sdim 4102249259Sdimdef msr_op : Operand<i32> { 4103249259Sdim let ParserMatchClass = msr_asmoperand; 4104249259Sdim let PrintMethod = "printMSROperand"; 4105249259Sdim let DecoderMethod = "DecodeMSROperand"; 4106249259Sdim} 4107249259Sdim 4108249259Sdimdef pstate_asmoperand : AsmOperandClass { 4109249259Sdim let Name = "MSRPState"; 4110249259Sdim // See comment above about parser. 4111249259Sdim let ParserMethod = "ParseSysRegOperand"; 4112249259Sdim let DiagnosticType = "MSR"; 4113249259Sdim} 4114249259Sdim 4115249259Sdimdef pstate_op : Operand<i32> { 4116249259Sdim let ParserMatchClass = pstate_asmoperand; 4117249259Sdim let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>"; 4118249259Sdim let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>"; 4119249259Sdim} 4120249259Sdim 4121249259Sdim// When <CRn> is specified, an assembler should accept something like "C4", not 4122249259Sdim// the usual "#4" immediate. 4123249259Sdimdef CRx_asmoperand : AsmOperandClass { 4124249259Sdim let Name = "CRx"; 4125249259Sdim let PredicateMethod = "isUImm<4>"; 4126249259Sdim let RenderMethod = "addImmOperands"; 4127249259Sdim let ParserMethod = "ParseCRxOperand"; 4128249259Sdim // Diagnostics are handled in all cases by ParseCRxOperand. 4129249259Sdim} 4130249259Sdim 4131249259Sdimdef CRx : Operand<i32> { 4132249259Sdim let ParserMatchClass = CRx_asmoperand; 4133249259Sdim let PrintMethod = "printCRxOperand"; 4134249259Sdim} 4135249259Sdim 4136249259Sdim 4137249259Sdim// Finally, we can start defining the instructions. 4138249259Sdim 4139249259Sdim// HINT is straightforward, with a few aliases. 4140249259Sdimdef HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7", 4141249259Sdim [], NoItinerary> { 4142249259Sdim bits<7> UImm7; 4143249259Sdim let CRm = UImm7{6-3}; 4144249259Sdim let Op2 = UImm7{2-0}; 4145249259Sdim 4146249259Sdim let Op0 = 0b00; 4147249259Sdim let Op1 = 0b011; 4148249259Sdim let CRn = 0b0010; 4149249259Sdim let Rt = 0b11111; 4150249259Sdim} 4151249259Sdim 4152249259Sdimdef : InstAlias<"nop", (HINTi 0)>; 4153249259Sdimdef : InstAlias<"yield", (HINTi 1)>; 4154249259Sdimdef : InstAlias<"wfe", (HINTi 2)>; 4155249259Sdimdef : InstAlias<"wfi", (HINTi 3)>; 4156249259Sdimdef : InstAlias<"sev", (HINTi 4)>; 4157249259Sdimdef : InstAlias<"sevl", (HINTi 5)>; 4158249259Sdim 4159249259Sdim// Quite a few instructions then follow a similar pattern of fixing common 4160249259Sdim// fields in the bitpattern, we'll define a helper-class for them. 4161249259Sdimclass simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2, 4162249259Sdim Operand operand, string asmop> 4163249259Sdim : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"), 4164249259Sdim [], NoItinerary> { 4165249259Sdim let Op0 = op0; 4166249259Sdim let Op1 = op1; 4167249259Sdim let CRn = crn; 4168249259Sdim let Op2 = op2; 4169249259Sdim let Rt = 0b11111; 4170249259Sdim} 4171249259Sdim 4172249259Sdim 4173249259Sdimdef CLREXi : simple_sys<0b00, 0b011, 0b0011, 0b010, uimm4, "clrex">; 4174249259Sdimdef DSBi : simple_sys<0b00, 0b011, 0b0011, 0b100, dbarrier_op, "dsb">; 4175249259Sdimdef DMBi : simple_sys<0b00, 0b011, 0b0011, 0b101, dbarrier_op, "dmb">; 4176249259Sdimdef ISBi : simple_sys<0b00, 0b011, 0b0011, 0b110, isb_op, "isb">; 4177249259Sdim 4178249259Sdimdef : InstAlias<"clrex", (CLREXi 0b1111)>; 4179249259Sdimdef : InstAlias<"isb", (ISBi 0b1111)>; 4180249259Sdim 4181249259Sdim// (DMBi 0xb) is a "DMB ISH" instruciton, appropriate for Linux SMP 4182249259Sdim// configurations at least. 4183249259Sdimdef : Pat<(atomic_fence imm, imm), (DMBi 0xb)>; 4184249259Sdim 4185249259Sdim// Any SYS bitpattern can be represented with a complex and opaque "SYS" 4186249259Sdim// instruction. 4187249259Sdimdef SYSiccix : A64I_system<0b0, (outs), 4188249259Sdim (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, 4189249259Sdim uimm3:$Op2, GPR64:$Rt), 4190249259Sdim "sys\t$Op1, $CRn, $CRm, $Op2, $Rt", 4191249259Sdim [], NoItinerary> { 4192249259Sdim let Op0 = 0b01; 4193249259Sdim} 4194249259Sdim 4195249259Sdim// You can skip the Xt argument whether it makes sense or not for the generic 4196249259Sdim// SYS instruction. 4197249259Sdimdef : InstAlias<"sys $Op1, $CRn, $CRm, $Op2", 4198249259Sdim (SYSiccix uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2, XZR)>; 4199249259Sdim 4200249259Sdim 4201249259Sdim// But many have aliases, which obviously don't fit into 4202249259Sdimclass SYSalias<dag ins, string asmstring> 4203249259Sdim : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> { 4204249259Sdim let isAsmParserOnly = 1; 4205249259Sdim 4206249259Sdim bits<14> SysOp; 4207249259Sdim let Op0 = 0b01; 4208249259Sdim let Op1 = SysOp{13-11}; 4209249259Sdim let CRn = SysOp{10-7}; 4210249259Sdim let CRm = SysOp{6-3}; 4211249259Sdim let Op2 = SysOp{2-0}; 4212249259Sdim} 4213249259Sdim 4214249259Sdimdef ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">; 4215249259Sdim 4216249259Sdimdef ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> { 4217249259Sdim let Rt = 0b11111; 4218249259Sdim} 4219249259Sdim 4220249259Sdimdef DCix : SYSalias<(ins dc_op:$SysOp, GPR64:$Rt), "dc\t$SysOp, $Rt">; 4221249259Sdimdef ATix : SYSalias<(ins at_op:$SysOp, GPR64:$Rt), "at\t$SysOp, $Rt">; 4222249259Sdim 4223249259Sdimdef TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">; 4224249259Sdim 4225249259Sdimdef TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> { 4226249259Sdim let Rt = 0b11111; 4227249259Sdim} 4228249259Sdim 4229249259Sdim 4230249259Sdimdef SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt), 4231249259Sdim (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2), 4232249259Sdim "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2", 4233249259Sdim [], NoItinerary> { 4234249259Sdim let Op0 = 0b01; 4235249259Sdim} 4236249259Sdim 4237249259Sdim// The instructions themselves are rather simple for MSR and MRS. 4238249259Sdimdef MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt), 4239249259Sdim "msr\t$SysReg, $Rt", [], NoItinerary> { 4240249259Sdim bits<16> SysReg; 4241249259Sdim let Op0 = SysReg{15-14}; 4242249259Sdim let Op1 = SysReg{13-11}; 4243249259Sdim let CRn = SysReg{10-7}; 4244249259Sdim let CRm = SysReg{6-3}; 4245249259Sdim let Op2 = SysReg{2-0}; 4246249259Sdim} 4247249259Sdim 4248249259Sdimdef MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg), 4249249259Sdim "mrs\t$Rt, $SysReg", [], NoItinerary> { 4250249259Sdim bits<16> SysReg; 4251249259Sdim let Op0 = SysReg{15-14}; 4252249259Sdim let Op1 = SysReg{13-11}; 4253249259Sdim let CRn = SysReg{10-7}; 4254249259Sdim let CRm = SysReg{6-3}; 4255249259Sdim let Op2 = SysReg{2-0}; 4256249259Sdim} 4257249259Sdim 4258249259Sdimdef MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm), 4259249259Sdim "msr\t$PState, $CRm", [], NoItinerary> { 4260249259Sdim bits<6> PState; 4261249259Sdim 4262249259Sdim let Op0 = 0b00; 4263249259Sdim let Op1 = PState{5-3}; 4264249259Sdim let CRn = 0b0100; 4265249259Sdim let Op2 = PState{2-0}; 4266249259Sdim let Rt = 0b11111; 4267249259Sdim} 4268249259Sdim 4269249259Sdim//===----------------------------------------------------------------------===// 4270249259Sdim// Test & branch (immediate) instructions 4271249259Sdim//===----------------------------------------------------------------------===// 4272249259Sdim// Contains: TBZ, TBNZ 4273249259Sdim 4274249259Sdim// The bit to test is a simple unsigned 6-bit immediate in the X-register 4275249259Sdim// versions. 4276249259Sdimdef uimm6 : Operand<i64> { 4277249259Sdim let ParserMatchClass = uimm6_asmoperand; 4278249259Sdim} 4279249259Sdim 4280249259Sdimdef label_wid14_scal4_asmoperand : label_asmoperand<14, 4>; 4281249259Sdim 4282249259Sdimdef tbimm_target : Operand<OtherVT> { 4283249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>"; 4284249259Sdim 4285249259Sdim // This label is a 14-bit offset from PC, scaled by the instruction-width: 4. 4286249259Sdim let PrintMethod = "printLabelOperand<14, 4>"; 4287249259Sdim let ParserMatchClass = label_wid14_scal4_asmoperand; 4288249259Sdim 4289249259Sdim let OperandType = "OPERAND_PCREL"; 4290249259Sdim} 4291249259Sdim 4292249259Sdimdef A64eq : ImmLeaf<i32, [{ return Imm == A64CC::EQ; }]>; 4293249259Sdimdef A64ne : ImmLeaf<i32, [{ return Imm == A64CC::NE; }]>; 4294249259Sdim 4295249259Sdim// These instructions correspond to patterns involving "and" with a power of 4296249259Sdim// two, which we need to be able to select. 4297249259Sdimdef tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">; 4298249259Sdimdef tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">; 4299249259Sdim 4300249259Sdimlet isBranch = 1, isTerminator = 1 in { 4301249259Sdim def TBZxii : A64I_TBimm<0b0, (outs), 4302249259Sdim (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4303249259Sdim "tbz\t$Rt, $Imm, $Label", 4304249259Sdim [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4305249259Sdim A64eq, bb:$Label)], 4306249259Sdim NoItinerary>; 4307249259Sdim 4308249259Sdim def TBNZxii : A64I_TBimm<0b1, (outs), 4309249259Sdim (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label), 4310249259Sdim "tbnz\t$Rt, $Imm, $Label", 4311249259Sdim [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0), 4312249259Sdim A64ne, bb:$Label)], 4313249259Sdim NoItinerary>; 4314249259Sdim 4315249259Sdim 4316249259Sdim // Note, these instructions overlap with the above 64-bit patterns. This is 4317249259Sdim // intentional, "tbz x3, #1, somewhere" and "tbz w3, #1, somewhere" would both 4318249259Sdim // do the same thing and are both permitted assembly. They also both have 4319249259Sdim // sensible DAG patterns. 4320249259Sdim def TBZwii : A64I_TBimm<0b0, (outs), 4321249259Sdim (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4322249259Sdim "tbz\t$Rt, $Imm, $Label", 4323249259Sdim [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4324249259Sdim A64eq, bb:$Label)], 4325249259Sdim NoItinerary> { 4326249259Sdim let Imm{5} = 0b0; 4327249259Sdim } 4328249259Sdim 4329249259Sdim def TBNZwii : A64I_TBimm<0b1, (outs), 4330249259Sdim (ins GPR32:$Rt, uimm5:$Imm, tbimm_target:$Label), 4331249259Sdim "tbnz\t$Rt, $Imm, $Label", 4332249259Sdim [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0), 4333249259Sdim A64ne, bb:$Label)], 4334249259Sdim NoItinerary> { 4335249259Sdim let Imm{5} = 0b0; 4336249259Sdim } 4337249259Sdim} 4338249259Sdim 4339249259Sdim//===----------------------------------------------------------------------===// 4340249259Sdim// Unconditional branch (immediate) instructions 4341249259Sdim//===----------------------------------------------------------------------===// 4342249259Sdim// Contains: B, BL 4343249259Sdim 4344249259Sdimdef label_wid26_scal4_asmoperand : label_asmoperand<26, 4>; 4345249259Sdim 4346249259Sdimdef bimm_target : Operand<OtherVT> { 4347249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>"; 4348249259Sdim 4349249259Sdim // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4350249259Sdim let PrintMethod = "printLabelOperand<26, 4>"; 4351249259Sdim let ParserMatchClass = label_wid26_scal4_asmoperand; 4352249259Sdim 4353249259Sdim let OperandType = "OPERAND_PCREL"; 4354249259Sdim} 4355249259Sdim 4356249259Sdimdef blimm_target : Operand<i64> { 4357249259Sdim let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>"; 4358249259Sdim 4359249259Sdim // This label is a 26-bit offset from PC, scaled by the instruction-width: 4. 4360249259Sdim let PrintMethod = "printLabelOperand<26, 4>"; 4361249259Sdim let ParserMatchClass = label_wid26_scal4_asmoperand; 4362249259Sdim 4363249259Sdim let OperandType = "OPERAND_PCREL"; 4364249259Sdim} 4365249259Sdim 4366249259Sdimclass A64I_BimmImpl<bit op, string asmop, list<dag> patterns, Operand lbl_type> 4367249259Sdim : A64I_Bimm<op, (outs), (ins lbl_type:$Label), 4368249259Sdim !strconcat(asmop, "\t$Label"), patterns, 4369249259Sdim NoItinerary>; 4370249259Sdim 4371249259Sdimlet isBranch = 1 in { 4372249259Sdim def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> { 4373249259Sdim let isTerminator = 1; 4374249259Sdim let isBarrier = 1; 4375249259Sdim } 4376249259Sdim 4377249259Sdim def BLimm : A64I_BimmImpl<0b1, "bl", 4378249259Sdim [(AArch64Call tglobaladdr:$Label)], blimm_target> { 4379249259Sdim let isCall = 1; 4380249259Sdim let Defs = [X30]; 4381249259Sdim } 4382249259Sdim} 4383249259Sdim 4384249259Sdimdef : Pat<(AArch64Call texternalsym:$Label), (BLimm texternalsym:$Label)>; 4385249259Sdim 4386249259Sdim//===----------------------------------------------------------------------===// 4387249259Sdim// Unconditional branch (register) instructions 4388249259Sdim//===----------------------------------------------------------------------===// 4389249259Sdim// Contains: BR, BLR, RET, ERET, DRP. 4390249259Sdim 4391249259Sdim// Most of the notional opcode fields in the A64I_Breg format are fixed in A64 4392249259Sdim// at the moment. 4393249259Sdimclass A64I_BregImpl<bits<4> opc, 4394249259Sdim dag outs, dag ins, string asmstr, list<dag> patterns, 4395249259Sdim InstrItinClass itin = NoItinerary> 4396249259Sdim : A64I_Breg<opc, 0b11111, 0b000000, 0b00000, 4397249259Sdim outs, ins, asmstr, patterns, itin> { 4398249259Sdim let isBranch = 1; 4399249259Sdim let isIndirectBranch = 1; 4400249259Sdim} 4401249259Sdim 4402249259Sdim// Note that these are not marked isCall or isReturn because as far as LLVM is 4403249259Sdim// concerned they're not. "ret" is just another jump unless it has been selected 4404249259Sdim// by LLVM as the function's return. 4405249259Sdim 4406249259Sdimlet isBranch = 1 in { 4407249259Sdim def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn), 4408249259Sdim "br\t$Rn", [(brind i64:$Rn)]> { 4409249259Sdim let isBarrier = 1; 4410249259Sdim let isTerminator = 1; 4411249259Sdim } 4412249259Sdim 4413249259Sdim def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn), 4414249259Sdim "blr\t$Rn", [(AArch64Call i64:$Rn)]> { 4415249259Sdim let isBarrier = 0; 4416249259Sdim let isCall = 1; 4417249259Sdim let Defs = [X30]; 4418249259Sdim } 4419249259Sdim 4420249259Sdim def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn), 4421249259Sdim "ret\t$Rn", []> { 4422249259Sdim let isBarrier = 1; 4423249259Sdim let isTerminator = 1; 4424249259Sdim let isReturn = 1; 4425249259Sdim } 4426249259Sdim 4427249259Sdim // Create a separate pseudo-instruction for codegen to use so that we don't 4428249259Sdim // flag x30 as used in every function. It'll be restored before the RET by the 4429249259Sdim // epilogue if it's legitimately used. 4430249259Sdim def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> { 4431249259Sdim let isTerminator = 1; 4432249259Sdim let isBarrier = 1; 4433249259Sdim let isReturn = 1; 4434249259Sdim } 4435249259Sdim 4436249259Sdim def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> { 4437249259Sdim let Rn = 0b11111; 4438249259Sdim let isBarrier = 1; 4439249259Sdim let isTerminator = 1; 4440249259Sdim let isReturn = 1; 4441249259Sdim } 4442249259Sdim 4443249259Sdim def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> { 4444249259Sdim let Rn = 0b11111; 4445249259Sdim let isBarrier = 1; 4446249259Sdim } 4447249259Sdim} 4448249259Sdim 4449249259Sdimdef RETAlias : InstAlias<"ret", (RETx X30)>; 4450249259Sdim 4451249259Sdim 4452249259Sdim//===----------------------------------------------------------------------===// 4453249259Sdim// Address generation patterns 4454249259Sdim//===----------------------------------------------------------------------===// 4455249259Sdim 4456249259Sdim// Primary method of address generation for the small/absolute memory model is 4457249259Sdim// an ADRP/ADR pair: 4458249259Sdim// ADRP x0, some_variable 4459249259Sdim// ADD x0, x0, #:lo12:some_variable 4460249259Sdim// 4461249259Sdim// The load/store elision of the ADD is accomplished when selecting 4462249259Sdim// addressing-modes. This just mops up the cases where that doesn't work and we 4463249259Sdim// really need an address in some register. 4464249259Sdim 4465249259Sdim// This wrapper applies a LO12 modifier to the address. Otherwise we could just 4466249259Sdim// use the same address. 4467249259Sdim 4468249259Sdimclass ADRP_ADD<SDNode Wrapper, SDNode addrop> 4469249259Sdim : Pat<(Wrapper addrop:$Hi, addrop:$Lo12, (i32 imm)), 4470249259Sdim (ADDxxi_lsl0_s (ADRPxi addrop:$Hi), addrop:$Lo12)>; 4471249259Sdim 4472249259Sdimdef : ADRP_ADD<A64WrapperSmall, tblockaddress>; 4473249259Sdimdef : ADRP_ADD<A64WrapperSmall, texternalsym>; 4474249259Sdimdef : ADRP_ADD<A64WrapperSmall, tglobaladdr>; 4475249259Sdimdef : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>; 4476249259Sdimdef : ADRP_ADD<A64WrapperSmall, tjumptable>; 4477249259Sdim 4478249259Sdim//===----------------------------------------------------------------------===// 4479249259Sdim// GOT access patterns 4480249259Sdim//===----------------------------------------------------------------------===// 4481249259Sdim 4482249259Sdimclass GOTLoadSmall<SDNode addrfrag> 4483249259Sdim : Pat<(A64GOTLoad (A64WrapperSmall addrfrag:$Hi, addrfrag:$Lo12, 8)), 4484249259Sdim (LS64_LDR (ADRPxi addrfrag:$Hi), addrfrag:$Lo12)>; 4485249259Sdim 4486249259Sdimdef : GOTLoadSmall<texternalsym>; 4487249259Sdimdef : GOTLoadSmall<tglobaladdr>; 4488249259Sdimdef : GOTLoadSmall<tglobaltlsaddr>; 4489249259Sdim 4490249259Sdim//===----------------------------------------------------------------------===// 4491249259Sdim// Tail call handling 4492249259Sdim//===----------------------------------------------------------------------===// 4493249259Sdim 4494249259Sdimlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in { 4495249259Sdim def TC_RETURNdi 4496249259Sdim : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff), 4497249259Sdim [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>; 4498249259Sdim 4499249259Sdim def TC_RETURNxi 4500249259Sdim : PseudoInst<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), 4501249259Sdim [(AArch64tcret i64:$dst, (i32 timm:$FPDiff))]>; 4502249259Sdim} 4503249259Sdim 4504249259Sdimlet isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 4505249259Sdim Uses = [XSP] in { 4506249259Sdim def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [], 4507249259Sdim (Bimm bimm_target:$Label)>; 4508249259Sdim 4509249259Sdim def TAIL_BRx : A64PseudoExpand<(outs), (ins tcGPR64:$Rd), [], 4510249259Sdim (BRx GPR64:$Rd)>; 4511249259Sdim} 4512249259Sdim 4513249259Sdim 4514249259Sdimdef : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)), 4515249259Sdim (TC_RETURNdi texternalsym:$dst, imm:$FPDiff)>; 4516249259Sdim 4517249259Sdim//===----------------------------------------------------------------------===// 4518249259Sdim// Thread local storage 4519249259Sdim//===----------------------------------------------------------------------===// 4520249259Sdim 4521249259Sdim// This is a pseudo-instruction representing the ".tlsdesccall" directive in 4522249259Sdim// assembly. Its effect is to insert an R_AARCH64_TLSDESC_CALL relocation at the 4523249259Sdim// current location. It should always be immediately followed by a BLR 4524249259Sdim// instruction, and is intended solely for relaxation by the linker. 4525249259Sdim 4526249259Sdimdef : Pat<(A64threadpointer), (MRSxi 0xde82)>; 4527249259Sdim 4528249259Sdimdef TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> { 4529249259Sdim let hasSideEffects = 1; 4530249259Sdim} 4531249259Sdim 4532249259Sdimdef TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var), 4533249259Sdim [(A64tlsdesc_blr i64:$Rn, tglobaltlsaddr:$Var)]> { 4534249259Sdim let isCall = 1; 4535249259Sdim let Defs = [X30]; 4536249259Sdim} 4537249259Sdim 4538249259Sdimdef : Pat<(A64tlsdesc_blr i64:$Rn, texternalsym:$Var), 4539249259Sdim (TLSDESC_BLRx $Rn, texternalsym:$Var)>; 4540249259Sdim 4541249259Sdim//===----------------------------------------------------------------------===// 4542249259Sdim// Bitfield patterns 4543249259Sdim//===----------------------------------------------------------------------===// 4544249259Sdim 4545249259Sdimdef bfi32_lsb_to_immr : SDNodeXForm<imm, [{ 4546249259Sdim return CurDAG->getTargetConstant((32 - N->getZExtValue()) % 32, MVT::i64); 4547249259Sdim}]>; 4548249259Sdim 4549249259Sdimdef bfi64_lsb_to_immr : SDNodeXForm<imm, [{ 4550249259Sdim return CurDAG->getTargetConstant((64 - N->getZExtValue()) % 64, MVT::i64); 4551249259Sdim}]>; 4552249259Sdim 4553249259Sdimdef bfi_width_to_imms : SDNodeXForm<imm, [{ 4554249259Sdim return CurDAG->getTargetConstant(N->getZExtValue() - 1, MVT::i64); 4555249259Sdim}]>; 4556249259Sdim 4557249259Sdim 4558249259Sdim// The simpler patterns deal with cases where no AND mask is actually needed 4559249259Sdim// (either all bits are used or the low 32 bits are used). 4560249259Sdimlet AddedComplexity = 10 in { 4561249259Sdim 4562249259Sdimdef : Pat<(A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4563249259Sdim (BFIxxii $src, $Rn, 4564249259Sdim (bfi64_lsb_to_immr (i64 imm:$ImmR)), 4565249259Sdim (bfi_width_to_imms (i64 imm:$ImmS)))>; 4566249259Sdim 4567249259Sdimdef : Pat<(A64Bfi i32:$src, i32:$Rn, imm:$ImmR, imm:$ImmS), 4568249259Sdim (BFIwwii $src, $Rn, 4569249259Sdim (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4570249259Sdim (bfi_width_to_imms (i64 imm:$ImmS)))>; 4571249259Sdim 4572249259Sdim 4573249259Sdimdef : Pat<(and (A64Bfi i64:$src, i64:$Rn, imm:$ImmR, imm:$ImmS), 4574249259Sdim (i64 4294967295)), 4575249259Sdim (SUBREG_TO_REG (i64 0), 4576249259Sdim (BFIwwii (EXTRACT_SUBREG $src, sub_32), 4577249259Sdim (EXTRACT_SUBREG $Rn, sub_32), 4578249259Sdim (bfi32_lsb_to_immr (i64 imm:$ImmR)), 4579249259Sdim (bfi_width_to_imms (i64 imm:$ImmS))), 4580249259Sdim sub_32)>; 4581249259Sdim 4582249259Sdim} 4583249259Sdim 4584249259Sdim//===----------------------------------------------------------------------===// 4585249259Sdim// Miscellaneous patterns 4586249259Sdim//===----------------------------------------------------------------------===// 4587249259Sdim 4588249259Sdim// Truncation from 64 to 32-bits just involves renaming your register. 4589249259Sdimdef : Pat<(i32 (trunc i64:$val)), (EXTRACT_SUBREG $val, sub_32)>; 4590249259Sdim 4591249259Sdim// Similarly, extension where we don't care about the high bits is 4592249259Sdim// just a rename. 4593249259Sdimdef : Pat<(i64 (anyext i32:$val)), 4594249259Sdim (INSERT_SUBREG (IMPLICIT_DEF), $val, sub_32)>; 4595249259Sdim 4596249259Sdim// SELECT instructions providing f128 types need to be handled by a 4597249259Sdim// pseudo-instruction since the eventual code will need to introduce basic 4598249259Sdim// blocks and control flow. 4599249259Sdimdef F128CSEL : PseudoInst<(outs FPR128:$Rd), 4600249259Sdim (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond), 4601249259Sdim [(set f128:$Rd, (simple_select f128:$Rn, f128:$Rm))]> { 4602249259Sdim let Uses = [NZCV]; 4603249259Sdim let usesCustomInserter = 1; 4604249259Sdim} 4605249259Sdim 4606249259Sdim//===----------------------------------------------------------------------===// 4607249259Sdim// Load/store patterns 4608249259Sdim//===----------------------------------------------------------------------===// 4609249259Sdim 4610249259Sdim// There are lots of patterns here, because we need to allow at least three 4611249259Sdim// parameters to vary independently. 4612249259Sdim// 1. Instruction: "ldrb w9, [sp]", "ldrh w9, [sp]", ... 4613249259Sdim// 2. LLVM source: zextloadi8, anyextloadi8, ... 4614249259Sdim// 3. Address-generation: A64Wrapper, (add BASE, OFFSET), ... 4615249259Sdim// 4616249259Sdim// The biggest problem turns out to be the address-generation variable. At the 4617249259Sdim// point of instantiation we need to produce two DAGs, one for the pattern and 4618249259Sdim// one for the instruction. Doing this at the lowest level of classes doesn't 4619249259Sdim// work. 4620249259Sdim// 4621249259Sdim// Consider the simple uimm12 addressing mode, and the desire to match both (add 4622249259Sdim// GPR64xsp:$Rn, uimm12:$Offset) and GPR64xsp:$Rn, particularly on the 4623249259Sdim// instruction side. We'd need to insert either "GPR64xsp" and "uimm12" or 4624249259Sdim// "GPR64xsp" and "0" into an unknown dag. !subst is not capable of this 4625249259Sdim// operation, and PatFrags are for selection not output. 4626249259Sdim// 4627249259Sdim// As a result, the address-generation patterns are the final 4628249259Sdim// instantiations. However, we do still need to vary the operand for the address 4629249259Sdim// further down (At the point we're deciding A64WrapperSmall, we don't know 4630249259Sdim// the memory width of the operation). 4631249259Sdim 4632249259Sdim//===------------------------------ 4633249259Sdim// 1. Basic infrastructural defs 4634249259Sdim//===------------------------------ 4635249259Sdim 4636249259Sdim// First, some simple classes for !foreach and !subst to use: 4637249259Sdimclass Decls { 4638249259Sdim dag pattern; 4639249259Sdim} 4640249259Sdim 4641249259Sdimdef decls : Decls; 4642249259Sdimdef ALIGN; 4643249259Sdimdef INST; 4644249259Sdimdef OFFSET; 4645249259Sdimdef SHIFT; 4646249259Sdim 4647249259Sdim// You can't use !subst on an actual immediate, but you *can* use it on an 4648249259Sdim// operand record that happens to match a single immediate. So we do. 4649249259Sdimdef imm_eq0 : ImmLeaf<i64, [{ return Imm == 0; }]>; 4650249259Sdimdef imm_eq1 : ImmLeaf<i64, [{ return Imm == 1; }]>; 4651249259Sdimdef imm_eq2 : ImmLeaf<i64, [{ return Imm == 2; }]>; 4652249259Sdimdef imm_eq3 : ImmLeaf<i64, [{ return Imm == 3; }]>; 4653249259Sdimdef imm_eq4 : ImmLeaf<i64, [{ return Imm == 4; }]>; 4654249259Sdim 4655249259Sdim// If the low bits of a pointer are known to be 0 then an "or" is just as good 4656249259Sdim// as addition for computing an offset. This fragment forwards that check for 4657249259Sdim// TableGen's use. 4658249259Sdimdef add_like_or : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), 4659249259Sdim[{ 4660249259Sdim return CurDAG->isBaseWithConstantOffset(SDValue(N, 0)); 4661249259Sdim}]>; 4662249259Sdim 4663249259Sdim// Load/store (unsigned immediate) operations with relocations against global 4664249259Sdim// symbols (for lo12) are only valid if those symbols have correct alignment 4665249259Sdim// (since the immediate offset is divided by the access scale, it can't have a 4666249259Sdim// remainder). 4667249259Sdim// 4668249259Sdim// The guaranteed alignment is provided as part of the WrapperSmall 4669249259Sdim// operation, and checked against one of these. 4670249259Sdimdef any_align : ImmLeaf<i32, [{ (void)Imm; return true; }]>; 4671249259Sdimdef min_align2 : ImmLeaf<i32, [{ return Imm >= 2; }]>; 4672249259Sdimdef min_align4 : ImmLeaf<i32, [{ return Imm >= 4; }]>; 4673249259Sdimdef min_align8 : ImmLeaf<i32, [{ return Imm >= 8; }]>; 4674249259Sdimdef min_align16 : ImmLeaf<i32, [{ return Imm >= 16; }]>; 4675249259Sdim 4676249259Sdim// "Normal" load/store instructions can be used on atomic operations, provided 4677249259Sdim// the ordering parameter is at most "monotonic". Anything above that needs 4678249259Sdim// special handling with acquire/release instructions. 4679249259Sdimclass simple_load<PatFrag base> 4680249259Sdim : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 4681249259Sdim return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4682249259Sdim}]>; 4683249259Sdim 4684249259Sdimdef atomic_load_simple_i8 : simple_load<atomic_load_8>; 4685249259Sdimdef atomic_load_simple_i16 : simple_load<atomic_load_16>; 4686249259Sdimdef atomic_load_simple_i32 : simple_load<atomic_load_32>; 4687249259Sdimdef atomic_load_simple_i64 : simple_load<atomic_load_64>; 4688249259Sdim 4689249259Sdimclass simple_store<PatFrag base> 4690249259Sdim : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 4691249259Sdim return cast<AtomicSDNode>(N)->getOrdering() <= Monotonic; 4692249259Sdim}]>; 4693249259Sdim 4694249259Sdimdef atomic_store_simple_i8 : simple_store<atomic_store_8>; 4695249259Sdimdef atomic_store_simple_i16 : simple_store<atomic_store_16>; 4696249259Sdimdef atomic_store_simple_i32 : simple_store<atomic_store_32>; 4697249259Sdimdef atomic_store_simple_i64 : simple_store<atomic_store_64>; 4698249259Sdim 4699249259Sdim//===------------------------------ 4700249259Sdim// 2. UImm12 and SImm9 4701249259Sdim//===------------------------------ 4702249259Sdim 4703249259Sdim// These instructions have two operands providing the address so they can be 4704249259Sdim// treated similarly for most purposes. 4705249259Sdim 4706249259Sdim//===------------------------------ 4707249259Sdim// 2.1 Base patterns covering extend/truncate semantics 4708249259Sdim//===------------------------------ 4709249259Sdim 4710249259Sdim// Atomic patterns can be shared between integer operations of all sizes, a 4711249259Sdim// quick multiclass here allows reuse. 4712249259Sdimmulticlass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4713249259Sdim dag Offset, dag address, ValueType transty, 4714249259Sdim ValueType sty> { 4715249259Sdim def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4716249259Sdim (LOAD Base, Offset)>; 4717249259Sdim 4718249259Sdim def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4719249259Sdim (STORE $Rt, Base, Offset)>; 4720249259Sdim} 4721249259Sdim 4722249259Sdim// Instructions accessing a memory chunk smaller than a register (or, in a 4723249259Sdim// pinch, the same size) have a characteristic set of patterns they want to 4724249259Sdim// match: extending loads and truncating stores. This class deals with the 4725249259Sdim// sign-neutral version of those patterns. 4726249259Sdim// 4727249259Sdim// It will be instantiated across multiple addressing-modes. 4728249259Sdimmulticlass ls_small_pats<Instruction LOAD, Instruction STORE, 4729249259Sdim dag Base, dag Offset, 4730249259Sdim dag address, ValueType sty> 4731249259Sdim : ls_atomic_pats<LOAD, STORE, Base, Offset, address, i32, sty> { 4732249259Sdim def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>; 4733249259Sdim 4734249259Sdim def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>; 4735249259Sdim 4736249259Sdim // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4737249259Sdim // register was actually set. 4738249259Sdim def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4739249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4740249259Sdim 4741249259Sdim def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4742249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset), sub_32)>; 4743249259Sdim 4744249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4745249259Sdim (STORE $Rt, Base, Offset)>; 4746249259Sdim 4747249259Sdim // For truncating store from 64-bits, we have to manually tell LLVM to 4748249259Sdim // ignore the high bits of the x register. 4749249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4750249259Sdim (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4751249259Sdim} 4752249259Sdim 4753249259Sdim// Next come patterns for sign-extending loads. 4754249259Sdimmulticlass load_signed_pats<string T, string U, dag Base, dag Offset, 4755249259Sdim dag address, ValueType sty> { 4756249259Sdim def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4757249259Sdim (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>; 4758249259Sdim 4759249259Sdim def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 4760249259Sdim (!cast<Instruction>("LDRS" # T # "x" # U) Base, Offset)>; 4761249259Sdim 4762249259Sdim} 4763249259Sdim 4764249259Sdim// and finally "natural-width" loads and stores come next. 4765249259Sdimmulticlass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4766249259Sdim dag Offset, dag address, ValueType sty> { 4767249259Sdim def : Pat<(sty (load address)), (LOAD Base, Offset)>; 4768249259Sdim def : Pat<(store sty:$Rt, address), (STORE $Rt, Base, Offset)>; 4769249259Sdim} 4770249259Sdim 4771249259Sdim// Integer operations also get atomic instructions to select for. 4772249259Sdimmulticlass ls_int_neutral_pats<Instruction LOAD, Instruction STORE, dag Base, 4773249259Sdim dag Offset, dag address, ValueType sty> 4774249259Sdim : ls_neutral_pats<LOAD, STORE, Base, Offset, address, sty>, 4775249259Sdim ls_atomic_pats<LOAD, STORE, Base, Offset, address, sty, sty>; 4776249259Sdim 4777249259Sdim//===------------------------------ 4778249259Sdim// 2.2. Addressing-mode instantiations 4779249259Sdim//===------------------------------ 4780249259Sdim 4781249259Sdimmulticlass uimm12_pats<dag address, dag Base, dag Offset> { 4782249259Sdim defm : ls_small_pats<LS8_LDR, LS8_STR, Base, 4783249259Sdim !foreach(decls.pattern, Offset, 4784249259Sdim !subst(OFFSET, byte_uimm12, decls.pattern)), 4785249259Sdim !foreach(decls.pattern, address, 4786249259Sdim !subst(OFFSET, byte_uimm12, 4787249259Sdim !subst(ALIGN, any_align, decls.pattern))), 4788249259Sdim i8>; 4789249259Sdim defm : ls_small_pats<LS16_LDR, LS16_STR, Base, 4790249259Sdim !foreach(decls.pattern, Offset, 4791249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4792249259Sdim !foreach(decls.pattern, address, 4793249259Sdim !subst(OFFSET, hword_uimm12, 4794249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4795249259Sdim i16>; 4796249259Sdim defm : ls_small_pats<LS32_LDR, LS32_STR, Base, 4797249259Sdim !foreach(decls.pattern, Offset, 4798249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4799249259Sdim !foreach(decls.pattern, address, 4800249259Sdim !subst(OFFSET, word_uimm12, 4801249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4802249259Sdim i32>; 4803249259Sdim 4804249259Sdim defm : ls_int_neutral_pats<LS32_LDR, LS32_STR, Base, 4805249259Sdim !foreach(decls.pattern, Offset, 4806249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4807249259Sdim !foreach(decls.pattern, address, 4808249259Sdim !subst(OFFSET, word_uimm12, 4809249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4810249259Sdim i32>; 4811249259Sdim 4812249259Sdim defm : ls_int_neutral_pats<LS64_LDR, LS64_STR, Base, 4813249259Sdim !foreach(decls.pattern, Offset, 4814249259Sdim !subst(OFFSET, dword_uimm12, decls.pattern)), 4815249259Sdim !foreach(decls.pattern, address, 4816249259Sdim !subst(OFFSET, dword_uimm12, 4817249259Sdim !subst(ALIGN, min_align8, decls.pattern))), 4818249259Sdim i64>; 4819249259Sdim 4820249259Sdim defm : ls_neutral_pats<LSFP16_LDR, LSFP16_STR, Base, 4821249259Sdim !foreach(decls.pattern, Offset, 4822249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4823249259Sdim !foreach(decls.pattern, address, 4824249259Sdim !subst(OFFSET, hword_uimm12, 4825249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4826249259Sdim f16>; 4827249259Sdim 4828249259Sdim defm : ls_neutral_pats<LSFP32_LDR, LSFP32_STR, Base, 4829249259Sdim !foreach(decls.pattern, Offset, 4830249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)), 4831249259Sdim !foreach(decls.pattern, address, 4832249259Sdim !subst(OFFSET, word_uimm12, 4833249259Sdim !subst(ALIGN, min_align4, decls.pattern))), 4834249259Sdim f32>; 4835249259Sdim 4836249259Sdim defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base, 4837249259Sdim !foreach(decls.pattern, Offset, 4838249259Sdim !subst(OFFSET, dword_uimm12, decls.pattern)), 4839249259Sdim !foreach(decls.pattern, address, 4840249259Sdim !subst(OFFSET, dword_uimm12, 4841249259Sdim !subst(ALIGN, min_align8, decls.pattern))), 4842249259Sdim f64>; 4843249259Sdim 4844249259Sdim defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base, 4845249259Sdim !foreach(decls.pattern, Offset, 4846249259Sdim !subst(OFFSET, qword_uimm12, decls.pattern)), 4847249259Sdim !foreach(decls.pattern, address, 4848249259Sdim !subst(OFFSET, qword_uimm12, 4849249259Sdim !subst(ALIGN, min_align16, decls.pattern))), 4850249259Sdim f128>; 4851249259Sdim 4852249259Sdim defm : load_signed_pats<"B", "", Base, 4853249259Sdim !foreach(decls.pattern, Offset, 4854249259Sdim !subst(OFFSET, byte_uimm12, decls.pattern)), 4855249259Sdim !foreach(decls.pattern, address, 4856249259Sdim !subst(OFFSET, byte_uimm12, 4857249259Sdim !subst(ALIGN, any_align, decls.pattern))), 4858249259Sdim i8>; 4859249259Sdim 4860249259Sdim defm : load_signed_pats<"H", "", Base, 4861249259Sdim !foreach(decls.pattern, Offset, 4862249259Sdim !subst(OFFSET, hword_uimm12, decls.pattern)), 4863249259Sdim !foreach(decls.pattern, address, 4864249259Sdim !subst(OFFSET, hword_uimm12, 4865249259Sdim !subst(ALIGN, min_align2, decls.pattern))), 4866249259Sdim i16>; 4867249259Sdim 4868249259Sdim def : Pat<(sextloadi32 !foreach(decls.pattern, address, 4869249259Sdim !subst(OFFSET, word_uimm12, 4870249259Sdim !subst(ALIGN, min_align4, decls.pattern)))), 4871249259Sdim (LDRSWx Base, !foreach(decls.pattern, Offset, 4872249259Sdim !subst(OFFSET, word_uimm12, decls.pattern)))>; 4873249259Sdim} 4874249259Sdim 4875249259Sdim// Straightforward patterns of last resort: a pointer with or without an 4876249259Sdim// appropriate offset. 4877249259Sdimdefm : uimm12_pats<(i64 i64:$Rn), (i64 i64:$Rn), (i64 0)>; 4878249259Sdimdefm : uimm12_pats<(add i64:$Rn, OFFSET:$UImm12), 4879249259Sdim (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4880249259Sdim 4881249259Sdim// The offset could be hidden behind an "or", of course: 4882249259Sdimdefm : uimm12_pats<(add_like_or i64:$Rn, OFFSET:$UImm12), 4883249259Sdim (i64 i64:$Rn), (i64 OFFSET:$UImm12)>; 4884249259Sdim 4885249259Sdim// Global addresses under the small-absolute model should use these 4886249259Sdim// instructions. There are ELF relocations specifically for it. 4887249259Sdimdefm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN), 4888249259Sdim (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>; 4889249259Sdim 4890249259Sdimdefm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, 4891249259Sdim ALIGN), 4892249259Sdim (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>; 4893249259Sdim 4894249259Sdim// External symbols that make it this far should also get standard relocations. 4895249259Sdimdefm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, 4896249259Sdim ALIGN), 4897249259Sdim (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>; 4898249259Sdim 4899249259Sdimdefm : uimm12_pats<(A64WrapperSmall tconstpool:$Hi, tconstpool:$Lo12, ALIGN), 4900249259Sdim (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>; 4901249259Sdim 4902249259Sdim// We also want to use uimm12 instructions for local variables at the moment. 4903249259Sdimdef tframeindex_XFORM : SDNodeXForm<frameindex, [{ 4904249259Sdim int FI = cast<FrameIndexSDNode>(N)->getIndex(); 4905249259Sdim return CurDAG->getTargetFrameIndex(FI, MVT::i64); 4906249259Sdim}]>; 4907249259Sdim 4908249259Sdimdefm : uimm12_pats<(i64 frameindex:$Rn), 4909249259Sdim (tframeindex_XFORM tframeindex:$Rn), (i64 0)>; 4910249259Sdim 4911249259Sdim// These can be much simpler than uimm12 because we don't to change the operand 4912249259Sdim// type (e.g. LDURB and LDURH take the same operands). 4913249259Sdimmulticlass simm9_pats<dag address, dag Base, dag Offset> { 4914249259Sdim defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>; 4915249259Sdim defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>; 4916249259Sdim 4917249259Sdim defm : ls_int_neutral_pats<LS32_LDUR, LS32_STUR, Base, Offset, address, i32>; 4918249259Sdim defm : ls_int_neutral_pats<LS64_LDUR, LS64_STUR, Base, Offset, address, i64>; 4919249259Sdim 4920249259Sdim defm : ls_neutral_pats<LSFP16_LDUR, LSFP16_STUR, Base, Offset, address, f16>; 4921249259Sdim defm : ls_neutral_pats<LSFP32_LDUR, LSFP32_STUR, Base, Offset, address, f32>; 4922249259Sdim defm : ls_neutral_pats<LSFP64_LDUR, LSFP64_STUR, Base, Offset, address, f64>; 4923249259Sdim defm : ls_neutral_pats<LSFP128_LDUR, LSFP128_STUR, Base, Offset, address, 4924249259Sdim f128>; 4925249259Sdim 4926249259Sdim def : Pat<(i64 (zextloadi32 address)), 4927249259Sdim (SUBREG_TO_REG (i64 0), (LS32_LDUR Base, Offset), sub_32)>; 4928249259Sdim 4929249259Sdim def : Pat<(truncstorei32 i64:$Rt, address), 4930249259Sdim (LS32_STUR (EXTRACT_SUBREG $Rt, sub_32), Base, Offset)>; 4931249259Sdim 4932249259Sdim defm : load_signed_pats<"B", "_U", Base, Offset, address, i8>; 4933249259Sdim defm : load_signed_pats<"H", "_U", Base, Offset, address, i16>; 4934249259Sdim def : Pat<(sextloadi32 address), (LDURSWx Base, Offset)>; 4935249259Sdim} 4936249259Sdim 4937249259Sdimdefm : simm9_pats<(add i64:$Rn, simm9:$SImm9), 4938249259Sdim (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 4939249259Sdim 4940249259Sdimdefm : simm9_pats<(add_like_or i64:$Rn, simm9:$SImm9), 4941249259Sdim (i64 $Rn), (SDXF_simm9 simm9:$SImm9)>; 4942249259Sdim 4943249259Sdim 4944249259Sdim//===------------------------------ 4945249259Sdim// 3. Register offset patterns 4946249259Sdim//===------------------------------ 4947249259Sdim 4948249259Sdim// Atomic patterns can be shared between integer operations of all sizes, a 4949249259Sdim// quick multiclass here allows reuse. 4950249259Sdimmulticlass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base, 4951249259Sdim dag Offset, dag Extend, dag address, 4952249259Sdim ValueType transty, ValueType sty> { 4953249259Sdim def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address), 4954249259Sdim (LOAD Base, Offset, Extend)>; 4955249259Sdim 4956249259Sdim def : Pat<(!cast<PatFrag>("atomic_store_simple_" # sty) address, transty:$Rt), 4957249259Sdim (STORE $Rt, Base, Offset, Extend)>; 4958249259Sdim} 4959249259Sdim 4960249259Sdim// The register offset instructions take three operands giving the instruction, 4961249259Sdim// and have an annoying split between instructions where Rm is 32-bit and 4962249259Sdim// 64-bit. So we need a special hierarchy to describe them. Other than that the 4963249259Sdim// same operations should be supported as for simm9 and uimm12 addressing. 4964249259Sdim 4965249259Sdimmulticlass ro_small_pats<Instruction LOAD, Instruction STORE, 4966249259Sdim dag Base, dag Offset, dag Extend, 4967249259Sdim dag address, ValueType sty> 4968249259Sdim : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, i32, sty> { 4969249259Sdim def : Pat<(!cast<SDNode>(zextload # sty) address), 4970249259Sdim (LOAD Base, Offset, Extend)>; 4971249259Sdim 4972249259Sdim def : Pat<(!cast<SDNode>(extload # sty) address), 4973249259Sdim (LOAD Base, Offset, Extend)>; 4974249259Sdim 4975249259Sdim // For zero-extension to 64-bits we have to tell LLVM that the whole 64-bit 4976249259Sdim // register was actually set. 4977249259Sdim def : Pat<(i64 (!cast<SDNode>(zextload # sty) address)), 4978249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 4979249259Sdim 4980249259Sdim def : Pat<(i64 (!cast<SDNode>(extload # sty) address)), 4981249259Sdim (SUBREG_TO_REG (i64 0), (LOAD Base, Offset, Extend), sub_32)>; 4982249259Sdim 4983249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i32:$Rt, address), 4984249259Sdim (STORE $Rt, Base, Offset, Extend)>; 4985249259Sdim 4986249259Sdim // For truncating store from 64-bits, we have to manually tell LLVM to 4987249259Sdim // ignore the high bits of the x register. 4988249259Sdim def : Pat<(!cast<SDNode>(truncstore # sty) i64:$Rt, address), 4989249259Sdim (STORE (EXTRACT_SUBREG $Rt, sub_32), Base, Offset, Extend)>; 4990249259Sdim 4991249259Sdim} 4992249259Sdim 4993249259Sdim// Next come patterns for sign-extending loads. 4994249259Sdimmulticlass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend, 4995249259Sdim dag address, ValueType sty> { 4996249259Sdim def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)), 4997249259Sdim (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset") 4998249259Sdim Base, Offset, Extend)>; 4999249259Sdim 5000249259Sdim def : Pat<(i64 (!cast<SDNode>("sextload" # sty) address)), 5001249259Sdim (!cast<Instruction>("LDRS" # T # "x_" # Rm # "_RegOffset") 5002249259Sdim Base, Offset, Extend)>; 5003249259Sdim} 5004249259Sdim 5005249259Sdim// and finally "natural-width" loads and stores come next. 5006249259Sdimmulticlass ro_neutral_pats<Instruction LOAD, Instruction STORE, 5007249259Sdim dag Base, dag Offset, dag Extend, dag address, 5008249259Sdim ValueType sty> { 5009249259Sdim def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>; 5010249259Sdim def : Pat<(store sty:$Rt, address), 5011249259Sdim (STORE $Rt, Base, Offset, Extend)>; 5012249259Sdim} 5013249259Sdim 5014249259Sdimmulticlass ro_int_neutral_pats<Instruction LOAD, Instruction STORE, 5015249259Sdim dag Base, dag Offset, dag Extend, dag address, 5016249259Sdim ValueType sty> 5017249259Sdim : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, sty>, 5018249259Sdim ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, sty, sty>; 5019249259Sdim 5020249259Sdimmulticlass regoff_pats<string Rm, dag address, dag Base, dag Offset, 5021249259Sdim dag Extend> { 5022249259Sdim defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"), 5023249259Sdim !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"), 5024249259Sdim Base, Offset, Extend, 5025249259Sdim !foreach(decls.pattern, address, 5026249259Sdim !subst(SHIFT, imm_eq0, decls.pattern)), 5027249259Sdim i8>; 5028249259Sdim defm : ro_small_pats<!cast<Instruction>("LS16_" # Rm # "_RegOffset_LDR"), 5029249259Sdim !cast<Instruction>("LS16_" # Rm # "_RegOffset_STR"), 5030249259Sdim Base, Offset, Extend, 5031249259Sdim !foreach(decls.pattern, address, 5032249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5033249259Sdim i16>; 5034249259Sdim defm : ro_small_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5035249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5036249259Sdim Base, Offset, Extend, 5037249259Sdim !foreach(decls.pattern, address, 5038249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5039249259Sdim i32>; 5040249259Sdim 5041249259Sdim defm : ro_int_neutral_pats< 5042249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"), 5043249259Sdim !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"), 5044249259Sdim Base, Offset, Extend, 5045249259Sdim !foreach(decls.pattern, address, 5046249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5047249259Sdim i32>; 5048249259Sdim 5049249259Sdim defm : ro_int_neutral_pats< 5050249259Sdim !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"), 5051249259Sdim !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"), 5052249259Sdim Base, Offset, Extend, 5053249259Sdim !foreach(decls.pattern, address, 5054249259Sdim !subst(SHIFT, imm_eq3, decls.pattern)), 5055249259Sdim i64>; 5056249259Sdim 5057249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"), 5058249259Sdim !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"), 5059249259Sdim Base, Offset, Extend, 5060249259Sdim !foreach(decls.pattern, address, 5061249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5062249259Sdim f16>; 5063249259Sdim 5064249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP32_" # Rm # "_RegOffset_LDR"), 5065249259Sdim !cast<Instruction>("LSFP32_" # Rm # "_RegOffset_STR"), 5066249259Sdim Base, Offset, Extend, 5067249259Sdim !foreach(decls.pattern, address, 5068249259Sdim !subst(SHIFT, imm_eq2, decls.pattern)), 5069249259Sdim f32>; 5070249259Sdim 5071249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP64_" # Rm # "_RegOffset_LDR"), 5072249259Sdim !cast<Instruction>("LSFP64_" # Rm # "_RegOffset_STR"), 5073249259Sdim Base, Offset, Extend, 5074249259Sdim !foreach(decls.pattern, address, 5075249259Sdim !subst(SHIFT, imm_eq3, decls.pattern)), 5076249259Sdim f64>; 5077249259Sdim 5078249259Sdim defm : ro_neutral_pats<!cast<Instruction>("LSFP128_" # Rm # "_RegOffset_LDR"), 5079249259Sdim !cast<Instruction>("LSFP128_" # Rm # "_RegOffset_STR"), 5080249259Sdim Base, Offset, Extend, 5081249259Sdim !foreach(decls.pattern, address, 5082249259Sdim !subst(SHIFT, imm_eq4, decls.pattern)), 5083249259Sdim f128>; 5084249259Sdim 5085249259Sdim defm : ro_signed_pats<"B", Rm, Base, Offset, Extend, 5086249259Sdim !foreach(decls.pattern, address, 5087249259Sdim !subst(SHIFT, imm_eq0, decls.pattern)), 5088249259Sdim i8>; 5089249259Sdim 5090249259Sdim defm : ro_signed_pats<"H", Rm, Base, Offset, Extend, 5091249259Sdim !foreach(decls.pattern, address, 5092249259Sdim !subst(SHIFT, imm_eq1, decls.pattern)), 5093249259Sdim i16>; 5094249259Sdim 5095249259Sdim def : Pat<(sextloadi32 !foreach(decls.pattern, address, 5096249259Sdim !subst(SHIFT, imm_eq2, decls.pattern))), 5097249259Sdim (!cast<Instruction>("LDRSWx_" # Rm # "_RegOffset") 5098249259Sdim Base, Offset, Extend)>; 5099249259Sdim} 5100249259Sdim 5101249259Sdim 5102249259Sdim// Finally we're in a position to tell LLVM exactly what addresses are reachable 5103249259Sdim// using register-offset instructions. Essentially a base plus a possibly 5104249259Sdim// extended, possibly shifted (by access size) offset. 5105249259Sdim 5106249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (sext i32:$Rm)), 5107249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 6)>; 5108249259Sdim 5109249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (shl (sext i32:$Rm), SHIFT)), 5110249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 7)>; 5111249259Sdim 5112249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (zext i32:$Rm)), 5113249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 2)>; 5114249259Sdim 5115249259Sdimdefm : regoff_pats<"Wm", (add i64:$Rn, (shl (zext i32:$Rm), SHIFT)), 5116249259Sdim (i64 i64:$Rn), (i32 i32:$Rm), (i64 3)>; 5117249259Sdim 5118249259Sdimdefm : regoff_pats<"Xm", (add i64:$Rn, i64:$Rm), 5119249259Sdim (i64 i64:$Rn), (i64 i64:$Rm), (i64 2)>; 5120249259Sdim 5121249259Sdimdefm : regoff_pats<"Xm", (add i64:$Rn, (shl i64:$Rm, SHIFT)), 5122249259Sdim (i64 i64:$Rn), (i64 i64:$Rm), (i64 3)>; 5123