AArch64InstrFormats.td revision 249259
1249259Sdim//===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tablegen -*-=// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// This file describes AArch64 instruction formats, down to the level of the 10249259Sdim// instruction's overall class. 11249259Sdim// ===----------------------------------------------------------------------===// 12249259Sdim 13249259Sdim 14249259Sdim//===----------------------------------------------------------------------===// 15249259Sdim// A64 Instruction Format Definitions. 16249259Sdim//===----------------------------------------------------------------------===// 17249259Sdim 18249259Sdim// A64 is currently the only instruction set supported by the AArch64 19249259Sdim// architecture. 20249259Sdimclass A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns, 21249259Sdim InstrItinClass itin> 22249259Sdim : Instruction { 23249259Sdim // All A64 instructions are 32-bit. This field will be filled in 24249259Sdim // gradually going down the hierarchy. 25249259Sdim field bits<32> Inst; 26249259Sdim 27249259Sdim field bits<32> Unpredictable = 0; 28249259Sdim // SoftFail is the generic name for this field, but we alias it so 29249259Sdim // as to make it more obvious what it means in ARM-land. 30249259Sdim field bits<32> SoftFail = Unpredictable; 31249259Sdim 32249259Sdim // LLVM-level model of the AArch64/A64 distinction. 33249259Sdim let Namespace = "AArch64"; 34249259Sdim let DecoderNamespace = "A64"; 35249259Sdim let Size = 4; 36249259Sdim 37249259Sdim // Set the templated fields 38249259Sdim let OutOperandList = outs; 39249259Sdim let InOperandList = ins; 40249259Sdim let AsmString = asmstr; 41249259Sdim let Pattern = patterns; 42249259Sdim let Itinerary = itin; 43249259Sdim} 44249259Sdim 45249259Sdimclass PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction { 46249259Sdim let Namespace = "AArch64"; 47249259Sdim 48249259Sdim let OutOperandList = outs; 49249259Sdim let InOperandList= ins; 50249259Sdim let Pattern = patterns; 51249259Sdim let isCodeGenOnly = 1; 52249259Sdim let isPseudo = 1; 53249259Sdim} 54249259Sdim 55249259Sdim// Represents a pseudo-instruction that represents a single A64 instruction for 56249259Sdim// whatever reason, the eventual result will be a 32-bit real instruction. 57249259Sdimclass A64PseudoInst<dag outs, dag ins, list<dag> patterns> 58249259Sdim : PseudoInst<outs, ins, patterns> { 59249259Sdim let Size = 4; 60249259Sdim} 61249259Sdim 62249259Sdim// As above, this will be a single A64 instruction, but we can actually give the 63249259Sdim// expansion in TableGen. 64249259Sdimclass A64PseudoExpand<dag outs, dag ins, list<dag> patterns, dag Result> 65249259Sdim : A64PseudoInst<outs, ins, patterns>, 66249259Sdim PseudoInstExpansion<Result>; 67249259Sdim 68249259Sdim 69249259Sdim// First, some common cross-hierarchy register formats. 70249259Sdim 71249259Sdimclass A64InstRd<dag outs, dag ins, string asmstr, 72249259Sdim list<dag> patterns, InstrItinClass itin> 73249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 74249259Sdim bits<5> Rd; 75249259Sdim 76249259Sdim let Inst{4-0} = Rd; 77249259Sdim} 78249259Sdim 79249259Sdimclass A64InstRt<dag outs, dag ins, string asmstr, 80249259Sdim list<dag> patterns, InstrItinClass itin> 81249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 82249259Sdim bits<5> Rt; 83249259Sdim 84249259Sdim let Inst{4-0} = Rt; 85249259Sdim} 86249259Sdim 87249259Sdim 88249259Sdimclass A64InstRdn<dag outs, dag ins, string asmstr, 89249259Sdim list<dag> patterns, InstrItinClass itin> 90249259Sdim : A64InstRd<outs, ins, asmstr, patterns, itin> { 91249259Sdim // Inherit rdt 92249259Sdim bits<5> Rn; 93249259Sdim 94249259Sdim let Inst{9-5} = Rn; 95249259Sdim} 96249259Sdim 97249259Sdimclass A64InstRtn<dag outs, dag ins, string asmstr, 98249259Sdim list<dag> patterns, InstrItinClass itin> 99249259Sdim : A64InstRt<outs, ins, asmstr, patterns, itin> { 100249259Sdim // Inherit rdt 101249259Sdim bits<5> Rn; 102249259Sdim 103249259Sdim let Inst{9-5} = Rn; 104249259Sdim} 105249259Sdim 106249259Sdim// Instructions taking Rt,Rt2,Rn 107249259Sdimclass A64InstRtt2n<dag outs, dag ins, string asmstr, 108249259Sdim list<dag> patterns, InstrItinClass itin> 109249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 110249259Sdim bits<5> Rt2; 111249259Sdim 112249259Sdim let Inst{14-10} = Rt2; 113249259Sdim} 114249259Sdim 115249259Sdimclass A64InstRdnm<dag outs, dag ins, string asmstr, 116249259Sdim list<dag> patterns, InstrItinClass itin> 117249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 118249259Sdim bits<5> Rm; 119249259Sdim 120249259Sdim let Inst{20-16} = Rm; 121249259Sdim} 122249259Sdim 123249259Sdim//===----------------------------------------------------------------------===// 124249259Sdim// 125249259Sdim// Actual A64 Instruction Formats 126249259Sdim// 127249259Sdim 128249259Sdim// Format for Add-subtract (extended register) instructions. 129249259Sdimclass A64I_addsubext<bit sf, bit op, bit S, bits<2> opt, bits<3> option, 130249259Sdim dag outs, dag ins, string asmstr, list<dag> patterns, 131249259Sdim InstrItinClass itin> 132249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 133249259Sdim bits<3> Imm3; 134249259Sdim 135249259Sdim let Inst{31} = sf; 136249259Sdim let Inst{30} = op; 137249259Sdim let Inst{29} = S; 138249259Sdim let Inst{28-24} = 0b01011; 139249259Sdim let Inst{23-22} = opt; 140249259Sdim let Inst{21} = 0b1; 141249259Sdim // Rm inherited in 20-16 142249259Sdim let Inst{15-13} = option; 143249259Sdim let Inst{12-10} = Imm3; 144249259Sdim // Rn inherited in 9-5 145249259Sdim // Rd inherited in 4-0 146249259Sdim} 147249259Sdim 148249259Sdim// Format for Add-subtract (immediate) instructions. 149249259Sdimclass A64I_addsubimm<bit sf, bit op, bit S, bits<2> shift, 150249259Sdim dag outs, dag ins, string asmstr, 151249259Sdim list<dag> patterns, InstrItinClass itin> 152249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 153249259Sdim bits<12> Imm12; 154249259Sdim 155249259Sdim let Inst{31} = sf; 156249259Sdim let Inst{30} = op; 157249259Sdim let Inst{29} = S; 158249259Sdim let Inst{28-24} = 0b10001; 159249259Sdim let Inst{23-22} = shift; 160249259Sdim let Inst{21-10} = Imm12; 161249259Sdim} 162249259Sdim 163249259Sdim// Format for Add-subtract (shifted register) instructions. 164249259Sdimclass A64I_addsubshift<bit sf, bit op, bit S, bits<2> shift, 165249259Sdim dag outs, dag ins, string asmstr, list<dag> patterns, 166249259Sdim InstrItinClass itin> 167249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 168249259Sdim bits<6> Imm6; 169249259Sdim 170249259Sdim let Inst{31} = sf; 171249259Sdim let Inst{30} = op; 172249259Sdim let Inst{29} = S; 173249259Sdim let Inst{28-24} = 0b01011; 174249259Sdim let Inst{23-22} = shift; 175249259Sdim let Inst{21} = 0b0; 176249259Sdim // Rm inherited in 20-16 177249259Sdim let Inst{15-10} = Imm6; 178249259Sdim // Rn inherited in 9-5 179249259Sdim // Rd inherited in 4-0 180249259Sdim} 181249259Sdim 182249259Sdim// Format for Add-subtract (with carry) instructions. 183249259Sdimclass A64I_addsubcarry<bit sf, bit op, bit S, bits<6> opcode2, 184249259Sdim dag outs, dag ins, string asmstr, list<dag> patterns, 185249259Sdim InstrItinClass itin> 186249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 187249259Sdim let Inst{31} = sf; 188249259Sdim let Inst{30} = op; 189249259Sdim let Inst{29} = S; 190249259Sdim let Inst{28-21} = 0b11010000; 191249259Sdim // Rm inherited in 20-16 192249259Sdim let Inst{15-10} = opcode2; 193249259Sdim // Rn inherited in 9-5 194249259Sdim // Rd inherited in 4-0 195249259Sdim} 196249259Sdim 197249259Sdim 198249259Sdim// Format for Bitfield instructions 199249259Sdimclass A64I_bitfield<bit sf, bits<2> opc, bit n, 200249259Sdim dag outs, dag ins, string asmstr, 201249259Sdim list<dag> patterns, InstrItinClass itin> 202249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 203249259Sdim bits<6> ImmR; 204249259Sdim bits<6> ImmS; 205249259Sdim 206249259Sdim let Inst{31} = sf; 207249259Sdim let Inst{30-29} = opc; 208249259Sdim let Inst{28-23} = 0b100110; 209249259Sdim let Inst{22} = n; 210249259Sdim let Inst{21-16} = ImmR; 211249259Sdim let Inst{15-10} = ImmS; 212249259Sdim // Inherit Rn in 9-5 213249259Sdim // Inherit Rd in 4-0 214249259Sdim} 215249259Sdim 216249259Sdim// Format for compare and branch (immediate) instructions. 217249259Sdimclass A64I_cmpbr<bit sf, bit op, 218249259Sdim dag outs, dag ins, string asmstr, 219249259Sdim list<dag> patterns, InstrItinClass itin> 220249259Sdim : A64InstRt<outs, ins, asmstr, patterns, itin> { 221249259Sdim bits<19> Label; 222249259Sdim 223249259Sdim let Inst{31} = sf; 224249259Sdim let Inst{30-25} = 0b011010; 225249259Sdim let Inst{24} = op; 226249259Sdim let Inst{23-5} = Label; 227249259Sdim // Inherit Rt in 4-0 228249259Sdim} 229249259Sdim 230249259Sdim// Format for conditional branch (immediate) instructions. 231249259Sdimclass A64I_condbr<bit o1, bit o0, 232249259Sdim dag outs, dag ins, string asmstr, 233249259Sdim list<dag> patterns, InstrItinClass itin> 234249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 235249259Sdim bits<19> Label; 236249259Sdim bits<4> Cond; 237249259Sdim 238249259Sdim let Inst{31-25} = 0b0101010; 239249259Sdim let Inst{24} = o1; 240249259Sdim let Inst{23-5} = Label; 241249259Sdim let Inst{4} = o0; 242249259Sdim let Inst{3-0} = Cond; 243249259Sdim} 244249259Sdim 245249259Sdim// Format for conditional compare (immediate) instructions. 246249259Sdimclass A64I_condcmpimm<bit sf, bit op, bit o2, bit o3, bit s, 247249259Sdim dag outs, dag ins, string asmstr, 248249259Sdim list<dag> patterns, InstrItinClass itin> 249249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 250249259Sdim bits<5> Rn; 251249259Sdim bits<5> UImm5; 252249259Sdim bits<4> NZCVImm; 253249259Sdim bits<4> Cond; 254249259Sdim 255249259Sdim let Inst{31} = sf; 256249259Sdim let Inst{30} = op; 257249259Sdim let Inst{29} = s; 258249259Sdim let Inst{28-21} = 0b11010010; 259249259Sdim let Inst{20-16} = UImm5; 260249259Sdim let Inst{15-12} = Cond; 261249259Sdim let Inst{11} = 0b1; 262249259Sdim let Inst{10} = o2; 263249259Sdim let Inst{9-5} = Rn; 264249259Sdim let Inst{4} = o3; 265249259Sdim let Inst{3-0} = NZCVImm; 266249259Sdim} 267249259Sdim 268249259Sdim// Format for conditional compare (register) instructions. 269249259Sdimclass A64I_condcmpreg<bit sf, bit op, bit o2, bit o3, bit s, 270249259Sdim dag outs, dag ins, string asmstr, 271249259Sdim list<dag> patterns, InstrItinClass itin> 272249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 273249259Sdim bits<5> Rn; 274249259Sdim bits<5> Rm; 275249259Sdim bits<4> NZCVImm; 276249259Sdim bits<4> Cond; 277249259Sdim 278249259Sdim 279249259Sdim let Inst{31} = sf; 280249259Sdim let Inst{30} = op; 281249259Sdim let Inst{29} = s; 282249259Sdim let Inst{28-21} = 0b11010010; 283249259Sdim let Inst{20-16} = Rm; 284249259Sdim let Inst{15-12} = Cond; 285249259Sdim let Inst{11} = 0b0; 286249259Sdim let Inst{10} = o2; 287249259Sdim let Inst{9-5} = Rn; 288249259Sdim let Inst{4} = o3; 289249259Sdim let Inst{3-0} = NZCVImm; 290249259Sdim} 291249259Sdim 292249259Sdim// Format for conditional select instructions. 293249259Sdimclass A64I_condsel<bit sf, bit op, bit s, bits<2> op2, 294249259Sdim dag outs, dag ins, string asmstr, 295249259Sdim list<dag> patterns, InstrItinClass itin> 296249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 297249259Sdim bits<4> Cond; 298249259Sdim 299249259Sdim let Inst{31} = sf; 300249259Sdim let Inst{30} = op; 301249259Sdim let Inst{29} = s; 302249259Sdim let Inst{28-21} = 0b11010100; 303249259Sdim // Inherit Rm in 20-16 304249259Sdim let Inst{15-12} = Cond; 305249259Sdim let Inst{11-10} = op2; 306249259Sdim // Inherit Rn in 9-5 307249259Sdim // Inherit Rd in 4-0 308249259Sdim} 309249259Sdim 310249259Sdim// Format for data processing (1 source) instructions 311249259Sdimclass A64I_dp_1src<bit sf, bit S, bits<5> opcode2, bits<6> opcode, 312249259Sdim string asmstr, dag outs, dag ins, 313249259Sdim list<dag> patterns, InstrItinClass itin> 314249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 315249259Sdim let Inst{31} = sf; 316249259Sdim let Inst{30} = 0b1; 317249259Sdim let Inst{29} = S; 318249259Sdim let Inst{28-21} = 0b11010110; 319249259Sdim let Inst{20-16} = opcode2; 320249259Sdim let Inst{15-10} = opcode; 321249259Sdim} 322249259Sdim 323249259Sdim// Format for data processing (2 source) instructions 324249259Sdimclass A64I_dp_2src<bit sf, bits<6> opcode, bit S, 325249259Sdim string asmstr, dag outs, dag ins, 326249259Sdim list<dag> patterns, InstrItinClass itin> 327249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 328249259Sdim let Inst{31} = sf; 329249259Sdim let Inst{30} = 0b0; 330249259Sdim let Inst{29} = S; 331249259Sdim let Inst{28-21} = 0b11010110; 332249259Sdim let Inst{15-10} = opcode; 333249259Sdim} 334249259Sdim 335249259Sdim// Format for data-processing (3 source) instructions 336249259Sdim 337249259Sdimclass A64I_dp3<bit sf, bits<6> opcode, 338249259Sdim dag outs, dag ins, string asmstr, 339249259Sdim list<dag> patterns, InstrItinClass itin> 340249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 341249259Sdim bits<5> Ra; 342249259Sdim 343249259Sdim let Inst{31} = sf; 344249259Sdim let Inst{30-29} = opcode{5-4}; 345249259Sdim let Inst{28-24} = 0b11011; 346249259Sdim let Inst{23-21} = opcode{3-1}; 347249259Sdim // Inherits Rm in 20-16 348249259Sdim let Inst{15} = opcode{0}; 349249259Sdim let Inst{14-10} = Ra; 350249259Sdim // Inherits Rn in 9-5 351249259Sdim // Inherits Rd in 4-0 352249259Sdim} 353249259Sdim 354249259Sdim// Format for exception generation instructions 355249259Sdimclass A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll, 356249259Sdim dag outs, dag ins, string asmstr, 357249259Sdim list<dag> patterns, InstrItinClass itin> 358249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 359249259Sdim bits<16> UImm16; 360249259Sdim 361249259Sdim let Inst{31-24} = 0b11010100; 362249259Sdim let Inst{23-21} = opc; 363249259Sdim let Inst{20-5} = UImm16; 364249259Sdim let Inst{4-2} = op2; 365249259Sdim let Inst{1-0} = ll; 366249259Sdim} 367249259Sdim 368249259Sdim// Format for extract (immediate) instructions 369249259Sdimclass A64I_extract<bit sf, bits<3> op, bit n, 370249259Sdim dag outs, dag ins, string asmstr, 371249259Sdim list<dag> patterns, InstrItinClass itin> 372249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 373249259Sdim bits<6> LSB; 374249259Sdim 375249259Sdim let Inst{31} = sf; 376249259Sdim let Inst{30-29} = op{2-1}; 377249259Sdim let Inst{28-23} = 0b100111; 378249259Sdim let Inst{22} = n; 379249259Sdim let Inst{21} = op{0}; 380249259Sdim // Inherits Rm in bits 20-16 381249259Sdim let Inst{15-10} = LSB; 382249259Sdim // Inherits Rn in 9-5 383249259Sdim // Inherits Rd in 4-0 384249259Sdim} 385249259Sdim 386249259Sdim// Format for floating-point compare instructions. 387249259Sdimclass A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2, 388249259Sdim dag outs, dag ins, string asmstr, 389249259Sdim list<dag> patterns, InstrItinClass itin> 390249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 391249259Sdim bits<5> Rn; 392249259Sdim bits<5> Rm; 393249259Sdim 394249259Sdim let Inst{31} = m; 395249259Sdim let Inst{30} = 0b0; 396249259Sdim let Inst{29} = s; 397249259Sdim let Inst{28-24} = 0b11110; 398249259Sdim let Inst{23-22} = type; 399249259Sdim let Inst{21} = 0b1; 400249259Sdim let Inst{20-16} = Rm; 401249259Sdim let Inst{15-14} = op; 402249259Sdim let Inst{13-10} = 0b1000; 403249259Sdim let Inst{9-5} = Rn; 404249259Sdim let Inst{4-0} = opcode2; 405249259Sdim} 406249259Sdim 407249259Sdim// Format for floating-point conditional compare instructions. 408249259Sdimclass A64I_fpccmp<bit m, bit s, bits<2> type, bit op, 409249259Sdim dag outs, dag ins, string asmstr, 410249259Sdim list<dag> patterns, InstrItinClass itin> 411249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 412249259Sdim bits<5> Rn; 413249259Sdim bits<5> Rm; 414249259Sdim bits<4> NZCVImm; 415249259Sdim bits<4> Cond; 416249259Sdim 417249259Sdim let Inst{31} = m; 418249259Sdim let Inst{30} = 0b0; 419249259Sdim let Inst{29} = s; 420249259Sdim let Inst{28-24} = 0b11110; 421249259Sdim let Inst{23-22} = type; 422249259Sdim let Inst{21} = 0b1; 423249259Sdim let Inst{20-16} = Rm; 424249259Sdim let Inst{15-12} = Cond; 425249259Sdim let Inst{11-10} = 0b01; 426249259Sdim let Inst{9-5} = Rn; 427249259Sdim let Inst{4} = op; 428249259Sdim let Inst{3-0} = NZCVImm; 429249259Sdim} 430249259Sdim 431249259Sdim// Format for floating-point conditional select instructions. 432249259Sdimclass A64I_fpcondsel<bit m, bit s, bits<2> type, 433249259Sdim dag outs, dag ins, string asmstr, 434249259Sdim list<dag> patterns, InstrItinClass itin> 435249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 436249259Sdim bits<4> Cond; 437249259Sdim 438249259Sdim let Inst{31} = m; 439249259Sdim let Inst{30} = 0b0; 440249259Sdim let Inst{29} = s; 441249259Sdim let Inst{28-24} = 0b11110; 442249259Sdim let Inst{23-22} = type; 443249259Sdim let Inst{21} = 0b1; 444249259Sdim // Inherit Rm in 20-16 445249259Sdim let Inst{15-12} = Cond; 446249259Sdim let Inst{11-10} = 0b11; 447249259Sdim // Inherit Rn in 9-5 448249259Sdim // Inherit Rd in 4-0 449249259Sdim} 450249259Sdim 451249259Sdim 452249259Sdim// Format for floating-point data-processing (1 source) instructions. 453249259Sdimclass A64I_fpdp1<bit m, bit s, bits<2> type, bits<6> opcode, 454249259Sdim dag outs, dag ins, string asmstr, 455249259Sdim list<dag> patterns, InstrItinClass itin> 456249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 457249259Sdim let Inst{31} = m; 458249259Sdim let Inst{30} = 0b0; 459249259Sdim let Inst{29} = s; 460249259Sdim let Inst{28-24} = 0b11110; 461249259Sdim let Inst{23-22} = type; 462249259Sdim let Inst{21} = 0b1; 463249259Sdim let Inst{20-15} = opcode; 464249259Sdim let Inst{14-10} = 0b10000; 465249259Sdim // Inherit Rn in 9-5 466249259Sdim // Inherit Rd in 4-0 467249259Sdim} 468249259Sdim 469249259Sdim// Format for floating-point data-processing (2 sources) instructions. 470249259Sdimclass A64I_fpdp2<bit m, bit s, bits<2> type, bits<4> opcode, 471249259Sdim dag outs, dag ins, string asmstr, 472249259Sdim list<dag> patterns, InstrItinClass itin> 473249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 474249259Sdim let Inst{31} = m; 475249259Sdim let Inst{30} = 0b0; 476249259Sdim let Inst{29} = s; 477249259Sdim let Inst{28-24} = 0b11110; 478249259Sdim let Inst{23-22} = type; 479249259Sdim let Inst{21} = 0b1; 480249259Sdim // Inherit Rm in 20-16 481249259Sdim let Inst{15-12} = opcode; 482249259Sdim let Inst{11-10} = 0b10; 483249259Sdim // Inherit Rn in 9-5 484249259Sdim // Inherit Rd in 4-0 485249259Sdim} 486249259Sdim 487249259Sdim// Format for floating-point data-processing (3 sources) instructions. 488249259Sdimclass A64I_fpdp3<bit m, bit s, bits<2> type, bit o1, bit o0, 489249259Sdim dag outs, dag ins, string asmstr, 490249259Sdim list<dag> patterns, InstrItinClass itin> 491249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 492249259Sdim bits<5> Ra; 493249259Sdim 494249259Sdim let Inst{31} = m; 495249259Sdim let Inst{30} = 0b0; 496249259Sdim let Inst{29} = s; 497249259Sdim let Inst{28-24} = 0b11111; 498249259Sdim let Inst{23-22} = type; 499249259Sdim let Inst{21} = o1; 500249259Sdim // Inherit Rm in 20-16 501249259Sdim let Inst{15} = o0; 502249259Sdim let Inst{14-10} = Ra; 503249259Sdim // Inherit Rn in 9-5 504249259Sdim // Inherit Rd in 4-0 505249259Sdim} 506249259Sdim 507249259Sdim// Format for floating-point <-> fixed-point conversion instructions. 508249259Sdimclass A64I_fpfixed<bit sf, bit s, bits<2> type, bits<2> mode, bits<3> opcode, 509249259Sdim dag outs, dag ins, string asmstr, 510249259Sdim list<dag> patterns, InstrItinClass itin> 511249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 512249259Sdim bits<6> Scale; 513249259Sdim 514249259Sdim let Inst{31} = sf; 515249259Sdim let Inst{30} = 0b0; 516249259Sdim let Inst{29} = s; 517249259Sdim let Inst{28-24} = 0b11110; 518249259Sdim let Inst{23-22} = type; 519249259Sdim let Inst{21} = 0b0; 520249259Sdim let Inst{20-19} = mode; 521249259Sdim let Inst{18-16} = opcode; 522249259Sdim let Inst{15-10} = Scale; 523249259Sdim // Inherit Rn in 9-5 524249259Sdim // Inherit Rd in 4-0 525249259Sdim} 526249259Sdim 527249259Sdim// Format for floating-point <-> integer conversion instructions. 528249259Sdimclass A64I_fpint<bit sf, bit s, bits<2> type, bits<2> rmode, bits<3> opcode, 529249259Sdim dag outs, dag ins, string asmstr, 530249259Sdim list<dag> patterns, InstrItinClass itin> 531249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 532249259Sdim let Inst{31} = sf; 533249259Sdim let Inst{30} = 0b0; 534249259Sdim let Inst{29} = s; 535249259Sdim let Inst{28-24} = 0b11110; 536249259Sdim let Inst{23-22} = type; 537249259Sdim let Inst{21} = 0b1; 538249259Sdim let Inst{20-19} = rmode; 539249259Sdim let Inst{18-16} = opcode; 540249259Sdim let Inst{15-10} = 0b000000; 541249259Sdim // Inherit Rn in 9-5 542249259Sdim // Inherit Rd in 4-0 543249259Sdim} 544249259Sdim 545249259Sdim 546249259Sdim// Format for floating-point immediate instructions. 547249259Sdimclass A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5, 548249259Sdim dag outs, dag ins, string asmstr, 549249259Sdim list<dag> patterns, InstrItinClass itin> 550249259Sdim : A64InstRd<outs, ins, asmstr, patterns, itin> { 551249259Sdim bits<8> Imm8; 552249259Sdim 553249259Sdim let Inst{31} = m; 554249259Sdim let Inst{30} = 0b0; 555249259Sdim let Inst{29} = s; 556249259Sdim let Inst{28-24} = 0b11110; 557249259Sdim let Inst{23-22} = type; 558249259Sdim let Inst{21} = 0b1; 559249259Sdim let Inst{20-13} = Imm8; 560249259Sdim let Inst{12-10} = 0b100; 561249259Sdim let Inst{9-5} = imm5; 562249259Sdim // Inherit Rd in 4-0 563249259Sdim} 564249259Sdim 565249259Sdim// Format for load-register (literal) instructions. 566249259Sdimclass A64I_LDRlit<bits<2> opc, bit v, 567249259Sdim dag outs, dag ins, string asmstr, 568249259Sdim list<dag> patterns, InstrItinClass itin> 569249259Sdim : A64InstRt<outs, ins, asmstr, patterns, itin> { 570249259Sdim bits<19> Imm19; 571249259Sdim 572249259Sdim let Inst{31-30} = opc; 573249259Sdim let Inst{29-27} = 0b011; 574249259Sdim let Inst{26} = v; 575249259Sdim let Inst{25-24} = 0b00; 576249259Sdim let Inst{23-5} = Imm19; 577249259Sdim // Inherit Rt in 4-0 578249259Sdim} 579249259Sdim 580249259Sdim// Format for load-store exclusive instructions. 581249259Sdimclass A64I_LDSTex_tn<bits<2> size, bit o2, bit L, bit o1, bit o0, 582249259Sdim dag outs, dag ins, string asmstr, 583249259Sdim list <dag> patterns, InstrItinClass itin> 584249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 585249259Sdim let Inst{31-30} = size; 586249259Sdim let Inst{29-24} = 0b001000; 587249259Sdim let Inst{23} = o2; 588249259Sdim let Inst{22} = L; 589249259Sdim let Inst{21} = o1; 590249259Sdim let Inst{15} = o0; 591249259Sdim} 592249259Sdim 593249259Sdimclass A64I_LDSTex_tt2n<bits<2> size, bit o2, bit L, bit o1, bit o0, 594249259Sdim dag outs, dag ins, string asmstr, 595249259Sdim list <dag> patterns, InstrItinClass itin>: 596249259Sdim A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{ 597249259Sdim bits<5> Rt2; 598249259Sdim let Inst{14-10} = Rt2; 599249259Sdim} 600249259Sdim 601249259Sdimclass A64I_LDSTex_stn<bits<2> size, bit o2, bit L, bit o1, bit o0, 602249259Sdim dag outs, dag ins, string asmstr, 603249259Sdim list <dag> patterns, InstrItinClass itin>: 604249259Sdim A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{ 605249259Sdim bits<5> Rs; 606249259Sdim let Inst{20-16} = Rs; 607249259Sdim} 608249259Sdim 609249259Sdimclass A64I_LDSTex_stt2n<bits<2> size, bit o2, bit L, bit o1, bit o0, 610249259Sdim dag outs, dag ins, string asmstr, 611249259Sdim list <dag> patterns, InstrItinClass itin>: 612249259Sdim A64I_LDSTex_stn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{ 613249259Sdim bits<5> Rt2; 614249259Sdim let Inst{14-10} = Rt2; 615249259Sdim} 616249259Sdim 617249259Sdim// Format for load-store register (immediate post-indexed) instructions 618249259Sdimclass A64I_LSpostind<bits<2> size, bit v, bits<2> opc, 619249259Sdim dag outs, dag ins, string asmstr, 620249259Sdim list<dag> patterns, InstrItinClass itin> 621249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 622249259Sdim bits<9> SImm9; 623249259Sdim 624249259Sdim let Inst{31-30} = size; 625249259Sdim let Inst{29-27} = 0b111; 626249259Sdim let Inst{26} = v; 627249259Sdim let Inst{25-24} = 0b00; 628249259Sdim let Inst{23-22} = opc; 629249259Sdim let Inst{21} = 0b0; 630249259Sdim let Inst{20-12} = SImm9; 631249259Sdim let Inst{11-10} = 0b01; 632249259Sdim // Inherit Rn in 9-5 633249259Sdim // Inherit Rt in 4-0 634249259Sdim} 635249259Sdim 636249259Sdim// Format for load-store register (immediate pre-indexed) instructions 637249259Sdimclass A64I_LSpreind<bits<2> size, bit v, bits<2> opc, 638249259Sdim dag outs, dag ins, string asmstr, 639249259Sdim list<dag> patterns, InstrItinClass itin> 640249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 641249259Sdim bits<9> SImm9; 642249259Sdim 643249259Sdim 644249259Sdim let Inst{31-30} = size; 645249259Sdim let Inst{29-27} = 0b111; 646249259Sdim let Inst{26} = v; 647249259Sdim let Inst{25-24} = 0b00; 648249259Sdim let Inst{23-22} = opc; 649249259Sdim let Inst{21} = 0b0; 650249259Sdim let Inst{20-12} = SImm9; 651249259Sdim let Inst{11-10} = 0b11; 652249259Sdim // Inherit Rn in 9-5 653249259Sdim // Inherit Rt in 4-0 654249259Sdim} 655249259Sdim 656249259Sdim// Format for load-store register (unprivileged) instructions 657249259Sdimclass A64I_LSunpriv<bits<2> size, bit v, bits<2> opc, 658249259Sdim dag outs, dag ins, string asmstr, 659249259Sdim list<dag> patterns, InstrItinClass itin> 660249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 661249259Sdim bits<9> SImm9; 662249259Sdim 663249259Sdim 664249259Sdim let Inst{31-30} = size; 665249259Sdim let Inst{29-27} = 0b111; 666249259Sdim let Inst{26} = v; 667249259Sdim let Inst{25-24} = 0b00; 668249259Sdim let Inst{23-22} = opc; 669249259Sdim let Inst{21} = 0b0; 670249259Sdim let Inst{20-12} = SImm9; 671249259Sdim let Inst{11-10} = 0b10; 672249259Sdim // Inherit Rn in 9-5 673249259Sdim // Inherit Rt in 4-0 674249259Sdim} 675249259Sdim 676249259Sdim// Format for load-store (unscaled immediate) instructions. 677249259Sdimclass A64I_LSunalimm<bits<2> size, bit v, bits<2> opc, 678249259Sdim dag outs, dag ins, string asmstr, 679249259Sdim list<dag> patterns, InstrItinClass itin> 680249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 681249259Sdim bits<9> SImm9; 682249259Sdim 683249259Sdim let Inst{31-30} = size; 684249259Sdim let Inst{29-27} = 0b111; 685249259Sdim let Inst{26} = v; 686249259Sdim let Inst{25-24} = 0b00; 687249259Sdim let Inst{23-22} = opc; 688249259Sdim let Inst{21} = 0b0; 689249259Sdim let Inst{20-12} = SImm9; 690249259Sdim let Inst{11-10} = 0b00; 691249259Sdim // Inherit Rn in 9-5 692249259Sdim // Inherit Rt in 4-0 693249259Sdim} 694249259Sdim 695249259Sdim 696249259Sdim// Format for load-store (unsigned immediate) instructions. 697249259Sdimclass A64I_LSunsigimm<bits<2> size, bit v, bits<2> opc, 698249259Sdim dag outs, dag ins, string asmstr, 699249259Sdim list<dag> patterns, InstrItinClass itin> 700249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 701249259Sdim bits<12> UImm12; 702249259Sdim 703249259Sdim let Inst{31-30} = size; 704249259Sdim let Inst{29-27} = 0b111; 705249259Sdim let Inst{26} = v; 706249259Sdim let Inst{25-24} = 0b01; 707249259Sdim let Inst{23-22} = opc; 708249259Sdim let Inst{21-10} = UImm12; 709249259Sdim} 710249259Sdim 711249259Sdim// Format for load-store register (register offset) instructions. 712249259Sdimclass A64I_LSregoff<bits<2> size, bit v, bits<2> opc, bit optionlo, 713249259Sdim dag outs, dag ins, string asmstr, 714249259Sdim list<dag> patterns, InstrItinClass itin> 715249259Sdim : A64InstRtn<outs, ins, asmstr, patterns, itin> { 716249259Sdim bits<5> Rm; 717249259Sdim 718249259Sdim // Complex operand selection needed for these instructions, so they 719249259Sdim // need an "addr" field for encoding/decoding to be generated. 720249259Sdim bits<3> Ext; 721249259Sdim // OptionHi = Ext{2-1} 722249259Sdim // S = Ext{0} 723249259Sdim 724249259Sdim let Inst{31-30} = size; 725249259Sdim let Inst{29-27} = 0b111; 726249259Sdim let Inst{26} = v; 727249259Sdim let Inst{25-24} = 0b00; 728249259Sdim let Inst{23-22} = opc; 729249259Sdim let Inst{21} = 0b1; 730249259Sdim let Inst{20-16} = Rm; 731249259Sdim let Inst{15-14} = Ext{2-1}; 732249259Sdim let Inst{13} = optionlo; 733249259Sdim let Inst{12} = Ext{0}; 734249259Sdim let Inst{11-10} = 0b10; 735249259Sdim // Inherits Rn in 9-5 736249259Sdim // Inherits Rt in 4-0 737249259Sdim 738249259Sdim let AddedComplexity = 50; 739249259Sdim} 740249259Sdim 741249259Sdim// Format for Load-store register pair (offset) instructions 742249259Sdimclass A64I_LSPoffset<bits<2> opc, bit v, bit l, 743249259Sdim dag outs, dag ins, string asmstr, 744249259Sdim list<dag> patterns, InstrItinClass itin> 745249259Sdim : A64InstRtt2n<outs, ins, asmstr, patterns, itin> { 746249259Sdim bits<7> SImm7; 747249259Sdim 748249259Sdim let Inst{31-30} = opc; 749249259Sdim let Inst{29-27} = 0b101; 750249259Sdim let Inst{26} = v; 751249259Sdim let Inst{25-23} = 0b010; 752249259Sdim let Inst{22} = l; 753249259Sdim let Inst{21-15} = SImm7; 754249259Sdim // Inherit Rt2 in 14-10 755249259Sdim // Inherit Rn in 9-5 756249259Sdim // Inherit Rt in 4-0 757249259Sdim} 758249259Sdim 759249259Sdim// Format for Load-store register pair (post-indexed) instructions 760249259Sdimclass A64I_LSPpostind<bits<2> opc, bit v, bit l, 761249259Sdim dag outs, dag ins, string asmstr, 762249259Sdim list<dag> patterns, InstrItinClass itin> 763249259Sdim : A64InstRtt2n<outs, ins, asmstr, patterns, itin> { 764249259Sdim bits<7> SImm7; 765249259Sdim 766249259Sdim let Inst{31-30} = opc; 767249259Sdim let Inst{29-27} = 0b101; 768249259Sdim let Inst{26} = v; 769249259Sdim let Inst{25-23} = 0b001; 770249259Sdim let Inst{22} = l; 771249259Sdim let Inst{21-15} = SImm7; 772249259Sdim // Inherit Rt2 in 14-10 773249259Sdim // Inherit Rn in 9-5 774249259Sdim // Inherit Rt in 4-0 775249259Sdim} 776249259Sdim 777249259Sdim// Format for Load-store register pair (pre-indexed) instructions 778249259Sdimclass A64I_LSPpreind<bits<2> opc, bit v, bit l, 779249259Sdim dag outs, dag ins, string asmstr, 780249259Sdim list<dag> patterns, InstrItinClass itin> 781249259Sdim : A64InstRtt2n<outs, ins, asmstr, patterns, itin> { 782249259Sdim bits<7> SImm7; 783249259Sdim 784249259Sdim let Inst{31-30} = opc; 785249259Sdim let Inst{29-27} = 0b101; 786249259Sdim let Inst{26} = v; 787249259Sdim let Inst{25-23} = 0b011; 788249259Sdim let Inst{22} = l; 789249259Sdim let Inst{21-15} = SImm7; 790249259Sdim // Inherit Rt2 in 14-10 791249259Sdim // Inherit Rn in 9-5 792249259Sdim // Inherit Rt in 4-0 793249259Sdim} 794249259Sdim 795249259Sdim// Format for Load-store non-temporal register pair (offset) instructions 796249259Sdimclass A64I_LSPnontemp<bits<2> opc, bit v, bit l, 797249259Sdim dag outs, dag ins, string asmstr, 798249259Sdim list<dag> patterns, InstrItinClass itin> 799249259Sdim : A64InstRtt2n<outs, ins, asmstr, patterns, itin> { 800249259Sdim bits<7> SImm7; 801249259Sdim 802249259Sdim let Inst{31-30} = opc; 803249259Sdim let Inst{29-27} = 0b101; 804249259Sdim let Inst{26} = v; 805249259Sdim let Inst{25-23} = 0b000; 806249259Sdim let Inst{22} = l; 807249259Sdim let Inst{21-15} = SImm7; 808249259Sdim // Inherit Rt2 in 14-10 809249259Sdim // Inherit Rn in 9-5 810249259Sdim // Inherit Rt in 4-0 811249259Sdim} 812249259Sdim 813249259Sdim// Format for Logical (immediate) instructions 814249259Sdimclass A64I_logicalimm<bit sf, bits<2> opc, 815249259Sdim dag outs, dag ins, string asmstr, 816249259Sdim list<dag> patterns, InstrItinClass itin> 817249259Sdim : A64InstRdn<outs, ins, asmstr, patterns, itin> { 818249259Sdim bit N; 819249259Sdim bits<6> ImmR; 820249259Sdim bits<6> ImmS; 821249259Sdim 822249259Sdim // N, ImmR and ImmS have no separate existence in any assembly syntax (or for 823249259Sdim // selection), so we'll combine them into a single field here. 824249259Sdim bits<13> Imm; 825249259Sdim // N = Imm{12}; 826249259Sdim // ImmR = Imm{11-6}; 827249259Sdim // ImmS = Imm{5-0}; 828249259Sdim 829249259Sdim let Inst{31} = sf; 830249259Sdim let Inst{30-29} = opc; 831249259Sdim let Inst{28-23} = 0b100100; 832249259Sdim let Inst{22} = Imm{12}; 833249259Sdim let Inst{21-16} = Imm{11-6}; 834249259Sdim let Inst{15-10} = Imm{5-0}; 835249259Sdim // Rn inherited in 9-5 836249259Sdim // Rd inherited in 4-0 837249259Sdim} 838249259Sdim 839249259Sdim// Format for Logical (shifted register) instructions 840249259Sdimclass A64I_logicalshift<bit sf, bits<2> opc, bits<2> shift, bit N, 841249259Sdim dag outs, dag ins, string asmstr, 842249259Sdim list<dag> patterns, InstrItinClass itin> 843249259Sdim : A64InstRdnm<outs, ins, asmstr, patterns, itin> { 844249259Sdim bits<6> Imm6; 845249259Sdim 846249259Sdim let Inst{31} = sf; 847249259Sdim let Inst{30-29} = opc; 848249259Sdim let Inst{28-24} = 0b01010; 849249259Sdim let Inst{23-22} = shift; 850249259Sdim let Inst{21} = N; 851249259Sdim // Rm inherited 852249259Sdim let Inst{15-10} = Imm6; 853249259Sdim // Rn inherited 854249259Sdim // Rd inherited 855249259Sdim} 856249259Sdim 857249259Sdim// Format for Move wide (immediate) 858249259Sdimclass A64I_movw<bit sf, bits<2> opc, 859249259Sdim dag outs, dag ins, string asmstr, 860249259Sdim list<dag> patterns, InstrItinClass itin> 861249259Sdim : A64InstRd<outs, ins, asmstr, patterns, itin> { 862249259Sdim bits<16> UImm16; 863249259Sdim bits<2> Shift; // Called "hw" officially 864249259Sdim 865249259Sdim let Inst{31} = sf; 866249259Sdim let Inst{30-29} = opc; 867249259Sdim let Inst{28-23} = 0b100101; 868249259Sdim let Inst{22-21} = Shift; 869249259Sdim let Inst{20-5} = UImm16; 870249259Sdim // Inherits Rd in 4-0 871249259Sdim} 872249259Sdim 873249259Sdim// Format for PC-relative addressing instructions, ADR and ADRP. 874249259Sdimclass A64I_PCADR<bit op, 875249259Sdim dag outs, dag ins, string asmstr, 876249259Sdim list<dag> patterns, InstrItinClass itin> 877249259Sdim : A64InstRd<outs, ins, asmstr, patterns, itin> { 878249259Sdim bits<21> Label; 879249259Sdim 880249259Sdim let Inst{31} = op; 881249259Sdim let Inst{30-29} = Label{1-0}; 882249259Sdim let Inst{28-24} = 0b10000; 883249259Sdim let Inst{23-5} = Label{20-2}; 884249259Sdim} 885249259Sdim 886249259Sdim// Format for system instructions 887249259Sdimclass A64I_system<bit l, 888249259Sdim dag outs, dag ins, string asmstr, 889249259Sdim list<dag> patterns, InstrItinClass itin> 890249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 891249259Sdim bits<2> Op0; 892249259Sdim bits<3> Op1; 893249259Sdim bits<4> CRn; 894249259Sdim bits<4> CRm; 895249259Sdim bits<3> Op2; 896249259Sdim bits<5> Rt; 897249259Sdim 898249259Sdim let Inst{31-22} = 0b1101010100; 899249259Sdim let Inst{21} = l; 900249259Sdim let Inst{20-19} = Op0; 901249259Sdim let Inst{18-16} = Op1; 902249259Sdim let Inst{15-12} = CRn; 903249259Sdim let Inst{11-8} = CRm; 904249259Sdim let Inst{7-5} = Op2; 905249259Sdim let Inst{4-0} = Rt; 906249259Sdim 907249259Sdim // These instructions can do horrible things. 908249259Sdim let hasSideEffects = 1; 909249259Sdim} 910249259Sdim 911249259Sdim// Format for unconditional branch (immediate) instructions 912249259Sdimclass A64I_Bimm<bit op, 913249259Sdim dag outs, dag ins, string asmstr, 914249259Sdim list<dag> patterns, InstrItinClass itin> 915249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 916249259Sdim // Doubly special in not even sharing register fields with other 917249259Sdim // instructions, so we create our own Rn here. 918249259Sdim bits<26> Label; 919249259Sdim 920249259Sdim let Inst{31} = op; 921249259Sdim let Inst{30-26} = 0b00101; 922249259Sdim let Inst{25-0} = Label; 923249259Sdim} 924249259Sdim 925249259Sdim// Format for Test & branch (immediate) instructions 926249259Sdimclass A64I_TBimm<bit op, 927249259Sdim dag outs, dag ins, string asmstr, 928249259Sdim list<dag> patterns, InstrItinClass itin> 929249259Sdim : A64InstRt<outs, ins, asmstr, patterns, itin> { 930249259Sdim // Doubly special in not even sharing register fields with other 931249259Sdim // instructions, so we create our own Rn here. 932249259Sdim bits<6> Imm; 933249259Sdim bits<14> Label; 934249259Sdim 935249259Sdim let Inst{31} = Imm{5}; 936249259Sdim let Inst{30-25} = 0b011011; 937249259Sdim let Inst{24} = op; 938249259Sdim let Inst{23-19} = Imm{4-0}; 939249259Sdim let Inst{18-5} = Label; 940249259Sdim // Inherit Rt in 4-0 941249259Sdim} 942249259Sdim 943249259Sdim// Format for Unconditional branch (register) instructions, including 944249259Sdim// RET. Shares no fields with instructions further up the hierarchy 945249259Sdim// so top-level. 946249259Sdimclass A64I_Breg<bits<4> opc, bits<5> op2, bits<6> op3, bits<5> op4, 947249259Sdim dag outs, dag ins, string asmstr, 948249259Sdim list<dag> patterns, InstrItinClass itin> 949249259Sdim : A64Inst<outs, ins, asmstr, patterns, itin> { 950249259Sdim // Doubly special in not even sharing register fields with other 951249259Sdim // instructions, so we create our own Rn here. 952249259Sdim bits<5> Rn; 953249259Sdim 954249259Sdim let Inst{31-25} = 0b1101011; 955249259Sdim let Inst{24-21} = opc; 956249259Sdim let Inst{20-16} = op2; 957249259Sdim let Inst{15-10} = op3; 958249259Sdim let Inst{9-5} = Rn; 959249259Sdim let Inst{4-0} = op4; 960249259Sdim} 961249259Sdim 962