MCSubtargetInfo.cpp revision 263508 
1//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCSubtargetInfo.h"
11#include "llvm/ADT/StringRef.h"
12#include "llvm/ADT/Triple.h"
13#include "llvm/MC/MCInstrItineraries.h"
14#include "llvm/MC/SubtargetFeature.h"
15#include "llvm/Support/raw_ostream.h"
16#include <algorithm>
17
18using namespace llvm;
19
20MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
21
22/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
23/// with feature string). Recompute feature bits and scheduling model.
24void
25MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
26  SubtargetFeatures Features(FS);
27  FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
28                                        ProcFeatures, NumFeatures);
29
30  InitCPUSchedModel(CPU);
31}
32
33void
34MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
35  if (!CPU.empty())
36    CPUSchedModel = getSchedModelForCPU(CPU);
37  else
38    CPUSchedModel = &MCSchedModel::DefaultSchedModel;
39}
40
41void
42MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
43                                     const SubtargetFeatureKV *PF,
44                                     const SubtargetFeatureKV *PD,
45                                     const SubtargetInfoKV *ProcSched,
46                                     const MCWriteProcResEntry *WPR,
47                                     const MCWriteLatencyEntry *WL,
48                                     const MCReadAdvanceEntry *RA,
49                                     const InstrStage *IS,
50                                     const unsigned *OC,
51                                     const unsigned *FP,
52                                     unsigned NF, unsigned NP) {
53  TargetTriple = TT;
54  ProcFeatures = PF;
55  ProcDesc = PD;
56  ProcSchedModels = ProcSched;
57  WriteProcResTable = WPR;
58  WriteLatencyTable = WL;
59  ReadAdvanceTable = RA;
60
61  Stages = IS;
62  OperandCycles = OC;
63  ForwardingPaths = FP;
64  NumFeatures = NF;
65  NumProcs = NP;
66
67  InitMCProcessorInfo(CPU, FS);
68}
69
70/// ToggleFeature - Toggle a feature and returns the re-computed feature
71/// bits. This version does not change the implied bits.
72uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
73  FeatureBits ^= FB;
74  return FeatureBits;
75}
76
77/// ToggleFeature - Toggle a feature and returns the re-computed feature
78/// bits. This version will also change all implied bits.
79uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
80  SubtargetFeatures Features;
81  FeatureBits = Features.ToggleFeature(FeatureBits, FS,
82                                       ProcFeatures, NumFeatures);
83  return FeatureBits;
84}
85
86
87const MCSchedModel *
88MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
89  assert(ProcSchedModels && "Processor machine model not available!");
90
91#ifndef NDEBUG
92  for (size_t i = 1; i < NumProcs; i++) {
93    assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
94           "Processor machine model table is not sorted");
95  }
96#endif
97
98  // Find entry
99  const SubtargetInfoKV *Found =
100    std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
101  if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
102    errs() << "'" << CPU
103           << "' is not a recognized processor for this target"
104           << " (ignoring processor)\n";
105    return &MCSchedModel::DefaultSchedModel;
106  }
107  assert(Found->Value && "Missing processor SchedModel value");
108  return (const MCSchedModel *)Found->Value;
109}
110
111InstrItineraryData
112MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
113  const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
114  return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
115}
116
117/// Initialize an InstrItineraryData instance.
118void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
119  InstrItins =
120    InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
121}
122