SelectionDAGISel.cpp revision 263508
1//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAGISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "llvm/CodeGen/SelectionDAGISel.h" 16#include "ScheduleDAGSDNodes.h" 17#include "SelectionDAGBuilder.h" 18#include "llvm/ADT/PostOrderIterator.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/CFG.h" 23#include "llvm/Analysis/TargetTransformInfo.h" 24#include "llvm/CodeGen/FastISel.h" 25#include "llvm/CodeGen/FunctionLoweringInfo.h" 26#include "llvm/CodeGen/GCMetadata.h" 27#include "llvm/CodeGen/GCStrategy.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineModuleInfo.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 34#include "llvm/CodeGen/SchedulerRegistry.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/DebugInfo.h" 37#include "llvm/IR/Constants.h" 38#include "llvm/IR/Function.h" 39#include "llvm/IR/InlineAsm.h" 40#include "llvm/IR/Instructions.h" 41#include "llvm/IR/IntrinsicInst.h" 42#include "llvm/IR/Intrinsics.h" 43#include "llvm/IR/LLVMContext.h" 44#include "llvm/IR/Module.h" 45#include "llvm/Support/Compiler.h" 46#include "llvm/Support/Debug.h" 47#include "llvm/Support/ErrorHandling.h" 48#include "llvm/Support/Timer.h" 49#include "llvm/Support/raw_ostream.h" 50#include "llvm/Target/TargetInstrInfo.h" 51#include "llvm/Target/TargetIntrinsicInfo.h" 52#include "llvm/Target/TargetLibraryInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "llvm/Target/TargetOptions.h" 56#include "llvm/Target/TargetRegisterInfo.h" 57#include "llvm/Target/TargetSubtargetInfo.h" 58#include "llvm/Transforms/Utils/BasicBlockUtils.h" 59#include <algorithm> 60using namespace llvm; 61 62STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 63STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 64STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 65STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 66STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 67STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 68STATISTIC(NumFastIselFailLowerArguments, 69 "Number of entry blocks where fast isel failed to lower arguments"); 70 71#ifndef NDEBUG 72static cl::opt<bool> 73EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 74 cl::desc("Enable extra verbose messages in the \"fast\" " 75 "instruction selector")); 76 77 // Terminators 78STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 79STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 80STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 81STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 82STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 83STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 84STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 85 86 // Standard binary operators... 87STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 88STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 89STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 90STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 91STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 92STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 93STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 94STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 95STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 96STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 97STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 98STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 99 100 // Logical operators... 101STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 102STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 103STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 104 105 // Memory instructions... 106STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 107STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 108STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 109STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 110STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 111STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 112STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 113 114 // Convert instructions... 115STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 116STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 117STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 118STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 119STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 120STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 121STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 122STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 123STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 124STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 125STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 126STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 127 128 // Other instructions... 129STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 130STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 131STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 132STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 133STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 134STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 135STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 136STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 137STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 138STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 139STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 140STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 141STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 142STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 143STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 144#endif 145 146static cl::opt<bool> 147EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 148 cl::desc("Enable verbose messages in the \"fast\" " 149 "instruction selector")); 150static cl::opt<bool> 151EnableFastISelAbort("fast-isel-abort", cl::Hidden, 152 cl::desc("Enable abort calls when \"fast\" instruction selection " 153 "fails to lower an instruction")); 154static cl::opt<bool> 155EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden, 156 cl::desc("Enable abort calls when \"fast\" instruction selection " 157 "fails to lower a formal argument")); 158 159static cl::opt<bool> 160UseMBPI("use-mbpi", 161 cl::desc("use Machine Branch Probability Info"), 162 cl::init(true), cl::Hidden); 163 164#ifndef NDEBUG 165static cl::opt<bool> 166ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 167 cl::desc("Pop up a window to show dags before the first " 168 "dag combine pass")); 169static cl::opt<bool> 170ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 171 cl::desc("Pop up a window to show dags before legalize types")); 172static cl::opt<bool> 173ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 174 cl::desc("Pop up a window to show dags before legalize")); 175static cl::opt<bool> 176ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 177 cl::desc("Pop up a window to show dags before the second " 178 "dag combine pass")); 179static cl::opt<bool> 180ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 181 cl::desc("Pop up a window to show dags before the post legalize types" 182 " dag combine pass")); 183static cl::opt<bool> 184ViewISelDAGs("view-isel-dags", cl::Hidden, 185 cl::desc("Pop up a window to show isel dags as they are selected")); 186static cl::opt<bool> 187ViewSchedDAGs("view-sched-dags", cl::Hidden, 188 cl::desc("Pop up a window to show sched dags as they are processed")); 189static cl::opt<bool> 190ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 191 cl::desc("Pop up a window to show SUnit dags after they are processed")); 192#else 193static const bool ViewDAGCombine1 = false, 194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 195 ViewDAGCombine2 = false, 196 ViewDAGCombineLT = false, 197 ViewISelDAGs = false, ViewSchedDAGs = false, 198 ViewSUnitDAGs = false; 199#endif 200 201//===---------------------------------------------------------------------===// 202/// 203/// RegisterScheduler class - Track the registration of instruction schedulers. 204/// 205//===---------------------------------------------------------------------===// 206MachinePassRegistry RegisterScheduler::Registry; 207 208//===---------------------------------------------------------------------===// 209/// 210/// ISHeuristic command line option for instruction schedulers. 211/// 212//===---------------------------------------------------------------------===// 213static cl::opt<RegisterScheduler::FunctionPassCtor, false, 214 RegisterPassParser<RegisterScheduler> > 215ISHeuristic("pre-RA-sched", 216 cl::init(&createDefaultScheduler), 217 cl::desc("Instruction schedulers available (before register" 218 " allocation):")); 219 220static RegisterScheduler 221defaultListDAGScheduler("default", "Best scheduler for the target", 222 createDefaultScheduler); 223 224namespace llvm { 225 //===--------------------------------------------------------------------===// 226 /// \brief This class is used by SelectionDAGISel to temporarily override 227 /// the optimization level on a per-function basis. 228 class OptLevelChanger { 229 SelectionDAGISel &IS; 230 CodeGenOpt::Level SavedOptLevel; 231 bool SavedFastISel; 232 233 public: 234 OptLevelChanger(SelectionDAGISel &ISel, 235 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 236 SavedOptLevel = IS.OptLevel; 237 if (NewOptLevel == SavedOptLevel) 238 return; 239 IS.OptLevel = NewOptLevel; 240 IS.TM.setOptLevel(NewOptLevel); 241 SavedFastISel = IS.TM.Options.EnableFastISel; 242 if (NewOptLevel == CodeGenOpt::None) 243 IS.TM.setFastISel(true); 244 DEBUG(dbgs() << "\nChanging optimization level for Function " 245 << IS.MF->getFunction()->getName() << "\n"); 246 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 247 << " ; After: -O" << NewOptLevel << "\n"); 248 } 249 250 ~OptLevelChanger() { 251 if (IS.OptLevel == SavedOptLevel) 252 return; 253 DEBUG(dbgs() << "\nRestoring optimization level for Function " 254 << IS.MF->getFunction()->getName() << "\n"); 255 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 256 << " ; After: -O" << SavedOptLevel << "\n"); 257 IS.OptLevel = SavedOptLevel; 258 IS.TM.setOptLevel(SavedOptLevel); 259 IS.TM.setFastISel(SavedFastISel); 260 } 261 }; 262 263 //===--------------------------------------------------------------------===// 264 /// createDefaultScheduler - This creates an instruction scheduler appropriate 265 /// for the target. 266 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 267 CodeGenOpt::Level OptLevel) { 268 const TargetLowering *TLI = IS->getTargetLowering(); 269 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>(); 270 271 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() || 272 TLI->getSchedulingPreference() == Sched::Source) 273 return createSourceListDAGScheduler(IS, OptLevel); 274 if (TLI->getSchedulingPreference() == Sched::RegPressure) 275 return createBURRListDAGScheduler(IS, OptLevel); 276 if (TLI->getSchedulingPreference() == Sched::Hybrid) 277 return createHybridListDAGScheduler(IS, OptLevel); 278 if (TLI->getSchedulingPreference() == Sched::VLIW) 279 return createVLIWDAGScheduler(IS, OptLevel); 280 assert(TLI->getSchedulingPreference() == Sched::ILP && 281 "Unknown sched type!"); 282 return createILPListDAGScheduler(IS, OptLevel); 283 } 284} 285 286// EmitInstrWithCustomInserter - This method should be implemented by targets 287// that mark instructions with the 'usesCustomInserter' flag. These 288// instructions are special in various ways, which require special support to 289// insert. The specified MachineInstr is created but not inserted into any 290// basic blocks, and this method is called to expand it into a sequence of 291// instructions, potentially also creating new basic blocks and control flow. 292// When new basic blocks are inserted and the edges from MBB to its successors 293// are modified, the method should insert pairs of <OldSucc, NewSucc> into the 294// DenseMap. 295MachineBasicBlock * 296TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 297 MachineBasicBlock *MBB) const { 298#ifndef NDEBUG 299 dbgs() << "If a target marks an instruction with " 300 "'usesCustomInserter', it must implement " 301 "TargetLowering::EmitInstrWithCustomInserter!"; 302#endif 303 llvm_unreachable(0); 304} 305 306void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 307 SDNode *Node) const { 308 assert(!MI->hasPostISelHook() && 309 "If a target marks an instruction with 'hasPostISelHook', " 310 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 311} 312 313//===----------------------------------------------------------------------===// 314// SelectionDAGISel code 315//===----------------------------------------------------------------------===// 316 317SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 318 CodeGenOpt::Level OL) : 319 MachineFunctionPass(ID), TM(tm), 320 FuncInfo(new FunctionLoweringInfo(TM)), 321 CurDAG(new SelectionDAG(tm, OL)), 322 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 323 GFI(), 324 OptLevel(OL), 325 DAGSize(0) { 326 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 327 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 328 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 329 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 330 } 331 332SelectionDAGISel::~SelectionDAGISel() { 333 delete SDB; 334 delete CurDAG; 335 delete FuncInfo; 336} 337 338void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 339 AU.addRequired<AliasAnalysis>(); 340 AU.addPreserved<AliasAnalysis>(); 341 AU.addRequired<GCModuleInfo>(); 342 AU.addPreserved<GCModuleInfo>(); 343 AU.addRequired<TargetLibraryInfo>(); 344 if (UseMBPI && OptLevel != CodeGenOpt::None) 345 AU.addRequired<BranchProbabilityInfo>(); 346 MachineFunctionPass::getAnalysisUsage(AU); 347} 348 349/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 350/// may trap on it. In this case we have to split the edge so that the path 351/// through the predecessor block that doesn't go to the phi block doesn't 352/// execute the possibly trapping instruction. 353/// 354/// This is required for correctness, so it must be done at -O0. 355/// 356static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 357 // Loop for blocks with phi nodes. 358 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 359 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 360 if (PN == 0) continue; 361 362 ReprocessBlock: 363 // For each block with a PHI node, check to see if any of the input values 364 // are potentially trapping constant expressions. Constant expressions are 365 // the only potentially trapping value that can occur as the argument to a 366 // PHI. 367 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 368 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 369 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 370 if (CE == 0 || !CE->canTrap()) continue; 371 372 // The only case we have to worry about is when the edge is critical. 373 // Since this block has a PHI Node, we assume it has multiple input 374 // edges: check to see if the pred has multiple successors. 375 BasicBlock *Pred = PN->getIncomingBlock(i); 376 if (Pred->getTerminator()->getNumSuccessors() == 1) 377 continue; 378 379 // Okay, we have to split this edge. 380 SplitCriticalEdge(Pred->getTerminator(), 381 GetSuccessorNumber(Pred, BB), SDISel, true); 382 goto ReprocessBlock; 383 } 384 } 385} 386 387bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 388 // Do some sanity-checking on the command-line options. 389 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 390 "-fast-isel-verbose requires -fast-isel"); 391 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 392 "-fast-isel-abort requires -fast-isel"); 393 394 const Function &Fn = *mf.getFunction(); 395 const TargetInstrInfo &TII = *TM.getInstrInfo(); 396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 397 const TargetLowering *TLI = TM.getTargetLowering(); 398 399 MF = &mf; 400 RegInfo = &MF->getRegInfo(); 401 AA = &getAnalysis<AliasAnalysis>(); 402 LibInfo = &getAnalysis<TargetLibraryInfo>(); 403 TTI = getAnalysisIfAvailable<TargetTransformInfo>(); 404 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 405 406 TargetSubtargetInfo &ST = 407 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>()); 408 ST.resetSubtargetFeatures(MF); 409 TM.resetTargetOptions(MF); 410 411 // Reset OptLevel to None for optnone functions. 412 CodeGenOpt::Level NewOptLevel = OptLevel; 413 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 414 NewOptLevel = CodeGenOpt::None; 415 OptLevelChanger OLC(*this, NewOptLevel); 416 417 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 418 419 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 420 421 CurDAG->init(*MF, TTI, TLI); 422 FuncInfo->set(Fn, *MF); 423 424 if (UseMBPI && OptLevel != CodeGenOpt::None) 425 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 426 else 427 FuncInfo->BPI = 0; 428 429 SDB->init(GFI, *AA, LibInfo); 430 431 MF->setHasMSInlineAsm(false); 432 SelectAllBasicBlocks(Fn); 433 434 // If the first basic block in the function has live ins that need to be 435 // copied into vregs, emit the copies into the top of the block before 436 // emitting the code for the block. 437 MachineBasicBlock *EntryMBB = MF->begin(); 438 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 439 440 DenseMap<unsigned, unsigned> LiveInMap; 441 if (!FuncInfo->ArgDbgValues.empty()) 442 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 443 E = RegInfo->livein_end(); LI != E; ++LI) 444 if (LI->second) 445 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 446 447 // Insert DBG_VALUE instructions for function arguments to the entry block. 448 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 449 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 450 bool hasFI = MI->getOperand(0).isFI(); 451 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 452 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 453 EntryMBB->insert(EntryMBB->begin(), MI); 454 else { 455 MachineInstr *Def = RegInfo->getVRegDef(Reg); 456 if (Def) { 457 MachineBasicBlock::iterator InsertPos = Def; 458 // FIXME: VR def may not be in entry block. 459 Def->getParent()->insert(llvm::next(InsertPos), MI); 460 } else 461 DEBUG(dbgs() << "Dropping debug info for dead vreg" 462 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 463 } 464 465 // If Reg is live-in then update debug info to track its copy in a vreg. 466 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 467 if (LDI != LiveInMap.end()) { 468 assert(!hasFI && "There's no handling of frame pointer updating here yet " 469 "- add if needed"); 470 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 471 MachineBasicBlock::iterator InsertPos = Def; 472 const MDNode *Variable = 473 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 474 bool IsIndirect = MI->isIndirectDebugValue(); 475 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 476 // Def is never a terminator here, so it is ok to increment InsertPos. 477 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 478 TII.get(TargetOpcode::DBG_VALUE), 479 IsIndirect, 480 LDI->second, Offset, Variable); 481 482 // If this vreg is directly copied into an exported register then 483 // that COPY instructions also need DBG_VALUE, if it is the only 484 // user of LDI->second. 485 MachineInstr *CopyUseMI = NULL; 486 for (MachineRegisterInfo::use_iterator 487 UI = RegInfo->use_begin(LDI->second); 488 MachineInstr *UseMI = UI.skipInstruction();) { 489 if (UseMI->isDebugValue()) continue; 490 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 491 CopyUseMI = UseMI; continue; 492 } 493 // Otherwise this is another use or second copy use. 494 CopyUseMI = NULL; break; 495 } 496 if (CopyUseMI) { 497 MachineInstr *NewMI = 498 BuildMI(*MF, CopyUseMI->getDebugLoc(), 499 TII.get(TargetOpcode::DBG_VALUE), 500 IsIndirect, 501 CopyUseMI->getOperand(0).getReg(), 502 Offset, Variable); 503 MachineBasicBlock::iterator Pos = CopyUseMI; 504 EntryMBB->insertAfter(Pos, NewMI); 505 } 506 } 507 } 508 509 // Determine if there are any calls in this machine function. 510 MachineFrameInfo *MFI = MF->getFrameInfo(); 511 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; 512 ++I) { 513 514 if (MFI->hasCalls() && MF->hasMSInlineAsm()) 515 break; 516 517 const MachineBasicBlock *MBB = I; 518 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); 519 II != IE; ++II) { 520 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 521 if ((MCID.isCall() && !MCID.isReturn()) || 522 II->isStackAligningInlineAsm()) { 523 MFI->setHasCalls(true); 524 } 525 if (II->isMSInlineAsm()) { 526 MF->setHasMSInlineAsm(true); 527 } 528 } 529 } 530 531 // Determine if there is a call to setjmp in the machine function. 532 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 533 534 // Replace forward-declared registers with the registers containing 535 // the desired value. 536 MachineRegisterInfo &MRI = MF->getRegInfo(); 537 for (DenseMap<unsigned, unsigned>::iterator 538 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 539 I != E; ++I) { 540 unsigned From = I->first; 541 unsigned To = I->second; 542 // If To is also scheduled to be replaced, find what its ultimate 543 // replacement is. 544 for (;;) { 545 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 546 if (J == E) break; 547 To = J->second; 548 } 549 // Make sure the new register has a sufficiently constrained register class. 550 if (TargetRegisterInfo::isVirtualRegister(From) && 551 TargetRegisterInfo::isVirtualRegister(To)) 552 MRI.constrainRegClass(To, MRI.getRegClass(From)); 553 // Replace it. 554 MRI.replaceRegWith(From, To); 555 } 556 557 // Freeze the set of reserved registers now that MachineFrameInfo has been 558 // set up. All the information required by getReservedRegs() should be 559 // available now. 560 MRI.freezeReservedRegs(*MF); 561 562 // Release function-specific state. SDB and CurDAG are already cleared 563 // at this point. 564 FuncInfo->clear(); 565 566 return true; 567} 568 569void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 570 BasicBlock::const_iterator End, 571 bool &HadTailCall) { 572 // Lower all of the non-terminator instructions. If a call is emitted 573 // as a tail call, cease emitting nodes for this block. Terminators 574 // are handled below. 575 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 576 SDB->visit(*I); 577 578 // Make sure the root of the DAG is up-to-date. 579 CurDAG->setRoot(SDB->getControlRoot()); 580 HadTailCall = SDB->HasTailCall; 581 SDB->clear(); 582 583 // Final step, emit the lowered DAG as machine code. 584 CodeGenAndEmitDAG(); 585} 586 587void SelectionDAGISel::ComputeLiveOutVRegInfo() { 588 SmallPtrSet<SDNode*, 128> VisitedNodes; 589 SmallVector<SDNode*, 128> Worklist; 590 591 Worklist.push_back(CurDAG->getRoot().getNode()); 592 593 APInt KnownZero; 594 APInt KnownOne; 595 596 do { 597 SDNode *N = Worklist.pop_back_val(); 598 599 // If we've already seen this node, ignore it. 600 if (!VisitedNodes.insert(N)) 601 continue; 602 603 // Otherwise, add all chain operands to the worklist. 604 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 605 if (N->getOperand(i).getValueType() == MVT::Other) 606 Worklist.push_back(N->getOperand(i).getNode()); 607 608 // If this is a CopyToReg with a vreg dest, process it. 609 if (N->getOpcode() != ISD::CopyToReg) 610 continue; 611 612 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 613 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 614 continue; 615 616 // Ignore non-scalar or non-integer values. 617 SDValue Src = N->getOperand(2); 618 EVT SrcVT = Src.getValueType(); 619 if (!SrcVT.isInteger() || SrcVT.isVector()) 620 continue; 621 622 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 623 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 624 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 625 } while (!Worklist.empty()); 626} 627 628void SelectionDAGISel::CodeGenAndEmitDAG() { 629 std::string GroupName; 630 if (TimePassesIsEnabled) 631 GroupName = "Instruction Selection and Scheduling"; 632 std::string BlockName; 633 int BlockNumber = -1; 634 (void)BlockNumber; 635#ifdef NDEBUG 636 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 637 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 638 ViewSUnitDAGs) 639#endif 640 { 641 BlockNumber = FuncInfo->MBB->getNumber(); 642 BlockName = MF->getName().str() + ":" + 643 FuncInfo->MBB->getBasicBlock()->getName().str(); 644 } 645 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 646 << " '" << BlockName << "'\n"; CurDAG->dump()); 647 648 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 649 650 // Run the DAG combiner in pre-legalize mode. 651 { 652 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 653 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 654 } 655 656 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 657 << " '" << BlockName << "'\n"; CurDAG->dump()); 658 659 // Second step, hack on the DAG until it only uses operations and types that 660 // the target supports. 661 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 662 BlockName); 663 664 bool Changed; 665 { 666 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 667 Changed = CurDAG->LegalizeTypes(); 668 } 669 670 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 671 << " '" << BlockName << "'\n"; CurDAG->dump()); 672 673 CurDAG->NewNodesMustHaveLegalTypes = true; 674 675 if (Changed) { 676 if (ViewDAGCombineLT) 677 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 678 679 // Run the DAG combiner in post-type-legalize mode. 680 { 681 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 682 TimePassesIsEnabled); 683 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 684 } 685 686 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 687 << " '" << BlockName << "'\n"; CurDAG->dump()); 688 689 } 690 691 { 692 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 693 Changed = CurDAG->LegalizeVectors(); 694 } 695 696 if (Changed) { 697 { 698 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 699 CurDAG->LegalizeTypes(); 700 } 701 702 if (ViewDAGCombineLT) 703 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 704 705 // Run the DAG combiner in post-type-legalize mode. 706 { 707 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 708 TimePassesIsEnabled); 709 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 710 } 711 712 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 713 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 714 } 715 716 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 717 718 { 719 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 720 CurDAG->Legalize(); 721 } 722 723 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 724 << " '" << BlockName << "'\n"; CurDAG->dump()); 725 726 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 727 728 // Run the DAG combiner in post-legalize mode. 729 { 730 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 731 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 732 } 733 734 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 735 << " '" << BlockName << "'\n"; CurDAG->dump()); 736 737 if (OptLevel != CodeGenOpt::None) 738 ComputeLiveOutVRegInfo(); 739 740 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 741 742 // Third, instruction select all of the operations to machine code, adding the 743 // code to the MachineBasicBlock. 744 { 745 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 746 DoInstructionSelection(); 747 } 748 749 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 750 << " '" << BlockName << "'\n"; CurDAG->dump()); 751 752 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 753 754 // Schedule machine code. 755 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 756 { 757 NamedRegionTimer T("Instruction Scheduling", GroupName, 758 TimePassesIsEnabled); 759 Scheduler->Run(CurDAG, FuncInfo->MBB); 760 } 761 762 if (ViewSUnitDAGs) Scheduler->viewGraph(); 763 764 // Emit machine code to BB. This can change 'BB' to the last block being 765 // inserted into. 766 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 767 { 768 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 769 770 // FuncInfo->InsertPt is passed by reference and set to the end of the 771 // scheduled instructions. 772 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 773 } 774 775 // If the block was split, make sure we update any references that are used to 776 // update PHI nodes later on. 777 if (FirstMBB != LastMBB) 778 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 779 780 // Free the scheduler state. 781 { 782 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 783 TimePassesIsEnabled); 784 delete Scheduler; 785 } 786 787 // Free the SelectionDAG state, now that we're finished with it. 788 CurDAG->clear(); 789} 790 791namespace { 792/// ISelUpdater - helper class to handle updates of the instruction selection 793/// graph. 794class ISelUpdater : public SelectionDAG::DAGUpdateListener { 795 SelectionDAG::allnodes_iterator &ISelPosition; 796public: 797 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 798 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 799 800 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 801 /// deleted is the current ISelPosition node, update ISelPosition. 802 /// 803 virtual void NodeDeleted(SDNode *N, SDNode *E) { 804 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 805 ++ISelPosition; 806 } 807}; 808} // end anonymous namespace 809 810void SelectionDAGISel::DoInstructionSelection() { 811 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 812 << FuncInfo->MBB->getNumber() 813 << " '" << FuncInfo->MBB->getName() << "'\n"); 814 815 PreprocessISelDAG(); 816 817 // Select target instructions for the DAG. 818 { 819 // Number all nodes with a topological order and set DAGSize. 820 DAGSize = CurDAG->AssignTopologicalOrder(); 821 822 // Create a dummy node (which is not added to allnodes), that adds 823 // a reference to the root node, preventing it from being deleted, 824 // and tracking any changes of the root. 825 HandleSDNode Dummy(CurDAG->getRoot()); 826 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 827 ++ISelPosition; 828 829 // Make sure that ISelPosition gets properly updated when nodes are deleted 830 // in calls made from this function. 831 ISelUpdater ISU(*CurDAG, ISelPosition); 832 833 // The AllNodes list is now topological-sorted. Visit the 834 // nodes by starting at the end of the list (the root of the 835 // graph) and preceding back toward the beginning (the entry 836 // node). 837 while (ISelPosition != CurDAG->allnodes_begin()) { 838 SDNode *Node = --ISelPosition; 839 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 840 // but there are currently some corner cases that it misses. Also, this 841 // makes it theoretically possible to disable the DAGCombiner. 842 if (Node->use_empty()) 843 continue; 844 845 SDNode *ResNode = Select(Node); 846 847 // FIXME: This is pretty gross. 'Select' should be changed to not return 848 // anything at all and this code should be nuked with a tactical strike. 849 850 // If node should not be replaced, continue with the next one. 851 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 852 continue; 853 // Replace node. 854 if (ResNode) { 855 ReplaceUses(Node, ResNode); 856 } 857 858 // If after the replacement this node is not used any more, 859 // remove this dead node. 860 if (Node->use_empty()) // Don't delete EntryToken, etc. 861 CurDAG->RemoveDeadNode(Node); 862 } 863 864 CurDAG->setRoot(Dummy.getValue()); 865 } 866 867 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 868 869 PostprocessISelDAG(); 870} 871 872/// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 873/// do other setup for EH landing-pad blocks. 874void SelectionDAGISel::PrepareEHLandingPad() { 875 MachineBasicBlock *MBB = FuncInfo->MBB; 876 877 // Add a label to mark the beginning of the landing pad. Deletion of the 878 // landing pad can thus be detected via the MachineModuleInfo. 879 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 880 881 // Assign the call site to the landing pad's begin label. 882 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 883 884 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 885 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 886 .addSym(Label); 887 888 // Mark exception register as live in. 889 const TargetLowering *TLI = getTargetLowering(); 890 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 891 if (unsigned Reg = TLI->getExceptionPointerRegister()) 892 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 893 894 // Mark exception selector register as live in. 895 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 896 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 897} 898 899/// isFoldedOrDeadInstruction - Return true if the specified instruction is 900/// side-effect free and is either dead or folded into a generated instruction. 901/// Return false if it needs to be emitted. 902static bool isFoldedOrDeadInstruction(const Instruction *I, 903 FunctionLoweringInfo *FuncInfo) { 904 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 905 !isa<TerminatorInst>(I) && // Terminators aren't folded. 906 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 907 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 908 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 909} 910 911#ifndef NDEBUG 912// Collect per Instruction statistics for fast-isel misses. Only those 913// instructions that cause the bail are accounted for. It does not account for 914// instructions higher in the block. Thus, summing the per instructions stats 915// will not add up to what is reported by NumFastIselFailures. 916static void collectFailStats(const Instruction *I) { 917 switch (I->getOpcode()) { 918 default: assert (0 && "<Invalid operator> "); 919 920 // Terminators 921 case Instruction::Ret: NumFastIselFailRet++; return; 922 case Instruction::Br: NumFastIselFailBr++; return; 923 case Instruction::Switch: NumFastIselFailSwitch++; return; 924 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 925 case Instruction::Invoke: NumFastIselFailInvoke++; return; 926 case Instruction::Resume: NumFastIselFailResume++; return; 927 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 928 929 // Standard binary operators... 930 case Instruction::Add: NumFastIselFailAdd++; return; 931 case Instruction::FAdd: NumFastIselFailFAdd++; return; 932 case Instruction::Sub: NumFastIselFailSub++; return; 933 case Instruction::FSub: NumFastIselFailFSub++; return; 934 case Instruction::Mul: NumFastIselFailMul++; return; 935 case Instruction::FMul: NumFastIselFailFMul++; return; 936 case Instruction::UDiv: NumFastIselFailUDiv++; return; 937 case Instruction::SDiv: NumFastIselFailSDiv++; return; 938 case Instruction::FDiv: NumFastIselFailFDiv++; return; 939 case Instruction::URem: NumFastIselFailURem++; return; 940 case Instruction::SRem: NumFastIselFailSRem++; return; 941 case Instruction::FRem: NumFastIselFailFRem++; return; 942 943 // Logical operators... 944 case Instruction::And: NumFastIselFailAnd++; return; 945 case Instruction::Or: NumFastIselFailOr++; return; 946 case Instruction::Xor: NumFastIselFailXor++; return; 947 948 // Memory instructions... 949 case Instruction::Alloca: NumFastIselFailAlloca++; return; 950 case Instruction::Load: NumFastIselFailLoad++; return; 951 case Instruction::Store: NumFastIselFailStore++; return; 952 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 953 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 954 case Instruction::Fence: NumFastIselFailFence++; return; 955 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 956 957 // Convert instructions... 958 case Instruction::Trunc: NumFastIselFailTrunc++; return; 959 case Instruction::ZExt: NumFastIselFailZExt++; return; 960 case Instruction::SExt: NumFastIselFailSExt++; return; 961 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 962 case Instruction::FPExt: NumFastIselFailFPExt++; return; 963 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 964 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 965 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 966 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 967 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 968 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 969 case Instruction::BitCast: NumFastIselFailBitCast++; return; 970 971 // Other instructions... 972 case Instruction::ICmp: NumFastIselFailICmp++; return; 973 case Instruction::FCmp: NumFastIselFailFCmp++; return; 974 case Instruction::PHI: NumFastIselFailPHI++; return; 975 case Instruction::Select: NumFastIselFailSelect++; return; 976 case Instruction::Call: NumFastIselFailCall++; return; 977 case Instruction::Shl: NumFastIselFailShl++; return; 978 case Instruction::LShr: NumFastIselFailLShr++; return; 979 case Instruction::AShr: NumFastIselFailAShr++; return; 980 case Instruction::VAArg: NumFastIselFailVAArg++; return; 981 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 982 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 983 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 984 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 985 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 986 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 987 } 988} 989#endif 990 991void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 992 // Initialize the Fast-ISel state, if needed. 993 FastISel *FastIS = 0; 994 if (TM.Options.EnableFastISel) 995 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo); 996 997 // Iterate over all basic blocks in the function. 998 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 999 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1000 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1001 const BasicBlock *LLVMBB = *I; 1002 1003 if (OptLevel != CodeGenOpt::None) { 1004 bool AllPredsVisited = true; 1005 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1006 PI != PE; ++PI) { 1007 if (!FuncInfo->VisitedBBs.count(*PI)) { 1008 AllPredsVisited = false; 1009 break; 1010 } 1011 } 1012 1013 if (AllPredsVisited) { 1014 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1015 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1016 FuncInfo->ComputePHILiveOutRegInfo(PN); 1017 } else { 1018 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1019 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1020 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1021 } 1022 1023 FuncInfo->VisitedBBs.insert(LLVMBB); 1024 } 1025 1026 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1027 BasicBlock::const_iterator const End = LLVMBB->end(); 1028 BasicBlock::const_iterator BI = End; 1029 1030 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1031 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1032 1033 // Setup an EH landing-pad block. 1034 FuncInfo->ExceptionPointerVirtReg = 0; 1035 FuncInfo->ExceptionSelectorVirtReg = 0; 1036 if (FuncInfo->MBB->isLandingPad()) 1037 PrepareEHLandingPad(); 1038 1039 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1040 if (FastIS) { 1041 FastIS->startNewBlock(); 1042 1043 // Emit code for any incoming arguments. This must happen before 1044 // beginning FastISel on the entry block. 1045 if (LLVMBB == &Fn.getEntryBlock()) { 1046 ++NumEntryBlocks; 1047 1048 // Lower any arguments needed in this block if this is the entry block. 1049 if (!FastIS->LowerArguments()) { 1050 // Fast isel failed to lower these arguments 1051 ++NumFastIselFailLowerArguments; 1052 if (EnableFastISelAbortArgs) 1053 llvm_unreachable("FastISel didn't lower all arguments"); 1054 1055 // Use SelectionDAG argument lowering 1056 LowerArguments(Fn); 1057 CurDAG->setRoot(SDB->getControlRoot()); 1058 SDB->clear(); 1059 CodeGenAndEmitDAG(); 1060 } 1061 1062 // If we inserted any instructions at the beginning, make a note of 1063 // where they are, so we can be sure to emit subsequent instructions 1064 // after them. 1065 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1066 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1067 else 1068 FastIS->setLastLocalValue(0); 1069 } 1070 1071 unsigned NumFastIselRemaining = std::distance(Begin, End); 1072 // Do FastISel on as many instructions as possible. 1073 for (; BI != Begin; --BI) { 1074 const Instruction *Inst = llvm::prior(BI); 1075 1076 // If we no longer require this instruction, skip it. 1077 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1078 --NumFastIselRemaining; 1079 continue; 1080 } 1081 1082 // Bottom-up: reset the insert pos at the top, after any local-value 1083 // instructions. 1084 FastIS->recomputeInsertPt(); 1085 1086 // Try to select the instruction with FastISel. 1087 if (FastIS->SelectInstruction(Inst)) { 1088 --NumFastIselRemaining; 1089 ++NumFastIselSuccess; 1090 // If fast isel succeeded, skip over all the folded instructions, and 1091 // then see if there is a load right before the selected instructions. 1092 // Try to fold the load if so. 1093 const Instruction *BeforeInst = Inst; 1094 while (BeforeInst != Begin) { 1095 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1096 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1097 break; 1098 } 1099 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1100 BeforeInst->hasOneUse() && 1101 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1102 // If we succeeded, don't re-select the load. 1103 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1104 --NumFastIselRemaining; 1105 ++NumFastIselSuccess; 1106 } 1107 continue; 1108 } 1109 1110#ifndef NDEBUG 1111 if (EnableFastISelVerbose2) 1112 collectFailStats(Inst); 1113#endif 1114 1115 // Then handle certain instructions as single-LLVM-Instruction blocks. 1116 if (isa<CallInst>(Inst)) { 1117 1118 if (EnableFastISelVerbose || EnableFastISelAbort) { 1119 dbgs() << "FastISel missed call: "; 1120 Inst->dump(); 1121 } 1122 1123 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1124 unsigned &R = FuncInfo->ValueMap[Inst]; 1125 if (!R) 1126 R = FuncInfo->CreateRegs(Inst->getType()); 1127 } 1128 1129 bool HadTailCall = false; 1130 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1131 SelectBasicBlock(Inst, BI, HadTailCall); 1132 1133 // If the call was emitted as a tail call, we're done with the block. 1134 // We also need to delete any previously emitted instructions. 1135 if (HadTailCall) { 1136 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1137 --BI; 1138 break; 1139 } 1140 1141 // Recompute NumFastIselRemaining as Selection DAG instruction 1142 // selection may have handled the call, input args, etc. 1143 unsigned RemainingNow = std::distance(Begin, BI); 1144 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1145 NumFastIselRemaining = RemainingNow; 1146 continue; 1147 } 1148 1149 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1150 // Don't abort, and use a different message for terminator misses. 1151 NumFastIselFailures += NumFastIselRemaining; 1152 if (EnableFastISelVerbose || EnableFastISelAbort) { 1153 dbgs() << "FastISel missed terminator: "; 1154 Inst->dump(); 1155 } 1156 } else { 1157 NumFastIselFailures += NumFastIselRemaining; 1158 if (EnableFastISelVerbose || EnableFastISelAbort) { 1159 dbgs() << "FastISel miss: "; 1160 Inst->dump(); 1161 } 1162 if (EnableFastISelAbort) 1163 // The "fast" selector couldn't handle something and bailed. 1164 // For the purpose of debugging, just abort. 1165 llvm_unreachable("FastISel didn't select the entire block"); 1166 } 1167 break; 1168 } 1169 1170 FastIS->recomputeInsertPt(); 1171 } else { 1172 // Lower any arguments needed in this block if this is the entry block. 1173 if (LLVMBB == &Fn.getEntryBlock()) { 1174 ++NumEntryBlocks; 1175 LowerArguments(Fn); 1176 } 1177 } 1178 1179 if (Begin != BI) 1180 ++NumDAGBlocks; 1181 else 1182 ++NumFastIselBlocks; 1183 1184 if (Begin != BI) { 1185 // Run SelectionDAG instruction selection on the remainder of the block 1186 // not handled by FastISel. If FastISel is not run, this is the entire 1187 // block. 1188 bool HadTailCall; 1189 SelectBasicBlock(Begin, BI, HadTailCall); 1190 } 1191 1192 FinishBasicBlock(); 1193 FuncInfo->PHINodesToUpdate.clear(); 1194 } 1195 1196 delete FastIS; 1197 SDB->clearDanglingDebugInfo(); 1198 SDB->SPDescriptor.resetPerFunctionState(); 1199} 1200 1201/// Given that the input MI is before a partial terminator sequence TSeq, return 1202/// true if M + TSeq also a partial terminator sequence. 1203/// 1204/// A Terminator sequence is a sequence of MachineInstrs which at this point in 1205/// lowering copy vregs into physical registers, which are then passed into 1206/// terminator instructors so we can satisfy ABI constraints. A partial 1207/// terminator sequence is an improper subset of a terminator sequence (i.e. it 1208/// may be the whole terminator sequence). 1209static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1210 // If we do not have a copy or an implicit def, we return true if and only if 1211 // MI is a debug value. 1212 if (!MI->isCopy() && !MI->isImplicitDef()) 1213 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1214 // physical registers if there is debug info associated with the terminator 1215 // of our mbb. We want to include said debug info in our terminator 1216 // sequence, so we return true in that case. 1217 return MI->isDebugValue(); 1218 1219 // We have left the terminator sequence if we are not doing one of the 1220 // following: 1221 // 1222 // 1. Copying a vreg into a physical register. 1223 // 2. Copying a vreg into a vreg. 1224 // 3. Defining a register via an implicit def. 1225 1226 // OPI should always be a register definition... 1227 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1228 if (!OPI->isReg() || !OPI->isDef()) 1229 return false; 1230 1231 // Defining any register via an implicit def is always ok. 1232 if (MI->isImplicitDef()) 1233 return true; 1234 1235 // Grab the copy source... 1236 MachineInstr::const_mop_iterator OPI2 = OPI; 1237 ++OPI2; 1238 assert(OPI2 != MI->operands_end() 1239 && "Should have a copy implying we should have 2 arguments."); 1240 1241 // Make sure that the copy dest is not a vreg when the copy source is a 1242 // physical register. 1243 if (!OPI2->isReg() || 1244 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1245 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1246 return false; 1247 1248 return true; 1249} 1250 1251/// Find the split point at which to splice the end of BB into its success stack 1252/// protector check machine basic block. 1253/// 1254/// On many platforms, due to ABI constraints, terminators, even before register 1255/// allocation, use physical registers. This creates an issue for us since 1256/// physical registers at this point can not travel across basic 1257/// blocks. Luckily, selectiondag always moves physical registers into vregs 1258/// when they enter functions and moves them through a sequence of copies back 1259/// into the physical registers right before the terminator creating a 1260/// ``Terminator Sequence''. This function is searching for the beginning of the 1261/// terminator sequence so that we can ensure that we splice off not just the 1262/// terminator, but additionally the copies that move the vregs into the 1263/// physical registers. 1264static MachineBasicBlock::iterator 1265FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1266 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1267 // 1268 if (SplitPoint == BB->begin()) 1269 return SplitPoint; 1270 1271 MachineBasicBlock::iterator Start = BB->begin(); 1272 MachineBasicBlock::iterator Previous = SplitPoint; 1273 --Previous; 1274 1275 while (MIIsInTerminatorSequence(Previous)) { 1276 SplitPoint = Previous; 1277 if (Previous == Start) 1278 break; 1279 --Previous; 1280 } 1281 1282 return SplitPoint; 1283} 1284 1285void 1286SelectionDAGISel::FinishBasicBlock() { 1287 1288 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1289 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1290 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1291 dbgs() << "Node " << i << " : (" 1292 << FuncInfo->PHINodesToUpdate[i].first 1293 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1294 1295 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1296 SDB->JTCases.empty() && 1297 SDB->BitTestCases.empty(); 1298 1299 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1300 // PHI nodes in successors. 1301 if (MustUpdatePHINodes) { 1302 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1303 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1304 assert(PHI->isPHI() && 1305 "This is not a machine PHI node that we are updating!"); 1306 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1307 continue; 1308 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1309 } 1310 } 1311 1312 // Handle stack protector. 1313 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1314 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1315 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1316 1317 // Find the split point to split the parent mbb. At the same time copy all 1318 // physical registers used in the tail of parent mbb into virtual registers 1319 // before the split point and back into physical registers after the split 1320 // point. This prevents us needing to deal with Live-ins and many other 1321 // register allocation issues caused by us splitting the parent mbb. The 1322 // register allocator will clean up said virtual copies later on. 1323 MachineBasicBlock::iterator SplitPoint = 1324 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1325 1326 // Splice the terminator of ParentMBB into SuccessMBB. 1327 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1328 SplitPoint, 1329 ParentMBB->end()); 1330 1331 // Add compare/jump on neq/jump to the parent BB. 1332 FuncInfo->MBB = ParentMBB; 1333 FuncInfo->InsertPt = ParentMBB->end(); 1334 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1335 CurDAG->setRoot(SDB->getRoot()); 1336 SDB->clear(); 1337 CodeGenAndEmitDAG(); 1338 1339 // CodeGen Failure MBB if we have not codegened it yet. 1340 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1341 if (!FailureMBB->size()) { 1342 FuncInfo->MBB = FailureMBB; 1343 FuncInfo->InsertPt = FailureMBB->end(); 1344 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1345 CurDAG->setRoot(SDB->getRoot()); 1346 SDB->clear(); 1347 CodeGenAndEmitDAG(); 1348 } 1349 1350 // Clear the Per-BB State. 1351 SDB->SPDescriptor.resetPerBBState(); 1352 } 1353 1354 // If we updated PHI Nodes, return early. 1355 if (MustUpdatePHINodes) 1356 return; 1357 1358 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1359 // Lower header first, if it wasn't already lowered 1360 if (!SDB->BitTestCases[i].Emitted) { 1361 // Set the current basic block to the mbb we wish to insert the code into 1362 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1363 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1364 // Emit the code 1365 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1366 CurDAG->setRoot(SDB->getRoot()); 1367 SDB->clear(); 1368 CodeGenAndEmitDAG(); 1369 } 1370 1371 uint32_t UnhandledWeight = 0; 1372 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1373 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1374 1375 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1376 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1377 // Set the current basic block to the mbb we wish to insert the code into 1378 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1379 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1380 // Emit the code 1381 if (j+1 != ej) 1382 SDB->visitBitTestCase(SDB->BitTestCases[i], 1383 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1384 UnhandledWeight, 1385 SDB->BitTestCases[i].Reg, 1386 SDB->BitTestCases[i].Cases[j], 1387 FuncInfo->MBB); 1388 else 1389 SDB->visitBitTestCase(SDB->BitTestCases[i], 1390 SDB->BitTestCases[i].Default, 1391 UnhandledWeight, 1392 SDB->BitTestCases[i].Reg, 1393 SDB->BitTestCases[i].Cases[j], 1394 FuncInfo->MBB); 1395 1396 1397 CurDAG->setRoot(SDB->getRoot()); 1398 SDB->clear(); 1399 CodeGenAndEmitDAG(); 1400 } 1401 1402 // Update PHI Nodes 1403 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1404 pi != pe; ++pi) { 1405 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1406 MachineBasicBlock *PHIBB = PHI->getParent(); 1407 assert(PHI->isPHI() && 1408 "This is not a machine PHI node that we are updating!"); 1409 // This is "default" BB. We have two jumps to it. From "header" BB and 1410 // from last "case" BB. 1411 if (PHIBB == SDB->BitTestCases[i].Default) 1412 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1413 .addMBB(SDB->BitTestCases[i].Parent) 1414 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1415 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1416 // One of "cases" BB. 1417 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1418 j != ej; ++j) { 1419 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1420 if (cBB->isSuccessor(PHIBB)) 1421 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1422 } 1423 } 1424 } 1425 SDB->BitTestCases.clear(); 1426 1427 // If the JumpTable record is filled in, then we need to emit a jump table. 1428 // Updating the PHI nodes is tricky in this case, since we need to determine 1429 // whether the PHI is a successor of the range check MBB or the jump table MBB 1430 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1431 // Lower header first, if it wasn't already lowered 1432 if (!SDB->JTCases[i].first.Emitted) { 1433 // Set the current basic block to the mbb we wish to insert the code into 1434 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1435 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1436 // Emit the code 1437 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1438 FuncInfo->MBB); 1439 CurDAG->setRoot(SDB->getRoot()); 1440 SDB->clear(); 1441 CodeGenAndEmitDAG(); 1442 } 1443 1444 // Set the current basic block to the mbb we wish to insert the code into 1445 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1446 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1447 // Emit the code 1448 SDB->visitJumpTable(SDB->JTCases[i].second); 1449 CurDAG->setRoot(SDB->getRoot()); 1450 SDB->clear(); 1451 CodeGenAndEmitDAG(); 1452 1453 // Update PHI Nodes 1454 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1455 pi != pe; ++pi) { 1456 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1457 MachineBasicBlock *PHIBB = PHI->getParent(); 1458 assert(PHI->isPHI() && 1459 "This is not a machine PHI node that we are updating!"); 1460 // "default" BB. We can go there only from header BB. 1461 if (PHIBB == SDB->JTCases[i].second.Default) 1462 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1463 .addMBB(SDB->JTCases[i].first.HeaderBB); 1464 // JT BB. Just iterate over successors here 1465 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1466 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1467 } 1468 } 1469 SDB->JTCases.clear(); 1470 1471 // If the switch block involved a branch to one of the actual successors, we 1472 // need to update PHI nodes in that block. 1473 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1474 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1475 assert(PHI->isPHI() && 1476 "This is not a machine PHI node that we are updating!"); 1477 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1478 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1479 } 1480 1481 // If we generated any switch lowering information, build and codegen any 1482 // additional DAGs necessary. 1483 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1484 // Set the current basic block to the mbb we wish to insert the code into 1485 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1486 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1487 1488 // Determine the unique successors. 1489 SmallVector<MachineBasicBlock *, 2> Succs; 1490 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1491 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1492 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1493 1494 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1495 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1496 CurDAG->setRoot(SDB->getRoot()); 1497 SDB->clear(); 1498 CodeGenAndEmitDAG(); 1499 1500 // Remember the last block, now that any splitting is done, for use in 1501 // populating PHI nodes in successors. 1502 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1503 1504 // Handle any PHI nodes in successors of this chunk, as if we were coming 1505 // from the original BB before switch expansion. Note that PHI nodes can 1506 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1507 // handle them the right number of times. 1508 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1509 FuncInfo->MBB = Succs[i]; 1510 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1511 // FuncInfo->MBB may have been removed from the CFG if a branch was 1512 // constant folded. 1513 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1514 for (MachineBasicBlock::iterator 1515 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1516 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1517 MachineInstrBuilder PHI(*MF, MBBI); 1518 // This value for this PHI node is recorded in PHINodesToUpdate. 1519 for (unsigned pn = 0; ; ++pn) { 1520 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1521 "Didn't find PHI entry!"); 1522 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1523 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1524 break; 1525 } 1526 } 1527 } 1528 } 1529 } 1530 } 1531 SDB->SwitchCases.clear(); 1532} 1533 1534 1535/// Create the scheduler. If a specific scheduler was specified 1536/// via the SchedulerRegistry, use it, otherwise select the 1537/// one preferred by the target. 1538/// 1539ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1540 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1541 1542 if (!Ctor) { 1543 Ctor = ISHeuristic; 1544 RegisterScheduler::setDefault(Ctor); 1545 } 1546 1547 return Ctor(this, OptLevel); 1548} 1549 1550//===----------------------------------------------------------------------===// 1551// Helper functions used by the generated instruction selector. 1552//===----------------------------------------------------------------------===// 1553// Calls to these methods are generated by tblgen. 1554 1555/// CheckAndMask - The isel is trying to match something like (and X, 255). If 1556/// the dag combiner simplified the 255, we still want to match. RHS is the 1557/// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1558/// specified in the .td file (e.g. 255). 1559bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1560 int64_t DesiredMaskS) const { 1561 const APInt &ActualMask = RHS->getAPIntValue(); 1562 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1563 1564 // If the actual mask exactly matches, success! 1565 if (ActualMask == DesiredMask) 1566 return true; 1567 1568 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1569 if (ActualMask.intersects(~DesiredMask)) 1570 return false; 1571 1572 // Otherwise, the DAG Combiner may have proven that the value coming in is 1573 // either already zero or is not demanded. Check for known zero input bits. 1574 APInt NeededMask = DesiredMask & ~ActualMask; 1575 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1576 return true; 1577 1578 // TODO: check to see if missing bits are just not demanded. 1579 1580 // Otherwise, this pattern doesn't match. 1581 return false; 1582} 1583 1584/// CheckOrMask - The isel is trying to match something like (or X, 255). If 1585/// the dag combiner simplified the 255, we still want to match. RHS is the 1586/// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1587/// specified in the .td file (e.g. 255). 1588bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1589 int64_t DesiredMaskS) const { 1590 const APInt &ActualMask = RHS->getAPIntValue(); 1591 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1592 1593 // If the actual mask exactly matches, success! 1594 if (ActualMask == DesiredMask) 1595 return true; 1596 1597 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1598 if (ActualMask.intersects(~DesiredMask)) 1599 return false; 1600 1601 // Otherwise, the DAG Combiner may have proven that the value coming in is 1602 // either already zero or is not demanded. Check for known zero input bits. 1603 APInt NeededMask = DesiredMask & ~ActualMask; 1604 1605 APInt KnownZero, KnownOne; 1606 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1607 1608 // If all the missing bits in the or are already known to be set, match! 1609 if ((NeededMask & KnownOne) == NeededMask) 1610 return true; 1611 1612 // TODO: check to see if missing bits are just not demanded. 1613 1614 // Otherwise, this pattern doesn't match. 1615 return false; 1616} 1617 1618 1619/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1620/// by tblgen. Others should not call it. 1621void SelectionDAGISel:: 1622SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1623 std::vector<SDValue> InOps; 1624 std::swap(InOps, Ops); 1625 1626 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1627 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1628 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1629 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1630 1631 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1632 if (InOps[e-1].getValueType() == MVT::Glue) 1633 --e; // Don't process a glue operand if it is here. 1634 1635 while (i != e) { 1636 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1637 if (!InlineAsm::isMemKind(Flags)) { 1638 // Just skip over this operand, copying the operands verbatim. 1639 Ops.insert(Ops.end(), InOps.begin()+i, 1640 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1641 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1642 } else { 1643 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1644 "Memory operand with multiple values?"); 1645 // Otherwise, this is a memory operand. Ask the target to select it. 1646 std::vector<SDValue> SelOps; 1647 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1648 report_fatal_error("Could not match memory address. Inline asm" 1649 " failure!"); 1650 1651 // Add this to the output node. 1652 unsigned NewFlags = 1653 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1654 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1655 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1656 i += 2; 1657 } 1658 } 1659 1660 // Add the glue input back if present. 1661 if (e != InOps.size()) 1662 Ops.push_back(InOps.back()); 1663} 1664 1665/// findGlueUse - Return use of MVT::Glue value produced by the specified 1666/// SDNode. 1667/// 1668static SDNode *findGlueUse(SDNode *N) { 1669 unsigned FlagResNo = N->getNumValues()-1; 1670 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1671 SDUse &Use = I.getUse(); 1672 if (Use.getResNo() == FlagResNo) 1673 return Use.getUser(); 1674 } 1675 return NULL; 1676} 1677 1678/// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1679/// This function recursively traverses up the operand chain, ignoring 1680/// certain nodes. 1681static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1682 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1683 bool IgnoreChains) { 1684 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1685 // greater than all of its (recursive) operands. If we scan to a point where 1686 // 'use' is smaller than the node we're scanning for, then we know we will 1687 // never find it. 1688 // 1689 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1690 // happen because we scan down to newly selected nodes in the case of glue 1691 // uses. 1692 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1693 return false; 1694 1695 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1696 // won't fail if we scan it again. 1697 if (!Visited.insert(Use)) 1698 return false; 1699 1700 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1701 // Ignore chain uses, they are validated by HandleMergeInputChains. 1702 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1703 continue; 1704 1705 SDNode *N = Use->getOperand(i).getNode(); 1706 if (N == Def) { 1707 if (Use == ImmedUse || Use == Root) 1708 continue; // We are not looking for immediate use. 1709 assert(N != Root); 1710 return true; 1711 } 1712 1713 // Traverse up the operand chain. 1714 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1715 return true; 1716 } 1717 return false; 1718} 1719 1720/// IsProfitableToFold - Returns true if it's profitable to fold the specific 1721/// operand node N of U during instruction selection that starts at Root. 1722bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1723 SDNode *Root) const { 1724 if (OptLevel == CodeGenOpt::None) return false; 1725 return N.hasOneUse(); 1726} 1727 1728/// IsLegalToFold - Returns true if the specific operand node N of 1729/// U can be folded during instruction selection that starts at Root. 1730bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1731 CodeGenOpt::Level OptLevel, 1732 bool IgnoreChains) { 1733 if (OptLevel == CodeGenOpt::None) return false; 1734 1735 // If Root use can somehow reach N through a path that that doesn't contain 1736 // U then folding N would create a cycle. e.g. In the following 1737 // diagram, Root can reach N through X. If N is folded into into Root, then 1738 // X is both a predecessor and a successor of U. 1739 // 1740 // [N*] // 1741 // ^ ^ // 1742 // / \ // 1743 // [U*] [X]? // 1744 // ^ ^ // 1745 // \ / // 1746 // \ / // 1747 // [Root*] // 1748 // 1749 // * indicates nodes to be folded together. 1750 // 1751 // If Root produces glue, then it gets (even more) interesting. Since it 1752 // will be "glued" together with its glue use in the scheduler, we need to 1753 // check if it might reach N. 1754 // 1755 // [N*] // 1756 // ^ ^ // 1757 // / \ // 1758 // [U*] [X]? // 1759 // ^ ^ // 1760 // \ \ // 1761 // \ | // 1762 // [Root*] | // 1763 // ^ | // 1764 // f | // 1765 // | / // 1766 // [Y] / // 1767 // ^ / // 1768 // f / // 1769 // | / // 1770 // [GU] // 1771 // 1772 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1773 // (call it Fold), then X is a predecessor of GU and a successor of 1774 // Fold. But since Fold and GU are glued together, this will create 1775 // a cycle in the scheduling graph. 1776 1777 // If the node has glue, walk down the graph to the "lowest" node in the 1778 // glueged set. 1779 EVT VT = Root->getValueType(Root->getNumValues()-1); 1780 while (VT == MVT::Glue) { 1781 SDNode *GU = findGlueUse(Root); 1782 if (GU == NULL) 1783 break; 1784 Root = GU; 1785 VT = Root->getValueType(Root->getNumValues()-1); 1786 1787 // If our query node has a glue result with a use, we've walked up it. If 1788 // the user (which has already been selected) has a chain or indirectly uses 1789 // the chain, our WalkChainUsers predicate will not consider it. Because of 1790 // this, we cannot ignore chains in this predicate. 1791 IgnoreChains = false; 1792 } 1793 1794 1795 SmallPtrSet<SDNode*, 16> Visited; 1796 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1797} 1798 1799SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1800 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1801 SelectInlineAsmMemoryOperands(Ops); 1802 1803 EVT VTs[] = { MVT::Other, MVT::Glue }; 1804 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), 1805 VTs, &Ops[0], Ops.size()); 1806 New->setNodeId(-1); 1807 return New.getNode(); 1808} 1809 1810SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1811 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1812} 1813 1814/// GetVBR - decode a vbr encoding whose top bit is set. 1815LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1816GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1817 assert(Val >= 128 && "Not a VBR"); 1818 Val &= 127; // Remove first vbr bit. 1819 1820 unsigned Shift = 7; 1821 uint64_t NextBits; 1822 do { 1823 NextBits = MatcherTable[Idx++]; 1824 Val |= (NextBits&127) << Shift; 1825 Shift += 7; 1826 } while (NextBits & 128); 1827 1828 return Val; 1829} 1830 1831 1832/// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1833/// interior glue and chain results to use the new glue and chain results. 1834void SelectionDAGISel:: 1835UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1836 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1837 SDValue InputGlue, 1838 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1839 bool isMorphNodeTo) { 1840 SmallVector<SDNode*, 4> NowDeadNodes; 1841 1842 // Now that all the normal results are replaced, we replace the chain and 1843 // glue results if present. 1844 if (!ChainNodesMatched.empty()) { 1845 assert(InputChain.getNode() != 0 && 1846 "Matched input chains but didn't produce a chain"); 1847 // Loop over all of the nodes we matched that produced a chain result. 1848 // Replace all the chain results with the final chain we ended up with. 1849 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1850 SDNode *ChainNode = ChainNodesMatched[i]; 1851 1852 // If this node was already deleted, don't look at it. 1853 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1854 continue; 1855 1856 // Don't replace the results of the root node if we're doing a 1857 // MorphNodeTo. 1858 if (ChainNode == NodeToMatch && isMorphNodeTo) 1859 continue; 1860 1861 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1862 if (ChainVal.getValueType() == MVT::Glue) 1863 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1864 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1865 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1866 1867 // If the node became dead and we haven't already seen it, delete it. 1868 if (ChainNode->use_empty() && 1869 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1870 NowDeadNodes.push_back(ChainNode); 1871 } 1872 } 1873 1874 // If the result produces glue, update any glue results in the matched 1875 // pattern with the glue result. 1876 if (InputGlue.getNode() != 0) { 1877 // Handle any interior nodes explicitly marked. 1878 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1879 SDNode *FRN = GlueResultNodesMatched[i]; 1880 1881 // If this node was already deleted, don't look at it. 1882 if (FRN->getOpcode() == ISD::DELETED_NODE) 1883 continue; 1884 1885 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1886 "Doesn't have a glue result"); 1887 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1888 InputGlue); 1889 1890 // If the node became dead and we haven't already seen it, delete it. 1891 if (FRN->use_empty() && 1892 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1893 NowDeadNodes.push_back(FRN); 1894 } 1895 } 1896 1897 if (!NowDeadNodes.empty()) 1898 CurDAG->RemoveDeadNodes(NowDeadNodes); 1899 1900 DEBUG(dbgs() << "ISEL: Match complete!\n"); 1901} 1902 1903enum ChainResult { 1904 CR_Simple, 1905 CR_InducesCycle, 1906 CR_LeadsToInteriorNode 1907}; 1908 1909/// WalkChainUsers - Walk down the users of the specified chained node that is 1910/// part of the pattern we're matching, looking at all of the users we find. 1911/// This determines whether something is an interior node, whether we have a 1912/// non-pattern node in between two pattern nodes (which prevent folding because 1913/// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1914/// between pattern nodes (in which case the TF becomes part of the pattern). 1915/// 1916/// The walk we do here is guaranteed to be small because we quickly get down to 1917/// already selected nodes "below" us. 1918static ChainResult 1919WalkChainUsers(const SDNode *ChainedNode, 1920 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1921 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1922 ChainResult Result = CR_Simple; 1923 1924 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1925 E = ChainedNode->use_end(); UI != E; ++UI) { 1926 // Make sure the use is of the chain, not some other value we produce. 1927 if (UI.getUse().getValueType() != MVT::Other) continue; 1928 1929 SDNode *User = *UI; 1930 1931 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1932 continue; 1933 1934 // If we see an already-selected machine node, then we've gone beyond the 1935 // pattern that we're selecting down into the already selected chunk of the 1936 // DAG. 1937 unsigned UserOpcode = User->getOpcode(); 1938 if (User->isMachineOpcode() || 1939 UserOpcode == ISD::CopyToReg || 1940 UserOpcode == ISD::CopyFromReg || 1941 UserOpcode == ISD::INLINEASM || 1942 UserOpcode == ISD::EH_LABEL || 1943 UserOpcode == ISD::LIFETIME_START || 1944 UserOpcode == ISD::LIFETIME_END) { 1945 // If their node ID got reset to -1 then they've already been selected. 1946 // Treat them like a MachineOpcode. 1947 if (User->getNodeId() == -1) 1948 continue; 1949 } 1950 1951 // If we have a TokenFactor, we handle it specially. 1952 if (User->getOpcode() != ISD::TokenFactor) { 1953 // If the node isn't a token factor and isn't part of our pattern, then it 1954 // must be a random chained node in between two nodes we're selecting. 1955 // This happens when we have something like: 1956 // x = load ptr 1957 // call 1958 // y = x+4 1959 // store y -> ptr 1960 // Because we structurally match the load/store as a read/modify/write, 1961 // but the call is chained between them. We cannot fold in this case 1962 // because it would induce a cycle in the graph. 1963 if (!std::count(ChainedNodesInPattern.begin(), 1964 ChainedNodesInPattern.end(), User)) 1965 return CR_InducesCycle; 1966 1967 // Otherwise we found a node that is part of our pattern. For example in: 1968 // x = load ptr 1969 // y = x+4 1970 // store y -> ptr 1971 // This would happen when we're scanning down from the load and see the 1972 // store as a user. Record that there is a use of ChainedNode that is 1973 // part of the pattern and keep scanning uses. 1974 Result = CR_LeadsToInteriorNode; 1975 InteriorChainedNodes.push_back(User); 1976 continue; 1977 } 1978 1979 // If we found a TokenFactor, there are two cases to consider: first if the 1980 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1981 // uses of the TF are in our pattern) we just want to ignore it. Second, 1982 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1983 // [Load chain] 1984 // ^ 1985 // | 1986 // [Load] 1987 // ^ ^ 1988 // | \ DAG's like cheese 1989 // / \ do you? 1990 // / | 1991 // [TokenFactor] [Op] 1992 // ^ ^ 1993 // | | 1994 // \ / 1995 // \ / 1996 // [Store] 1997 // 1998 // In this case, the TokenFactor becomes part of our match and we rewrite it 1999 // as a new TokenFactor. 2000 // 2001 // To distinguish these two cases, do a recursive walk down the uses. 2002 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 2003 case CR_Simple: 2004 // If the uses of the TokenFactor are just already-selected nodes, ignore 2005 // it, it is "below" our pattern. 2006 continue; 2007 case CR_InducesCycle: 2008 // If the uses of the TokenFactor lead to nodes that are not part of our 2009 // pattern that are not selected, folding would turn this into a cycle, 2010 // bail out now. 2011 return CR_InducesCycle; 2012 case CR_LeadsToInteriorNode: 2013 break; // Otherwise, keep processing. 2014 } 2015 2016 // Okay, we know we're in the interesting interior case. The TokenFactor 2017 // is now going to be considered part of the pattern so that we rewrite its 2018 // uses (it may have uses that are not part of the pattern) with the 2019 // ultimate chain result of the generated code. We will also add its chain 2020 // inputs as inputs to the ultimate TokenFactor we create. 2021 Result = CR_LeadsToInteriorNode; 2022 ChainedNodesInPattern.push_back(User); 2023 InteriorChainedNodes.push_back(User); 2024 continue; 2025 } 2026 2027 return Result; 2028} 2029 2030/// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2031/// operation for when the pattern matched at least one node with a chains. The 2032/// input vector contains a list of all of the chained nodes that we match. We 2033/// must determine if this is a valid thing to cover (i.e. matching it won't 2034/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2035/// be used as the input node chain for the generated nodes. 2036static SDValue 2037HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2038 SelectionDAG *CurDAG) { 2039 // Walk all of the chained nodes we've matched, recursively scanning down the 2040 // users of the chain result. This adds any TokenFactor nodes that are caught 2041 // in between chained nodes to the chained and interior nodes list. 2042 SmallVector<SDNode*, 3> InteriorChainedNodes; 2043 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2044 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2045 InteriorChainedNodes) == CR_InducesCycle) 2046 return SDValue(); // Would induce a cycle. 2047 } 2048 2049 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2050 // that we are interested in. Form our input TokenFactor node. 2051 SmallVector<SDValue, 3> InputChains; 2052 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2053 // Add the input chain of this node to the InputChains list (which will be 2054 // the operands of the generated TokenFactor) if it's not an interior node. 2055 SDNode *N = ChainNodesMatched[i]; 2056 if (N->getOpcode() != ISD::TokenFactor) { 2057 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2058 continue; 2059 2060 // Otherwise, add the input chain. 2061 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2062 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2063 InputChains.push_back(InChain); 2064 continue; 2065 } 2066 2067 // If we have a token factor, we want to add all inputs of the token factor 2068 // that are not part of the pattern we're matching. 2069 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2070 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2071 N->getOperand(op).getNode())) 2072 InputChains.push_back(N->getOperand(op)); 2073 } 2074 } 2075 2076 if (InputChains.size() == 1) 2077 return InputChains[0]; 2078 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2079 MVT::Other, &InputChains[0], InputChains.size()); 2080} 2081 2082/// MorphNode - Handle morphing a node in place for the selector. 2083SDNode *SelectionDAGISel:: 2084MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2085 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 2086 // It is possible we're using MorphNodeTo to replace a node with no 2087 // normal results with one that has a normal result (or we could be 2088 // adding a chain) and the input could have glue and chains as well. 2089 // In this case we need to shift the operands down. 2090 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2091 // than the old isel though. 2092 int OldGlueResultNo = -1, OldChainResultNo = -1; 2093 2094 unsigned NTMNumResults = Node->getNumValues(); 2095 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2096 OldGlueResultNo = NTMNumResults-1; 2097 if (NTMNumResults != 1 && 2098 Node->getValueType(NTMNumResults-2) == MVT::Other) 2099 OldChainResultNo = NTMNumResults-2; 2100 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2101 OldChainResultNo = NTMNumResults-1; 2102 2103 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2104 // that this deletes operands of the old node that become dead. 2105 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 2106 2107 // MorphNodeTo can operate in two ways: if an existing node with the 2108 // specified operands exists, it can just return it. Otherwise, it 2109 // updates the node in place to have the requested operands. 2110 if (Res == Node) { 2111 // If we updated the node in place, reset the node ID. To the isel, 2112 // this should be just like a newly allocated machine node. 2113 Res->setNodeId(-1); 2114 } 2115 2116 unsigned ResNumResults = Res->getNumValues(); 2117 // Move the glue if needed. 2118 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2119 (unsigned)OldGlueResultNo != ResNumResults-1) 2120 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2121 SDValue(Res, ResNumResults-1)); 2122 2123 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2124 --ResNumResults; 2125 2126 // Move the chain reference if needed. 2127 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2128 (unsigned)OldChainResultNo != ResNumResults-1) 2129 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2130 SDValue(Res, ResNumResults-1)); 2131 2132 // Otherwise, no replacement happened because the node already exists. Replace 2133 // Uses of the old node with the new one. 2134 if (Res != Node) 2135 CurDAG->ReplaceAllUsesWith(Node, Res); 2136 2137 return Res; 2138} 2139 2140/// CheckSame - Implements OP_CheckSame. 2141LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2142CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2143 SDValue N, 2144 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2145 // Accept if it is exactly the same as a previously recorded node. 2146 unsigned RecNo = MatcherTable[MatcherIndex++]; 2147 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2148 return N == RecordedNodes[RecNo].first; 2149} 2150 2151/// CheckChildSame - Implements OP_CheckChildXSame. 2152LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2153CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2154 SDValue N, 2155 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2156 unsigned ChildNo) { 2157 if (ChildNo >= N.getNumOperands()) 2158 return false; // Match fails if out of range child #. 2159 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2160 RecordedNodes); 2161} 2162 2163/// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2164LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2165CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2166 const SelectionDAGISel &SDISel) { 2167 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2168} 2169 2170/// CheckNodePredicate - Implements OP_CheckNodePredicate. 2171LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2172CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2173 const SelectionDAGISel &SDISel, SDNode *N) { 2174 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2175} 2176 2177LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2178CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2179 SDNode *N) { 2180 uint16_t Opc = MatcherTable[MatcherIndex++]; 2181 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2182 return N->getOpcode() == Opc; 2183} 2184 2185LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2186CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2187 SDValue N, const TargetLowering *TLI) { 2188 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2189 if (N.getValueType() == VT) return true; 2190 2191 // Handle the case when VT is iPTR. 2192 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2193} 2194 2195LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2196CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2197 SDValue N, const TargetLowering *TLI, 2198 unsigned ChildNo) { 2199 if (ChildNo >= N.getNumOperands()) 2200 return false; // Match fails if out of range child #. 2201 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2202} 2203 2204LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2205CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2206 SDValue N) { 2207 return cast<CondCodeSDNode>(N)->get() == 2208 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2209} 2210 2211LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2212CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2213 SDValue N, const TargetLowering *TLI) { 2214 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2215 if (cast<VTSDNode>(N)->getVT() == VT) 2216 return true; 2217 2218 // Handle the case when VT is iPTR. 2219 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2220} 2221 2222LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2223CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2224 SDValue N) { 2225 int64_t Val = MatcherTable[MatcherIndex++]; 2226 if (Val & 128) 2227 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2228 2229 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2230 return C != 0 && C->getSExtValue() == Val; 2231} 2232 2233LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2234CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2235 SDValue N, const SelectionDAGISel &SDISel) { 2236 int64_t Val = MatcherTable[MatcherIndex++]; 2237 if (Val & 128) 2238 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2239 2240 if (N->getOpcode() != ISD::AND) return false; 2241 2242 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2243 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2244} 2245 2246LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2247CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2248 SDValue N, const SelectionDAGISel &SDISel) { 2249 int64_t Val = MatcherTable[MatcherIndex++]; 2250 if (Val & 128) 2251 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2252 2253 if (N->getOpcode() != ISD::OR) return false; 2254 2255 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2256 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2257} 2258 2259/// IsPredicateKnownToFail - If we know how and can do so without pushing a 2260/// scope, evaluate the current node. If the current predicate is known to 2261/// fail, set Result=true and return anything. If the current predicate is 2262/// known to pass, set Result=false and return the MatcherIndex to continue 2263/// with. If the current predicate is unknown, set Result=false and return the 2264/// MatcherIndex to continue with. 2265static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2266 unsigned Index, SDValue N, 2267 bool &Result, 2268 const SelectionDAGISel &SDISel, 2269 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2270 switch (Table[Index++]) { 2271 default: 2272 Result = false; 2273 return Index-1; // Could not evaluate this predicate. 2274 case SelectionDAGISel::OPC_CheckSame: 2275 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2276 return Index; 2277 case SelectionDAGISel::OPC_CheckChild0Same: 2278 case SelectionDAGISel::OPC_CheckChild1Same: 2279 case SelectionDAGISel::OPC_CheckChild2Same: 2280 case SelectionDAGISel::OPC_CheckChild3Same: 2281 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2282 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2283 return Index; 2284 case SelectionDAGISel::OPC_CheckPatternPredicate: 2285 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2286 return Index; 2287 case SelectionDAGISel::OPC_CheckPredicate: 2288 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2289 return Index; 2290 case SelectionDAGISel::OPC_CheckOpcode: 2291 Result = !::CheckOpcode(Table, Index, N.getNode()); 2292 return Index; 2293 case SelectionDAGISel::OPC_CheckType: 2294 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering()); 2295 return Index; 2296 case SelectionDAGISel::OPC_CheckChild0Type: 2297 case SelectionDAGISel::OPC_CheckChild1Type: 2298 case SelectionDAGISel::OPC_CheckChild2Type: 2299 case SelectionDAGISel::OPC_CheckChild3Type: 2300 case SelectionDAGISel::OPC_CheckChild4Type: 2301 case SelectionDAGISel::OPC_CheckChild5Type: 2302 case SelectionDAGISel::OPC_CheckChild6Type: 2303 case SelectionDAGISel::OPC_CheckChild7Type: 2304 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(), 2305 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2306 return Index; 2307 case SelectionDAGISel::OPC_CheckCondCode: 2308 Result = !::CheckCondCode(Table, Index, N); 2309 return Index; 2310 case SelectionDAGISel::OPC_CheckValueType: 2311 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering()); 2312 return Index; 2313 case SelectionDAGISel::OPC_CheckInteger: 2314 Result = !::CheckInteger(Table, Index, N); 2315 return Index; 2316 case SelectionDAGISel::OPC_CheckAndImm: 2317 Result = !::CheckAndImm(Table, Index, N, SDISel); 2318 return Index; 2319 case SelectionDAGISel::OPC_CheckOrImm: 2320 Result = !::CheckOrImm(Table, Index, N, SDISel); 2321 return Index; 2322 } 2323} 2324 2325namespace { 2326 2327struct MatchScope { 2328 /// FailIndex - If this match fails, this is the index to continue with. 2329 unsigned FailIndex; 2330 2331 /// NodeStack - The node stack when the scope was formed. 2332 SmallVector<SDValue, 4> NodeStack; 2333 2334 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2335 unsigned NumRecordedNodes; 2336 2337 /// NumMatchedMemRefs - The number of matched memref entries. 2338 unsigned NumMatchedMemRefs; 2339 2340 /// InputChain/InputGlue - The current chain/glue 2341 SDValue InputChain, InputGlue; 2342 2343 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2344 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2345}; 2346 2347} 2348 2349SDNode *SelectionDAGISel:: 2350SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2351 unsigned TableSize) { 2352 // FIXME: Should these even be selected? Handle these cases in the caller? 2353 switch (NodeToMatch->getOpcode()) { 2354 default: 2355 break; 2356 case ISD::EntryToken: // These nodes remain the same. 2357 case ISD::BasicBlock: 2358 case ISD::Register: 2359 case ISD::RegisterMask: 2360 //case ISD::VALUETYPE: 2361 //case ISD::CONDCODE: 2362 case ISD::HANDLENODE: 2363 case ISD::MDNODE_SDNODE: 2364 case ISD::TargetConstant: 2365 case ISD::TargetConstantFP: 2366 case ISD::TargetConstantPool: 2367 case ISD::TargetFrameIndex: 2368 case ISD::TargetExternalSymbol: 2369 case ISD::TargetBlockAddress: 2370 case ISD::TargetJumpTable: 2371 case ISD::TargetGlobalTLSAddress: 2372 case ISD::TargetGlobalAddress: 2373 case ISD::TokenFactor: 2374 case ISD::CopyFromReg: 2375 case ISD::CopyToReg: 2376 case ISD::EH_LABEL: 2377 case ISD::LIFETIME_START: 2378 case ISD::LIFETIME_END: 2379 NodeToMatch->setNodeId(-1); // Mark selected. 2380 return 0; 2381 case ISD::AssertSext: 2382 case ISD::AssertZext: 2383 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2384 NodeToMatch->getOperand(0)); 2385 return 0; 2386 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2387 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2388 } 2389 2390 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2391 2392 // Set up the node stack with NodeToMatch as the only node on the stack. 2393 SmallVector<SDValue, 8> NodeStack; 2394 SDValue N = SDValue(NodeToMatch, 0); 2395 NodeStack.push_back(N); 2396 2397 // MatchScopes - Scopes used when matching, if a match failure happens, this 2398 // indicates where to continue checking. 2399 SmallVector<MatchScope, 8> MatchScopes; 2400 2401 // RecordedNodes - This is the set of nodes that have been recorded by the 2402 // state machine. The second value is the parent of the node, or null if the 2403 // root is recorded. 2404 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2405 2406 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2407 // pattern. 2408 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2409 2410 // These are the current input chain and glue for use when generating nodes. 2411 // Various Emit operations change these. For example, emitting a copytoreg 2412 // uses and updates these. 2413 SDValue InputChain, InputGlue; 2414 2415 // ChainNodesMatched - If a pattern matches nodes that have input/output 2416 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2417 // which ones they are. The result is captured into this list so that we can 2418 // update the chain results when the pattern is complete. 2419 SmallVector<SDNode*, 3> ChainNodesMatched; 2420 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2421 2422 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2423 NodeToMatch->dump(CurDAG); 2424 dbgs() << '\n'); 2425 2426 // Determine where to start the interpreter. Normally we start at opcode #0, 2427 // but if the state machine starts with an OPC_SwitchOpcode, then we 2428 // accelerate the first lookup (which is guaranteed to be hot) with the 2429 // OpcodeOffset table. 2430 unsigned MatcherIndex = 0; 2431 2432 if (!OpcodeOffset.empty()) { 2433 // Already computed the OpcodeOffset table, just index into it. 2434 if (N.getOpcode() < OpcodeOffset.size()) 2435 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2436 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2437 2438 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2439 // Otherwise, the table isn't computed, but the state machine does start 2440 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2441 // is the first time we're selecting an instruction. 2442 unsigned Idx = 1; 2443 while (1) { 2444 // Get the size of this case. 2445 unsigned CaseSize = MatcherTable[Idx++]; 2446 if (CaseSize & 128) 2447 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2448 if (CaseSize == 0) break; 2449 2450 // Get the opcode, add the index to the table. 2451 uint16_t Opc = MatcherTable[Idx++]; 2452 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2453 if (Opc >= OpcodeOffset.size()) 2454 OpcodeOffset.resize((Opc+1)*2); 2455 OpcodeOffset[Opc] = Idx; 2456 Idx += CaseSize; 2457 } 2458 2459 // Okay, do the lookup for the first opcode. 2460 if (N.getOpcode() < OpcodeOffset.size()) 2461 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2462 } 2463 2464 while (1) { 2465 assert(MatcherIndex < TableSize && "Invalid index"); 2466#ifndef NDEBUG 2467 unsigned CurrentOpcodeIndex = MatcherIndex; 2468#endif 2469 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2470 switch (Opcode) { 2471 case OPC_Scope: { 2472 // Okay, the semantics of this operation are that we should push a scope 2473 // then evaluate the first child. However, pushing a scope only to have 2474 // the first check fail (which then pops it) is inefficient. If we can 2475 // determine immediately that the first check (or first several) will 2476 // immediately fail, don't even bother pushing a scope for them. 2477 unsigned FailIndex; 2478 2479 while (1) { 2480 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2481 if (NumToSkip & 128) 2482 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2483 // Found the end of the scope with no match. 2484 if (NumToSkip == 0) { 2485 FailIndex = 0; 2486 break; 2487 } 2488 2489 FailIndex = MatcherIndex+NumToSkip; 2490 2491 unsigned MatcherIndexOfPredicate = MatcherIndex; 2492 (void)MatcherIndexOfPredicate; // silence warning. 2493 2494 // If we can't evaluate this predicate without pushing a scope (e.g. if 2495 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2496 // push the scope and evaluate the full predicate chain. 2497 bool Result; 2498 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2499 Result, *this, RecordedNodes); 2500 if (!Result) 2501 break; 2502 2503 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2504 << "index " << MatcherIndexOfPredicate 2505 << ", continuing at " << FailIndex << "\n"); 2506 ++NumDAGIselRetries; 2507 2508 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2509 // move to the next case. 2510 MatcherIndex = FailIndex; 2511 } 2512 2513 // If the whole scope failed to match, bail. 2514 if (FailIndex == 0) break; 2515 2516 // Push a MatchScope which indicates where to go if the first child fails 2517 // to match. 2518 MatchScope NewEntry; 2519 NewEntry.FailIndex = FailIndex; 2520 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2521 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2522 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2523 NewEntry.InputChain = InputChain; 2524 NewEntry.InputGlue = InputGlue; 2525 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2526 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2527 MatchScopes.push_back(NewEntry); 2528 continue; 2529 } 2530 case OPC_RecordNode: { 2531 // Remember this node, it may end up being an operand in the pattern. 2532 SDNode *Parent = 0; 2533 if (NodeStack.size() > 1) 2534 Parent = NodeStack[NodeStack.size()-2].getNode(); 2535 RecordedNodes.push_back(std::make_pair(N, Parent)); 2536 continue; 2537 } 2538 2539 case OPC_RecordChild0: case OPC_RecordChild1: 2540 case OPC_RecordChild2: case OPC_RecordChild3: 2541 case OPC_RecordChild4: case OPC_RecordChild5: 2542 case OPC_RecordChild6: case OPC_RecordChild7: { 2543 unsigned ChildNo = Opcode-OPC_RecordChild0; 2544 if (ChildNo >= N.getNumOperands()) 2545 break; // Match fails if out of range child #. 2546 2547 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2548 N.getNode())); 2549 continue; 2550 } 2551 case OPC_RecordMemRef: 2552 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2553 continue; 2554 2555 case OPC_CaptureGlueInput: 2556 // If the current node has an input glue, capture it in InputGlue. 2557 if (N->getNumOperands() != 0 && 2558 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2559 InputGlue = N->getOperand(N->getNumOperands()-1); 2560 continue; 2561 2562 case OPC_MoveChild: { 2563 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2564 if (ChildNo >= N.getNumOperands()) 2565 break; // Match fails if out of range child #. 2566 N = N.getOperand(ChildNo); 2567 NodeStack.push_back(N); 2568 continue; 2569 } 2570 2571 case OPC_MoveParent: 2572 // Pop the current node off the NodeStack. 2573 NodeStack.pop_back(); 2574 assert(!NodeStack.empty() && "Node stack imbalance!"); 2575 N = NodeStack.back(); 2576 continue; 2577 2578 case OPC_CheckSame: 2579 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2580 continue; 2581 2582 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2583 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2584 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2585 Opcode-OPC_CheckChild0Same)) 2586 break; 2587 continue; 2588 2589 case OPC_CheckPatternPredicate: 2590 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2591 continue; 2592 case OPC_CheckPredicate: 2593 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2594 N.getNode())) 2595 break; 2596 continue; 2597 case OPC_CheckComplexPat: { 2598 unsigned CPNum = MatcherTable[MatcherIndex++]; 2599 unsigned RecNo = MatcherTable[MatcherIndex++]; 2600 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2601 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2602 RecordedNodes[RecNo].first, CPNum, 2603 RecordedNodes)) 2604 break; 2605 continue; 2606 } 2607 case OPC_CheckOpcode: 2608 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2609 continue; 2610 2611 case OPC_CheckType: 2612 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2613 break; 2614 continue; 2615 2616 case OPC_SwitchOpcode: { 2617 unsigned CurNodeOpcode = N.getOpcode(); 2618 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2619 unsigned CaseSize; 2620 while (1) { 2621 // Get the size of this case. 2622 CaseSize = MatcherTable[MatcherIndex++]; 2623 if (CaseSize & 128) 2624 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2625 if (CaseSize == 0) break; 2626 2627 uint16_t Opc = MatcherTable[MatcherIndex++]; 2628 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2629 2630 // If the opcode matches, then we will execute this case. 2631 if (CurNodeOpcode == Opc) 2632 break; 2633 2634 // Otherwise, skip over this case. 2635 MatcherIndex += CaseSize; 2636 } 2637 2638 // If no cases matched, bail out. 2639 if (CaseSize == 0) break; 2640 2641 // Otherwise, execute the case we found. 2642 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2643 << " to " << MatcherIndex << "\n"); 2644 continue; 2645 } 2646 2647 case OPC_SwitchType: { 2648 MVT CurNodeVT = N.getSimpleValueType(); 2649 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2650 unsigned CaseSize; 2651 while (1) { 2652 // Get the size of this case. 2653 CaseSize = MatcherTable[MatcherIndex++]; 2654 if (CaseSize & 128) 2655 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2656 if (CaseSize == 0) break; 2657 2658 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2659 if (CaseVT == MVT::iPTR) 2660 CaseVT = getTargetLowering()->getPointerTy(); 2661 2662 // If the VT matches, then we will execute this case. 2663 if (CurNodeVT == CaseVT) 2664 break; 2665 2666 // Otherwise, skip over this case. 2667 MatcherIndex += CaseSize; 2668 } 2669 2670 // If no cases matched, bail out. 2671 if (CaseSize == 0) break; 2672 2673 // Otherwise, execute the case we found. 2674 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2675 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2676 continue; 2677 } 2678 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2679 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2680 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2681 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2682 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(), 2683 Opcode-OPC_CheckChild0Type)) 2684 break; 2685 continue; 2686 case OPC_CheckCondCode: 2687 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2688 continue; 2689 case OPC_CheckValueType: 2690 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering())) 2691 break; 2692 continue; 2693 case OPC_CheckInteger: 2694 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2695 continue; 2696 case OPC_CheckAndImm: 2697 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2698 continue; 2699 case OPC_CheckOrImm: 2700 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2701 continue; 2702 2703 case OPC_CheckFoldableChainNode: { 2704 assert(NodeStack.size() != 1 && "No parent node"); 2705 // Verify that all intermediate nodes between the root and this one have 2706 // a single use. 2707 bool HasMultipleUses = false; 2708 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2709 if (!NodeStack[i].hasOneUse()) { 2710 HasMultipleUses = true; 2711 break; 2712 } 2713 if (HasMultipleUses) break; 2714 2715 // Check to see that the target thinks this is profitable to fold and that 2716 // we can fold it without inducing cycles in the graph. 2717 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2718 NodeToMatch) || 2719 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2720 NodeToMatch, OptLevel, 2721 true/*We validate our own chains*/)) 2722 break; 2723 2724 continue; 2725 } 2726 case OPC_EmitInteger: { 2727 MVT::SimpleValueType VT = 2728 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2729 int64_t Val = MatcherTable[MatcherIndex++]; 2730 if (Val & 128) 2731 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2732 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2733 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2734 continue; 2735 } 2736 case OPC_EmitRegister: { 2737 MVT::SimpleValueType VT = 2738 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2739 unsigned RegNo = MatcherTable[MatcherIndex++]; 2740 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2741 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2742 continue; 2743 } 2744 case OPC_EmitRegister2: { 2745 // For targets w/ more than 256 register names, the register enum 2746 // values are stored in two bytes in the matcher table (just like 2747 // opcodes). 2748 MVT::SimpleValueType VT = 2749 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2750 unsigned RegNo = MatcherTable[MatcherIndex++]; 2751 RegNo |= MatcherTable[MatcherIndex++] << 8; 2752 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2753 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2754 continue; 2755 } 2756 2757 case OPC_EmitConvertToTarget: { 2758 // Convert from IMM/FPIMM to target version. 2759 unsigned RecNo = MatcherTable[MatcherIndex++]; 2760 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 2761 SDValue Imm = RecordedNodes[RecNo].first; 2762 2763 if (Imm->getOpcode() == ISD::Constant) { 2764 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 2765 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 2766 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2767 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2768 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 2769 } 2770 2771 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2772 continue; 2773 } 2774 2775 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2776 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2777 // These are space-optimized forms of OPC_EmitMergeInputChains. 2778 assert(InputChain.getNode() == 0 && 2779 "EmitMergeInputChains should be the first chain producing node"); 2780 assert(ChainNodesMatched.empty() && 2781 "Should only have one EmitMergeInputChains per match"); 2782 2783 // Read all of the chained nodes. 2784 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2785 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2786 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2787 2788 // FIXME: What if other value results of the node have uses not matched 2789 // by this pattern? 2790 if (ChainNodesMatched.back() != NodeToMatch && 2791 !RecordedNodes[RecNo].first.hasOneUse()) { 2792 ChainNodesMatched.clear(); 2793 break; 2794 } 2795 2796 // Merge the input chains if they are not intra-pattern references. 2797 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2798 2799 if (InputChain.getNode() == 0) 2800 break; // Failed to merge. 2801 continue; 2802 } 2803 2804 case OPC_EmitMergeInputChains: { 2805 assert(InputChain.getNode() == 0 && 2806 "EmitMergeInputChains should be the first chain producing node"); 2807 // This node gets a list of nodes we matched in the input that have 2808 // chains. We want to token factor all of the input chains to these nodes 2809 // together. However, if any of the input chains is actually one of the 2810 // nodes matched in this pattern, then we have an intra-match reference. 2811 // Ignore these because the newly token factored chain should not refer to 2812 // the old nodes. 2813 unsigned NumChains = MatcherTable[MatcherIndex++]; 2814 assert(NumChains != 0 && "Can't TF zero chains"); 2815 2816 assert(ChainNodesMatched.empty() && 2817 "Should only have one EmitMergeInputChains per match"); 2818 2819 // Read all of the chained nodes. 2820 for (unsigned i = 0; i != NumChains; ++i) { 2821 unsigned RecNo = MatcherTable[MatcherIndex++]; 2822 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 2823 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2824 2825 // FIXME: What if other value results of the node have uses not matched 2826 // by this pattern? 2827 if (ChainNodesMatched.back() != NodeToMatch && 2828 !RecordedNodes[RecNo].first.hasOneUse()) { 2829 ChainNodesMatched.clear(); 2830 break; 2831 } 2832 } 2833 2834 // If the inner loop broke out, the match fails. 2835 if (ChainNodesMatched.empty()) 2836 break; 2837 2838 // Merge the input chains if they are not intra-pattern references. 2839 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2840 2841 if (InputChain.getNode() == 0) 2842 break; // Failed to merge. 2843 2844 continue; 2845 } 2846 2847 case OPC_EmitCopyToReg: { 2848 unsigned RecNo = MatcherTable[MatcherIndex++]; 2849 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 2850 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2851 2852 if (InputChain.getNode() == 0) 2853 InputChain = CurDAG->getEntryNode(); 2854 2855 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 2856 DestPhysReg, RecordedNodes[RecNo].first, 2857 InputGlue); 2858 2859 InputGlue = InputChain.getValue(1); 2860 continue; 2861 } 2862 2863 case OPC_EmitNodeXForm: { 2864 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2865 unsigned RecNo = MatcherTable[MatcherIndex++]; 2866 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 2867 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2868 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2869 continue; 2870 } 2871 2872 case OPC_EmitNode: 2873 case OPC_MorphNodeTo: { 2874 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2875 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2876 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2877 // Get the result VT list. 2878 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2879 SmallVector<EVT, 4> VTs; 2880 for (unsigned i = 0; i != NumVTs; ++i) { 2881 MVT::SimpleValueType VT = 2882 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2883 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy; 2884 VTs.push_back(VT); 2885 } 2886 2887 if (EmitNodeInfo & OPFL_Chain) 2888 VTs.push_back(MVT::Other); 2889 if (EmitNodeInfo & OPFL_GlueOutput) 2890 VTs.push_back(MVT::Glue); 2891 2892 // This is hot code, so optimize the two most common cases of 1 and 2 2893 // results. 2894 SDVTList VTList; 2895 if (VTs.size() == 1) 2896 VTList = CurDAG->getVTList(VTs[0]); 2897 else if (VTs.size() == 2) 2898 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2899 else 2900 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2901 2902 // Get the operand list. 2903 unsigned NumOps = MatcherTable[MatcherIndex++]; 2904 SmallVector<SDValue, 8> Ops; 2905 for (unsigned i = 0; i != NumOps; ++i) { 2906 unsigned RecNo = MatcherTable[MatcherIndex++]; 2907 if (RecNo & 128) 2908 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2909 2910 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2911 Ops.push_back(RecordedNodes[RecNo].first); 2912 } 2913 2914 // If there are variadic operands to add, handle them now. 2915 if (EmitNodeInfo & OPFL_VariadicInfo) { 2916 // Determine the start index to copy from. 2917 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2918 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2919 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2920 "Invalid variadic node"); 2921 // Copy all of the variadic operands, not including a potential glue 2922 // input. 2923 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2924 i != e; ++i) { 2925 SDValue V = NodeToMatch->getOperand(i); 2926 if (V.getValueType() == MVT::Glue) break; 2927 Ops.push_back(V); 2928 } 2929 } 2930 2931 // If this has chain/glue inputs, add them. 2932 if (EmitNodeInfo & OPFL_Chain) 2933 Ops.push_back(InputChain); 2934 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2935 Ops.push_back(InputGlue); 2936 2937 // Create the node. 2938 SDNode *Res = 0; 2939 if (Opcode != OPC_MorphNodeTo) { 2940 // If this is a normal EmitNode command, just create the new node and 2941 // add the results to the RecordedNodes list. 2942 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 2943 VTList, Ops); 2944 2945 // Add all the non-glue/non-chain results to the RecordedNodes list. 2946 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2947 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2948 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2949 (SDNode*) 0)); 2950 } 2951 2952 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2953 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2954 EmitNodeInfo); 2955 } else { 2956 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2957 // We will visit the equivalent node later. 2958 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2959 return 0; 2960 } 2961 2962 // If the node had chain/glue results, update our notion of the current 2963 // chain and glue. 2964 if (EmitNodeInfo & OPFL_GlueOutput) { 2965 InputGlue = SDValue(Res, VTs.size()-1); 2966 if (EmitNodeInfo & OPFL_Chain) 2967 InputChain = SDValue(Res, VTs.size()-2); 2968 } else if (EmitNodeInfo & OPFL_Chain) 2969 InputChain = SDValue(Res, VTs.size()-1); 2970 2971 // If the OPFL_MemRefs glue is set on this node, slap all of the 2972 // accumulated memrefs onto it. 2973 // 2974 // FIXME: This is vastly incorrect for patterns with multiple outputs 2975 // instructions that access memory and for ComplexPatterns that match 2976 // loads. 2977 if (EmitNodeInfo & OPFL_MemRefs) { 2978 // Only attach load or store memory operands if the generated 2979 // instruction may load or store. 2980 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2981 bool mayLoad = MCID.mayLoad(); 2982 bool mayStore = MCID.mayStore(); 2983 2984 unsigned NumMemRefs = 0; 2985 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 2986 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2987 if ((*I)->isLoad()) { 2988 if (mayLoad) 2989 ++NumMemRefs; 2990 } else if ((*I)->isStore()) { 2991 if (mayStore) 2992 ++NumMemRefs; 2993 } else { 2994 ++NumMemRefs; 2995 } 2996 } 2997 2998 MachineSDNode::mmo_iterator MemRefs = 2999 MF->allocateMemRefsArray(NumMemRefs); 3000 3001 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 3002 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3003 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3004 if ((*I)->isLoad()) { 3005 if (mayLoad) 3006 *MemRefsPos++ = *I; 3007 } else if ((*I)->isStore()) { 3008 if (mayStore) 3009 *MemRefsPos++ = *I; 3010 } else { 3011 *MemRefsPos++ = *I; 3012 } 3013 } 3014 3015 cast<MachineSDNode>(Res) 3016 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3017 } 3018 3019 DEBUG(dbgs() << " " 3020 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3021 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3022 3023 // If this was a MorphNodeTo then we're completely done! 3024 if (Opcode == OPC_MorphNodeTo) { 3025 // Update chain and glue uses. 3026 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3027 InputGlue, GlueResultNodesMatched, true); 3028 return Res; 3029 } 3030 3031 continue; 3032 } 3033 3034 case OPC_MarkGlueResults: { 3035 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3036 3037 // Read and remember all the glue-result nodes. 3038 for (unsigned i = 0; i != NumNodes; ++i) { 3039 unsigned RecNo = MatcherTable[MatcherIndex++]; 3040 if (RecNo & 128) 3041 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3042 3043 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3044 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3045 } 3046 continue; 3047 } 3048 3049 case OPC_CompleteMatch: { 3050 // The match has been completed, and any new nodes (if any) have been 3051 // created. Patch up references to the matched dag to use the newly 3052 // created nodes. 3053 unsigned NumResults = MatcherTable[MatcherIndex++]; 3054 3055 for (unsigned i = 0; i != NumResults; ++i) { 3056 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3057 if (ResSlot & 128) 3058 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3059 3060 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3061 SDValue Res = RecordedNodes[ResSlot].first; 3062 3063 assert(i < NodeToMatch->getNumValues() && 3064 NodeToMatch->getValueType(i) != MVT::Other && 3065 NodeToMatch->getValueType(i) != MVT::Glue && 3066 "Invalid number of results to complete!"); 3067 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3068 NodeToMatch->getValueType(i) == MVT::iPTR || 3069 Res.getValueType() == MVT::iPTR || 3070 NodeToMatch->getValueType(i).getSizeInBits() == 3071 Res.getValueType().getSizeInBits()) && 3072 "invalid replacement"); 3073 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3074 } 3075 3076 // If the root node defines glue, add it to the glue nodes to update list. 3077 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3078 GlueResultNodesMatched.push_back(NodeToMatch); 3079 3080 // Update chain and glue uses. 3081 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3082 InputGlue, GlueResultNodesMatched, false); 3083 3084 assert(NodeToMatch->use_empty() && 3085 "Didn't replace all uses of the node?"); 3086 3087 // FIXME: We just return here, which interacts correctly with SelectRoot 3088 // above. We should fix this to not return an SDNode* anymore. 3089 return 0; 3090 } 3091 } 3092 3093 // If the code reached this point, then the match failed. See if there is 3094 // another child to try in the current 'Scope', otherwise pop it until we 3095 // find a case to check. 3096 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3097 ++NumDAGIselRetries; 3098 while (1) { 3099 if (MatchScopes.empty()) { 3100 CannotYetSelect(NodeToMatch); 3101 return 0; 3102 } 3103 3104 // Restore the interpreter state back to the point where the scope was 3105 // formed. 3106 MatchScope &LastScope = MatchScopes.back(); 3107 RecordedNodes.resize(LastScope.NumRecordedNodes); 3108 NodeStack.clear(); 3109 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3110 N = NodeStack.back(); 3111 3112 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3113 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3114 MatcherIndex = LastScope.FailIndex; 3115 3116 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3117 3118 InputChain = LastScope.InputChain; 3119 InputGlue = LastScope.InputGlue; 3120 if (!LastScope.HasChainNodesMatched) 3121 ChainNodesMatched.clear(); 3122 if (!LastScope.HasGlueResultNodesMatched) 3123 GlueResultNodesMatched.clear(); 3124 3125 // Check to see what the offset is at the new MatcherIndex. If it is zero 3126 // we have reached the end of this scope, otherwise we have another child 3127 // in the current scope to try. 3128 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3129 if (NumToSkip & 128) 3130 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3131 3132 // If we have another child in this scope to match, update FailIndex and 3133 // try it. 3134 if (NumToSkip != 0) { 3135 LastScope.FailIndex = MatcherIndex+NumToSkip; 3136 break; 3137 } 3138 3139 // End of this scope, pop it and try the next child in the containing 3140 // scope. 3141 MatchScopes.pop_back(); 3142 } 3143 } 3144} 3145 3146 3147 3148void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3149 std::string msg; 3150 raw_string_ostream Msg(msg); 3151 Msg << "Cannot select: "; 3152 3153 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3154 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3155 N->getOpcode() != ISD::INTRINSIC_VOID) { 3156 N->printrFull(Msg, CurDAG); 3157 Msg << "\nIn function: " << MF->getName(); 3158 } else { 3159 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3160 unsigned iid = 3161 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3162 if (iid < Intrinsic::num_intrinsics) 3163 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3164 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3165 Msg << "target intrinsic %" << TII->getName(iid); 3166 else 3167 Msg << "unknown intrinsic #" << iid; 3168 } 3169 report_fatal_error(Msg.str()); 3170} 3171 3172char SelectionDAGISel::ID = 0; 3173