1207618Srdivacky//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===// 2207618Srdivacky// 3207618Srdivacky// The LLVM Compiler Infrastructure 4207618Srdivacky// 5207618Srdivacky// This file is distributed under the University of Illinois Open Source 6207618Srdivacky// License. See LICENSE.TXT for details. 7207618Srdivacky// 8207618Srdivacky//===----------------------------------------------------------------------===// 9207618Srdivacky// 10207618Srdivacky// This register allocator allocates registers to a basic block at a time, 11207618Srdivacky// attempting to keep values in registers and reusing registers as appropriate. 12207618Srdivacky// 13207618Srdivacky//===----------------------------------------------------------------------===// 14207618Srdivacky 15207618Srdivacky#define DEBUG_TYPE "regalloc" 16249423Sdim#include "llvm/CodeGen/Passes.h" 17249423Sdim#include "llvm/ADT/DenseMap.h" 18249423Sdim#include "llvm/ADT/IndexedMap.h" 19249423Sdim#include "llvm/ADT/STLExtras.h" 20249423Sdim#include "llvm/ADT/SmallSet.h" 21249423Sdim#include "llvm/ADT/SmallVector.h" 22249423Sdim#include "llvm/ADT/SparseSet.h" 23249423Sdim#include "llvm/ADT/Statistic.h" 24249423Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 25207618Srdivacky#include "llvm/CodeGen/MachineFunctionPass.h" 26207618Srdivacky#include "llvm/CodeGen/MachineInstr.h" 27212904Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 28207618Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 29207618Srdivacky#include "llvm/CodeGen/RegAllocRegistry.h" 30239462Sdim#include "llvm/CodeGen/RegisterClassInfo.h" 31249423Sdim#include "llvm/IR/BasicBlock.h" 32207618Srdivacky#include "llvm/Support/CommandLine.h" 33207618Srdivacky#include "llvm/Support/Debug.h" 34207618Srdivacky#include "llvm/Support/ErrorHandling.h" 35207618Srdivacky#include "llvm/Support/raw_ostream.h" 36249423Sdim#include "llvm/Target/TargetInstrInfo.h" 37249423Sdim#include "llvm/Target/TargetMachine.h" 38207618Srdivacky#include <algorithm> 39207618Srdivackyusing namespace llvm; 40207618Srdivacky 41207618SrdivackySTATISTIC(NumStores, "Number of stores added"); 42207618SrdivackySTATISTIC(NumLoads , "Number of loads added"); 43208599SrdivackySTATISTIC(NumCopies, "Number of copies coalesced"); 44207618Srdivacky 45207618Srdivackystatic RegisterRegAlloc 46207618Srdivacky fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator); 47207618Srdivacky 48207618Srdivackynamespace { 49207618Srdivacky class RAFast : public MachineFunctionPass { 50207618Srdivacky public: 51207618Srdivacky static char ID; 52212904Sdim RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1), 53234353Sdim isBulkSpilling(false) {} 54207618Srdivacky private: 55207618Srdivacky const TargetMachine *TM; 56207618Srdivacky MachineFunction *MF; 57208599Srdivacky MachineRegisterInfo *MRI; 58207618Srdivacky const TargetRegisterInfo *TRI; 59207618Srdivacky const TargetInstrInfo *TII; 60223017Sdim RegisterClassInfo RegClassInfo; 61207618Srdivacky 62208599Srdivacky // Basic block currently being allocated. 63208599Srdivacky MachineBasicBlock *MBB; 64208599Srdivacky 65207618Srdivacky // StackSlotForVirtReg - Maps virtual regs to the frame index where these 66207618Srdivacky // values are spilled. 67207618Srdivacky IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg; 68207618Srdivacky 69208599Srdivacky // Everything we know about a live virtual register. 70208599Srdivacky struct LiveReg { 71208599Srdivacky MachineInstr *LastUse; // Last instr to use reg. 72234353Sdim unsigned VirtReg; // Virtual register number. 73208599Srdivacky unsigned PhysReg; // Currently held here. 74208599Srdivacky unsigned short LastOpNum; // OpNum on LastUse. 75208599Srdivacky bool Dirty; // Register needs spill. 76208599Srdivacky 77234353Sdim explicit LiveReg(unsigned v) 78234353Sdim : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {} 79234353Sdim 80239462Sdim unsigned getSparseSetIndex() const { 81234353Sdim return TargetRegisterInfo::virtReg2Index(VirtReg); 82234353Sdim } 83208599Srdivacky }; 84208599Srdivacky 85234353Sdim typedef SparseSet<LiveReg> LiveRegMap; 86208599Srdivacky 87208599Srdivacky // LiveVirtRegs - This map contains entries for each virtual register 88207618Srdivacky // that is currently available in a physical register. 89208599Srdivacky LiveRegMap LiveVirtRegs; 90207618Srdivacky 91224145Sdim DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap; 92212904Sdim 93208599Srdivacky // RegState - Track the state of a physical register. 94208599Srdivacky enum RegState { 95208599Srdivacky // A disabled register is not available for allocation, but an alias may 96208599Srdivacky // be in use. A register can only be moved out of the disabled state if 97208599Srdivacky // all aliases are disabled. 98208599Srdivacky regDisabled, 99207618Srdivacky 100208599Srdivacky // A free register is not currently in use and can be allocated 101208599Srdivacky // immediately without checking aliases. 102208599Srdivacky regFree, 103207618Srdivacky 104221345Sdim // A reserved register has been assigned explicitly (e.g., setting up a 105208599Srdivacky // call parameter), and it remains reserved until it is used. 106208599Srdivacky regReserved 107208599Srdivacky 108208599Srdivacky // A register state may also be a virtual register number, indication that 109208599Srdivacky // the physical register is currently allocated to a virtual register. In 110208599Srdivacky // that case, LiveVirtRegs contains the inverse mapping. 111208599Srdivacky }; 112208599Srdivacky 113208599Srdivacky // PhysRegState - One of the RegState enums, or a virtreg. 114208599Srdivacky std::vector<unsigned> PhysRegState; 115208599Srdivacky 116249423Sdim // Set of register units. 117243830Sdim typedef SparseSet<unsigned> UsedInInstrSet; 118207618Srdivacky 119249423Sdim // Set of register units that are used in the current instruction, and so 120249423Sdim // cannot be allocated. 121243830Sdim UsedInInstrSet UsedInInstr; 122243830Sdim 123249423Sdim // Mark a physreg as used in this instruction. 124249423Sdim void markRegUsedInInstr(unsigned PhysReg) { 125249423Sdim for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 126249423Sdim UsedInInstr.insert(*Units); 127249423Sdim } 128249423Sdim 129249423Sdim // Check if a physreg or any of its aliases are used in this instruction. 130249423Sdim bool isRegUsedInInstr(unsigned PhysReg) const { 131249423Sdim for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 132249423Sdim if (UsedInInstr.count(*Units)) 133249423Sdim return true; 134249423Sdim return false; 135249423Sdim } 136249423Sdim 137212904Sdim // SkippedInstrs - Descriptors of instructions whose clobber list was 138212904Sdim // ignored because all registers were spilled. It is still necessary to 139212904Sdim // mark all the clobbered registers as used by the function. 140224145Sdim SmallPtrSet<const MCInstrDesc*, 4> SkippedInstrs; 141210299Sed 142208599Srdivacky // isBulkSpilling - This flag is set when LiveRegMap will be cleared 143208599Srdivacky // completely after spilling all live registers. LiveRegMap entries should 144208599Srdivacky // not be erased. 145208599Srdivacky bool isBulkSpilling; 146207618Srdivacky 147263508Sdim enum LLVM_ENUM_INT_TYPE(unsigned) { 148208599Srdivacky spillClean = 1, 149208599Srdivacky spillDirty = 100, 150208599Srdivacky spillImpossible = ~0u 151208599Srdivacky }; 152207618Srdivacky public: 153207618Srdivacky virtual const char *getPassName() const { 154207618Srdivacky return "Fast Register Allocator"; 155207618Srdivacky } 156207618Srdivacky 157207618Srdivacky virtual void getAnalysisUsage(AnalysisUsage &AU) const { 158207618Srdivacky AU.setPreservesCFG(); 159207618Srdivacky MachineFunctionPass::getAnalysisUsage(AU); 160207618Srdivacky } 161207618Srdivacky 162207618Srdivacky private: 163207618Srdivacky bool runOnMachineFunction(MachineFunction &Fn); 164208599Srdivacky void AllocateBasicBlock(); 165210299Sed void handleThroughOperands(MachineInstr *MI, 166210299Sed SmallVectorImpl<unsigned> &VirtDead); 167207618Srdivacky int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 168208599Srdivacky bool isLastUseOfLocalReg(MachineOperand&); 169207618Srdivacky 170208599Srdivacky void addKillFlag(const LiveReg&); 171208599Srdivacky void killVirtReg(LiveRegMap::iterator); 172208599Srdivacky void killVirtReg(unsigned VirtReg); 173208599Srdivacky void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator); 174208599Srdivacky void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 175207618Srdivacky 176208599Srdivacky void usePhysReg(MachineOperand&); 177208599Srdivacky void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 178208599Srdivacky unsigned calcSpillCost(unsigned PhysReg) const; 179234353Sdim void assignVirtToPhysReg(LiveReg&, unsigned PhysReg); 180234353Sdim LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { 181234353Sdim return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 182234353Sdim } 183234353Sdim LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { 184234353Sdim return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 185234353Sdim } 186234353Sdim LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg); 187234353Sdim LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator, 188234353Sdim unsigned Hint); 189208599Srdivacky LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, 190208599Srdivacky unsigned VirtReg, unsigned Hint); 191208599Srdivacky LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum, 192208599Srdivacky unsigned VirtReg, unsigned Hint); 193243830Sdim void spillAll(MachineBasicBlock::iterator MI); 194208599Srdivacky bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 195207618Srdivacky }; 196207618Srdivacky char RAFast::ID = 0; 197207618Srdivacky} 198207618Srdivacky 199207618Srdivacky/// getStackSpaceFor - This allocates space for the specified virtual register 200207618Srdivacky/// to be held on the stack. 201207618Srdivackyint RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { 202207618Srdivacky // Find the location Reg would belong... 203207618Srdivacky int SS = StackSlotForVirtReg[VirtReg]; 204207618Srdivacky if (SS != -1) 205207618Srdivacky return SS; // Already has space allocated? 206207618Srdivacky 207207618Srdivacky // Allocate a new stack object for this spill location... 208207618Srdivacky int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 209207618Srdivacky RC->getAlignment()); 210207618Srdivacky 211207618Srdivacky // Assign the slot. 212207618Srdivacky StackSlotForVirtReg[VirtReg] = FrameIdx; 213207618Srdivacky return FrameIdx; 214207618Srdivacky} 215207618Srdivacky 216208599Srdivacky/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to 217208599Srdivacky/// its virtual register, and it is guaranteed to be a block-local register. 218207618Srdivacky/// 219208599Srdivackybool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { 220208599Srdivacky // If the register has ever been spilled or reloaded, we conservatively assume 221208599Srdivacky // it is a global register used in multiple blocks. 222208599Srdivacky if (StackSlotForVirtReg[MO.getReg()] != -1) 223208599Srdivacky return false; 224207618Srdivacky 225208599Srdivacky // Check that the use/def chain has exactly one operand - MO. 226239462Sdim MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg()); 227239462Sdim if (&I.getOperand() != &MO) 228239462Sdim return false; 229239462Sdim return ++I == MRI->reg_nodbg_end(); 230208599Srdivacky} 231207618Srdivacky 232208599Srdivacky/// addKillFlag - Set kill flags on last use of a virtual register. 233208599Srdivackyvoid RAFast::addKillFlag(const LiveReg &LR) { 234208599Srdivacky if (!LR.LastUse) return; 235208599Srdivacky MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); 236208599Srdivacky if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { 237208599Srdivacky if (MO.getReg() == LR.PhysReg) 238208599Srdivacky MO.setIsKill(); 239208599Srdivacky else 240208599Srdivacky LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 241207618Srdivacky } 242208599Srdivacky} 243207618Srdivacky 244208599Srdivacky/// killVirtReg - Mark virtreg as no longer available. 245208599Srdivackyvoid RAFast::killVirtReg(LiveRegMap::iterator LRI) { 246234353Sdim addKillFlag(*LRI); 247234353Sdim assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg && 248234353Sdim "Broken RegState mapping"); 249234353Sdim PhysRegState[LRI->PhysReg] = regFree; 250208599Srdivacky // Erase from LiveVirtRegs unless we're spilling in bulk. 251208599Srdivacky if (!isBulkSpilling) 252208599Srdivacky LiveVirtRegs.erase(LRI); 253208599Srdivacky} 254207618Srdivacky 255208599Srdivacky/// killVirtReg - Mark virtreg as no longer available. 256208599Srdivackyvoid RAFast::killVirtReg(unsigned VirtReg) { 257208599Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 258208599Srdivacky "killVirtReg needs a virtual register"); 259234353Sdim LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); 260208599Srdivacky if (LRI != LiveVirtRegs.end()) 261208599Srdivacky killVirtReg(LRI); 262207618Srdivacky} 263207618Srdivacky 264208599Srdivacky/// spillVirtReg - This method spills the value specified by VirtReg into the 265212904Sdim/// corresponding stack slot if needed. 266208599Srdivackyvoid RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { 267208599Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 268208599Srdivacky "Spilling a physical register is illegal!"); 269234353Sdim LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); 270208599Srdivacky assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register"); 271208599Srdivacky spillVirtReg(MI, LRI); 272208599Srdivacky} 273207618Srdivacky 274208599Srdivacky/// spillVirtReg - Do the actual work of spilling. 275208599Srdivackyvoid RAFast::spillVirtReg(MachineBasicBlock::iterator MI, 276208599Srdivacky LiveRegMap::iterator LRI) { 277234353Sdim LiveReg &LR = *LRI; 278234353Sdim assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); 279207618Srdivacky 280208599Srdivacky if (LR.Dirty) { 281208599Srdivacky // If this physreg is used by the instruction, we want to kill it on the 282208599Srdivacky // instruction, not on the spill. 283208599Srdivacky bool SpillKill = LR.LastUse != MI; 284208599Srdivacky LR.Dirty = false; 285234353Sdim DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) 286218893Sdim << " in " << PrintReg(LR.PhysReg, TRI)); 287234353Sdim const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg); 288234353Sdim int FI = getStackSpaceFor(LRI->VirtReg, RC); 289208599Srdivacky DEBUG(dbgs() << " to stack slot #" << FI << "\n"); 290208599Srdivacky TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); 291208599Srdivacky ++NumStores; // Update statistics 292207618Srdivacky 293212904Sdim // If this register is used by DBG_VALUE then insert new DBG_VALUE to 294212904Sdim // identify spilled location as the place to find corresponding variable's 295212904Sdim // value. 296263508Sdim SmallVectorImpl<MachineInstr *> &LRIDbgValues = 297234353Sdim LiveDbgValueMap[LRI->VirtReg]; 298224145Sdim for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) { 299224145Sdim MachineInstr *DBG = LRIDbgValues[li]; 300263508Sdim const MDNode *MDPtr = DBG->getOperand(2).getMetadata(); 301263508Sdim bool IsIndirect = DBG->isIndirectDebugValue(); 302263508Sdim uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0; 303212904Sdim DebugLoc DL; 304212904Sdim if (MI == MBB->end()) { 305212904Sdim // If MI is at basic block end then use last instruction's location. 306212904Sdim MachineBasicBlock::iterator EI = MI; 307212904Sdim DL = (--EI)->getDebugLoc(); 308263508Sdim } else 309212904Sdim DL = MI->getDebugLoc(); 310263508Sdim MachineBasicBlock *MBB = DBG->getParent(); 311263508Sdim MachineInstr *NewDV = 312263508Sdim BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE)) 313263508Sdim .addFrameIndex(FI).addImm(Offset).addMetadata(MDPtr); 314263508Sdim (void)NewDV; 315263508Sdim DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV); 316212904Sdim } 317234353Sdim // Now this register is spilled there is should not be any DBG_VALUE 318234353Sdim // pointing to this register because they are all pointing to spilled value 319234353Sdim // now. 320224145Sdim LRIDbgValues.clear(); 321208599Srdivacky if (SpillKill) 322208599Srdivacky LR.LastUse = 0; // Don't kill register again 323207618Srdivacky } 324208599Srdivacky killVirtReg(LRI); 325207618Srdivacky} 326207618Srdivacky 327208599Srdivacky/// spillAll - Spill all dirty virtregs without killing them. 328243830Sdimvoid RAFast::spillAll(MachineBasicBlock::iterator MI) { 329208599Srdivacky if (LiveVirtRegs.empty()) return; 330208599Srdivacky isBulkSpilling = true; 331208599Srdivacky // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order 332208599Srdivacky // of spilling here is deterministic, if arbitrary. 333208599Srdivacky for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); 334208599Srdivacky i != e; ++i) 335208599Srdivacky spillVirtReg(MI, i); 336208599Srdivacky LiveVirtRegs.clear(); 337208599Srdivacky isBulkSpilling = false; 338207618Srdivacky} 339207618Srdivacky 340208599Srdivacky/// usePhysReg - Handle the direct use of a physical register. 341208599Srdivacky/// Check that the register is not used by a virtreg. 342208599Srdivacky/// Kill the physreg, marking it free. 343208599Srdivacky/// This may add implicit kills to MO->getParent() and invalidate MO. 344208599Srdivackyvoid RAFast::usePhysReg(MachineOperand &MO) { 345208599Srdivacky unsigned PhysReg = MO.getReg(); 346208599Srdivacky assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && 347208599Srdivacky "Bad usePhysReg operand"); 348249423Sdim markRegUsedInInstr(PhysReg); 349208599Srdivacky switch (PhysRegState[PhysReg]) { 350208599Srdivacky case regDisabled: 351208599Srdivacky break; 352208599Srdivacky case regReserved: 353208599Srdivacky PhysRegState[PhysReg] = regFree; 354208599Srdivacky // Fall through 355208599Srdivacky case regFree: 356208599Srdivacky MO.setIsKill(); 357208599Srdivacky return; 358208599Srdivacky default: 359218893Sdim // The physreg was allocated to a virtual register. That means the value we 360208599Srdivacky // wanted has been clobbered. 361208599Srdivacky llvm_unreachable("Instruction uses an allocated register"); 362208599Srdivacky } 363207618Srdivacky 364208599Srdivacky // Maybe a superregister is reserved? 365239462Sdim for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { 366239462Sdim unsigned Alias = *AI; 367208599Srdivacky switch (PhysRegState[Alias]) { 368208599Srdivacky case regDisabled: 369208599Srdivacky break; 370208599Srdivacky case regReserved: 371208599Srdivacky assert(TRI->isSuperRegister(PhysReg, Alias) && 372208599Srdivacky "Instruction is not using a subregister of a reserved register"); 373208599Srdivacky // Leave the superregister in the working set. 374208599Srdivacky PhysRegState[Alias] = regFree; 375208599Srdivacky MO.getParent()->addRegisterKilled(Alias, TRI, true); 376208599Srdivacky return; 377208599Srdivacky case regFree: 378208599Srdivacky if (TRI->isSuperRegister(PhysReg, Alias)) { 379208599Srdivacky // Leave the superregister in the working set. 380208599Srdivacky MO.getParent()->addRegisterKilled(Alias, TRI, true); 381208599Srdivacky return; 382208599Srdivacky } 383208599Srdivacky // Some other alias was in the working set - clear it. 384208599Srdivacky PhysRegState[Alias] = regDisabled; 385208599Srdivacky break; 386208599Srdivacky default: 387208599Srdivacky llvm_unreachable("Instruction uses an alias of an allocated register"); 388208599Srdivacky } 389208599Srdivacky } 390208599Srdivacky 391208599Srdivacky // All aliases are disabled, bring register into working set. 392208599Srdivacky PhysRegState[PhysReg] = regFree; 393208599Srdivacky MO.setIsKill(); 394207618Srdivacky} 395207618Srdivacky 396208599Srdivacky/// definePhysReg - Mark PhysReg as reserved or free after spilling any 397208599Srdivacky/// virtregs. This is very similar to defineVirtReg except the physreg is 398208599Srdivacky/// reserved instead of allocated. 399208599Srdivackyvoid RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg, 400208599Srdivacky RegState NewState) { 401249423Sdim markRegUsedInInstr(PhysReg); 402208599Srdivacky switch (unsigned VirtReg = PhysRegState[PhysReg]) { 403208599Srdivacky case regDisabled: 404208599Srdivacky break; 405208599Srdivacky default: 406208599Srdivacky spillVirtReg(MI, VirtReg); 407208599Srdivacky // Fall through. 408208599Srdivacky case regFree: 409208599Srdivacky case regReserved: 410208599Srdivacky PhysRegState[PhysReg] = NewState; 411208599Srdivacky return; 412208599Srdivacky } 413207618Srdivacky 414208599Srdivacky // This is a disabled register, disable all aliases. 415208599Srdivacky PhysRegState[PhysReg] = NewState; 416239462Sdim for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { 417239462Sdim unsigned Alias = *AI; 418208599Srdivacky switch (unsigned VirtReg = PhysRegState[Alias]) { 419208599Srdivacky case regDisabled: 420208599Srdivacky break; 421208599Srdivacky default: 422208599Srdivacky spillVirtReg(MI, VirtReg); 423208599Srdivacky // Fall through. 424208599Srdivacky case regFree: 425208599Srdivacky case regReserved: 426208599Srdivacky PhysRegState[Alias] = regDisabled; 427208599Srdivacky if (TRI->isSuperRegister(PhysReg, Alias)) 428208599Srdivacky return; 429208599Srdivacky break; 430208599Srdivacky } 431208599Srdivacky } 432207618Srdivacky} 433207618Srdivacky 434207618Srdivacky 435208599Srdivacky// calcSpillCost - Return the cost of spilling clearing out PhysReg and 436208599Srdivacky// aliases so it is free for allocation. 437208599Srdivacky// Returns 0 when PhysReg is free or disabled with all aliases disabled - it 438208599Srdivacky// can be allocated directly. 439208599Srdivacky// Returns spillImpossible when PhysReg or an alias can't be spilled. 440208599Srdivackyunsigned RAFast::calcSpillCost(unsigned PhysReg) const { 441249423Sdim if (isRegUsedInInstr(PhysReg)) { 442224145Sdim DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); 443208599Srdivacky return spillImpossible; 444221345Sdim } 445208599Srdivacky switch (unsigned VirtReg = PhysRegState[PhysReg]) { 446208599Srdivacky case regDisabled: 447208599Srdivacky break; 448208599Srdivacky case regFree: 449208599Srdivacky return 0; 450208599Srdivacky case regReserved: 451224145Sdim DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " 452224145Sdim << PrintReg(PhysReg, TRI) << " is reserved already.\n"); 453208599Srdivacky return spillImpossible; 454234353Sdim default: { 455234353Sdim LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); 456234353Sdim assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); 457234353Sdim return I->Dirty ? spillDirty : spillClean; 458208599Srdivacky } 459234353Sdim } 460207618Srdivacky 461221345Sdim // This is a disabled register, add up cost of aliases. 462224145Sdim DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); 463208599Srdivacky unsigned Cost = 0; 464239462Sdim for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { 465239462Sdim unsigned Alias = *AI; 466208599Srdivacky switch (unsigned VirtReg = PhysRegState[Alias]) { 467208599Srdivacky case regDisabled: 468208599Srdivacky break; 469208599Srdivacky case regFree: 470208599Srdivacky ++Cost; 471208599Srdivacky break; 472208599Srdivacky case regReserved: 473208599Srdivacky return spillImpossible; 474234353Sdim default: { 475234353Sdim LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); 476234353Sdim assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); 477234353Sdim Cost += I->Dirty ? spillDirty : spillClean; 478208599Srdivacky break; 479207618Srdivacky } 480234353Sdim } 481208599Srdivacky } 482208599Srdivacky return Cost; 483207618Srdivacky} 484207618Srdivacky 485207618Srdivacky 486208599Srdivacky/// assignVirtToPhysReg - This method updates local state so that we know 487208599Srdivacky/// that PhysReg is the proper container for VirtReg now. The physical 488208599Srdivacky/// register must not be used for anything else when this is called. 489207618Srdivacky/// 490234353Sdimvoid RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) { 491234353Sdim DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to " 492218893Sdim << PrintReg(PhysReg, TRI) << "\n"); 493234353Sdim PhysRegState[PhysReg] = LR.VirtReg; 494234353Sdim assert(!LR.PhysReg && "Already assigned a physreg"); 495234353Sdim LR.PhysReg = PhysReg; 496208599Srdivacky} 497207618Srdivacky 498234353SdimRAFast::LiveRegMap::iterator 499234353SdimRAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { 500234353Sdim LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); 501234353Sdim assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared"); 502234353Sdim assignVirtToPhysReg(*LRI, PhysReg); 503234353Sdim return LRI; 504234353Sdim} 505234353Sdim 506208599Srdivacky/// allocVirtReg - Allocate a physical register for VirtReg. 507234353SdimRAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI, 508234353Sdim LiveRegMap::iterator LRI, 509234353Sdim unsigned Hint) { 510234353Sdim const unsigned VirtReg = LRI->VirtReg; 511207618Srdivacky 512208599Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 513208599Srdivacky "Can only allocate virtual registers"); 514207618Srdivacky 515208599Srdivacky const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 516207618Srdivacky 517208599Srdivacky // Ignore invalid hints. 518208599Srdivacky if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || 519243830Sdim !RC->contains(Hint) || !MRI->isAllocatable(Hint))) 520208599Srdivacky Hint = 0; 521208599Srdivacky 522208599Srdivacky // Take hint when possible. 523208599Srdivacky if (Hint) { 524224145Sdim // Ignore the hint if we would have to spill a dirty register. 525224145Sdim unsigned Cost = calcSpillCost(Hint); 526224145Sdim if (Cost < spillDirty) { 527224145Sdim if (Cost) 528224145Sdim definePhysReg(MI, Hint, regFree); 529234353Sdim // definePhysReg may kill virtual registers and modify LiveVirtRegs. 530234353Sdim // That invalidates LRI, so run a new lookup for VirtReg. 531234353Sdim return assignVirtToPhysReg(VirtReg, Hint); 532207618Srdivacky } 533208599Srdivacky } 534207618Srdivacky 535249423Sdim ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC); 536207618Srdivacky 537208599Srdivacky // First try to find a completely free register. 538249423Sdim for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){ 539208599Srdivacky unsigned PhysReg = *I; 540249423Sdim if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) { 541234353Sdim assignVirtToPhysReg(*LRI, PhysReg); 542234353Sdim return LRI; 543234353Sdim } 544208599Srdivacky } 545207618Srdivacky 546218893Sdim DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " 547218893Sdim << RC->getName() << "\n"); 548207618Srdivacky 549208599Srdivacky unsigned BestReg = 0, BestCost = spillImpossible; 550249423Sdim for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){ 551208599Srdivacky unsigned Cost = calcSpillCost(*I); 552224145Sdim DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); 553221345Sdim DEBUG(dbgs() << "\tCost: " << Cost << "\n"); 554221345Sdim DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); 555208599Srdivacky // Cost is 0 when all aliases are already disabled. 556234353Sdim if (Cost == 0) { 557234353Sdim assignVirtToPhysReg(*LRI, *I); 558234353Sdim return LRI; 559234353Sdim } 560208599Srdivacky if (Cost < BestCost) 561208599Srdivacky BestReg = *I, BestCost = Cost; 562207618Srdivacky } 563207618Srdivacky 564208599Srdivacky if (BestReg) { 565208599Srdivacky definePhysReg(MI, BestReg, regFree); 566234353Sdim // definePhysReg may kill virtual registers and modify LiveVirtRegs. 567234353Sdim // That invalidates LRI, so run a new lookup for VirtReg. 568234353Sdim return assignVirtToPhysReg(VirtReg, BestReg); 569208599Srdivacky } 570207618Srdivacky 571224145Sdim // Nothing we can do. Report an error and keep going with a bad allocation. 572263508Sdim if (MI->isInlineAsm()) 573263508Sdim MI->emitError("inline assembly requires more registers than available"); 574263508Sdim else 575263508Sdim MI->emitError("ran out of registers during register allocation"); 576224145Sdim definePhysReg(MI, *AO.begin(), regFree); 577234353Sdim return assignVirtToPhysReg(VirtReg, *AO.begin()); 578208599Srdivacky} 579207618Srdivacky 580208599Srdivacky/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty. 581208599SrdivackyRAFast::LiveRegMap::iterator 582208599SrdivackyRAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, 583208599Srdivacky unsigned VirtReg, unsigned Hint) { 584208599Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 585208599Srdivacky "Not a virtual register"); 586208599Srdivacky LiveRegMap::iterator LRI; 587208599Srdivacky bool New; 588234353Sdim tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); 589208599Srdivacky if (New) { 590208599Srdivacky // If there is no hint, peek at the only use of this register. 591208599Srdivacky if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) && 592208599Srdivacky MRI->hasOneNonDBGUse(VirtReg)) { 593210299Sed const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg); 594208599Srdivacky // It's a copy, use the destination register as a hint. 595210299Sed if (UseMI.isCopyLike()) 596210299Sed Hint = UseMI.getOperand(0).getReg(); 597207618Srdivacky } 598234353Sdim LRI = allocVirtReg(MI, LRI, Hint); 599234353Sdim } else if (LRI->LastUse) { 600208599Srdivacky // Redefining a live register - kill at the last use, unless it is this 601208599Srdivacky // instruction defining VirtReg multiple times. 602234353Sdim if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) 603234353Sdim addKillFlag(*LRI); 604207618Srdivacky } 605234353Sdim assert(LRI->PhysReg && "Register not assigned"); 606234353Sdim LRI->LastUse = MI; 607234353Sdim LRI->LastOpNum = OpNum; 608234353Sdim LRI->Dirty = true; 609249423Sdim markRegUsedInInstr(LRI->PhysReg); 610208599Srdivacky return LRI; 611208599Srdivacky} 612207618Srdivacky 613208599Srdivacky/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it. 614208599SrdivackyRAFast::LiveRegMap::iterator 615208599SrdivackyRAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, 616208599Srdivacky unsigned VirtReg, unsigned Hint) { 617208599Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 618208599Srdivacky "Not a virtual register"); 619208599Srdivacky LiveRegMap::iterator LRI; 620208599Srdivacky bool New; 621234353Sdim tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); 622208599Srdivacky MachineOperand &MO = MI->getOperand(OpNum); 623208599Srdivacky if (New) { 624234353Sdim LRI = allocVirtReg(MI, LRI, Hint); 625208599Srdivacky const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 626208599Srdivacky int FrameIndex = getStackSpaceFor(VirtReg, RC); 627218893Sdim DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " 628234353Sdim << PrintReg(LRI->PhysReg, TRI) << "\n"); 629234353Sdim TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI); 630208599Srdivacky ++NumLoads; 631234353Sdim } else if (LRI->Dirty) { 632208599Srdivacky if (isLastUseOfLocalReg(MO)) { 633208599Srdivacky DEBUG(dbgs() << "Killing last use: " << MO << "\n"); 634210299Sed if (MO.isUse()) 635210299Sed MO.setIsKill(); 636210299Sed else 637210299Sed MO.setIsDead(); 638208599Srdivacky } else if (MO.isKill()) { 639208599Srdivacky DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n"); 640208599Srdivacky MO.setIsKill(false); 641210299Sed } else if (MO.isDead()) { 642210299Sed DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); 643210299Sed MO.setIsDead(false); 644207618Srdivacky } 645208599Srdivacky } else if (MO.isKill()) { 646208599Srdivacky // We must remove kill flags from uses of reloaded registers because the 647208599Srdivacky // register would be killed immediately, and there might be a second use: 648208599Srdivacky // %foo = OR %x<kill>, %x 649208599Srdivacky // This would cause a second reload of %x into a different register. 650208599Srdivacky DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); 651208599Srdivacky MO.setIsKill(false); 652210299Sed } else if (MO.isDead()) { 653210299Sed DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); 654210299Sed MO.setIsDead(false); 655207618Srdivacky } 656234353Sdim assert(LRI->PhysReg && "Register not assigned"); 657234353Sdim LRI->LastUse = MI; 658234353Sdim LRI->LastOpNum = OpNum; 659249423Sdim markRegUsedInInstr(LRI->PhysReg); 660208599Srdivacky return LRI; 661207618Srdivacky} 662207618Srdivacky 663208599Srdivacky// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering 664208599Srdivacky// subregs. This may invalidate any operand pointers. 665208599Srdivacky// Return true if the operand kills its register. 666208599Srdivackybool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { 667208599Srdivacky MachineOperand &MO = MI->getOperand(OpNum); 668239462Sdim bool Dead = MO.isDead(); 669208599Srdivacky if (!MO.getSubReg()) { 670208599Srdivacky MO.setReg(PhysReg); 671239462Sdim return MO.isKill() || Dead; 672207618Srdivacky } 673207618Srdivacky 674208599Srdivacky // Handle subregister index. 675208599Srdivacky MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); 676208599Srdivacky MO.setSubReg(0); 677208599Srdivacky 678208599Srdivacky // A kill flag implies killing the full register. Add corresponding super 679208599Srdivacky // register kill. 680208599Srdivacky if (MO.isKill()) { 681208599Srdivacky MI->addRegisterKilled(PhysReg, TRI, true); 682208599Srdivacky return true; 683207618Srdivacky } 684239462Sdim 685239462Sdim // A <def,read-undef> of a sub-register requires an implicit def of the full 686239462Sdim // register. 687239462Sdim if (MO.isDef() && MO.isUndef()) 688239462Sdim MI->addRegisterDefined(PhysReg, TRI); 689239462Sdim 690239462Sdim return Dead; 691207618Srdivacky} 692207618Srdivacky 693210299Sed// Handle special instruction operand like early clobbers and tied ops when 694210299Sed// there are additional physreg defines. 695210299Sedvoid RAFast::handleThroughOperands(MachineInstr *MI, 696210299Sed SmallVectorImpl<unsigned> &VirtDead) { 697210299Sed DEBUG(dbgs() << "Scanning for through registers:"); 698210299Sed SmallSet<unsigned, 8> ThroughRegs; 699210299Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 700210299Sed MachineOperand &MO = MI->getOperand(i); 701210299Sed if (!MO.isReg()) continue; 702210299Sed unsigned Reg = MO.getReg(); 703218893Sdim if (!TargetRegisterInfo::isVirtualRegister(Reg)) 704218893Sdim continue; 705210299Sed if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) || 706210299Sed (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 707210299Sed if (ThroughRegs.insert(Reg)) 708218893Sdim DEBUG(dbgs() << ' ' << PrintReg(Reg)); 709210299Sed } 710210299Sed } 711210299Sed 712210299Sed // If any physreg defines collide with preallocated through registers, 713210299Sed // we must spill and reallocate. 714210299Sed DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); 715210299Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 716210299Sed MachineOperand &MO = MI->getOperand(i); 717210299Sed if (!MO.isReg() || !MO.isDef()) continue; 718210299Sed unsigned Reg = MO.getReg(); 719210299Sed if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 720249423Sdim markRegUsedInInstr(Reg); 721239462Sdim for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 722239462Sdim if (ThroughRegs.count(PhysRegState[*AI])) 723239462Sdim definePhysReg(MI, *AI, regFree); 724210299Sed } 725210299Sed } 726210299Sed 727210299Sed SmallVector<unsigned, 8> PartialDefs; 728234353Sdim DEBUG(dbgs() << "Allocating tied uses.\n"); 729210299Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 730210299Sed MachineOperand &MO = MI->getOperand(i); 731210299Sed if (!MO.isReg()) continue; 732210299Sed unsigned Reg = MO.getReg(); 733218893Sdim if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 734210299Sed if (MO.isUse()) { 735210299Sed unsigned DefIdx = 0; 736210299Sed if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 737210299Sed DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand " 738210299Sed << DefIdx << ".\n"); 739210299Sed LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 740234353Sdim unsigned PhysReg = LRI->PhysReg; 741210299Sed setPhysReg(MI, i, PhysReg); 742210299Sed // Note: we don't update the def operand yet. That would cause the normal 743210299Sed // def-scan to attempt spilling. 744210299Sed } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { 745210299Sed DEBUG(dbgs() << "Partial redefine: " << MO << "\n"); 746210299Sed // Reload the register, but don't assign to the operand just yet. 747210299Sed // That would confuse the later phys-def processing pass. 748210299Sed LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 749234353Sdim PartialDefs.push_back(LRI->PhysReg); 750210299Sed } 751210299Sed } 752210299Sed 753234353Sdim DEBUG(dbgs() << "Allocating early clobbers.\n"); 754234353Sdim for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 755234353Sdim MachineOperand &MO = MI->getOperand(i); 756234353Sdim if (!MO.isReg()) continue; 757234353Sdim unsigned Reg = MO.getReg(); 758234353Sdim if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 759234353Sdim if (!MO.isEarlyClobber()) 760234353Sdim continue; 761234353Sdim // Note: defineVirtReg may invalidate MO. 762234353Sdim LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0); 763234353Sdim unsigned PhysReg = LRI->PhysReg; 764234353Sdim if (setPhysReg(MI, i, PhysReg)) 765234353Sdim VirtDead.push_back(Reg); 766234353Sdim } 767234353Sdim 768210299Sed // Restore UsedInInstr to a state usable for allocating normal virtual uses. 769243830Sdim UsedInInstr.clear(); 770210299Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 771210299Sed MachineOperand &MO = MI->getOperand(i); 772210299Sed if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; 773210299Sed unsigned Reg = MO.getReg(); 774210299Sed if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 775224145Sdim DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) 776224145Sdim << " as used in instr\n"); 777249423Sdim markRegUsedInInstr(Reg); 778210299Sed } 779210299Sed 780210299Sed // Also mark PartialDefs as used to avoid reallocation. 781210299Sed for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i) 782249423Sdim markRegUsedInInstr(PartialDefs[i]); 783210299Sed} 784210299Sed 785234353Sdimvoid RAFast::AllocateBasicBlock() { 786234353Sdim DEBUG(dbgs() << "\nAllocating " << *MBB); 787234353Sdim 788208599Srdivacky PhysRegState.assign(TRI->getNumRegs(), regDisabled); 789234353Sdim assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?"); 790207618Srdivacky 791208599Srdivacky MachineBasicBlock::iterator MII = MBB->begin(); 792207618Srdivacky 793208599Srdivacky // Add live-in registers as live. 794208599Srdivacky for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 795208599Srdivacky E = MBB->livein_end(); I != E; ++I) 796243830Sdim if (MRI->isAllocatable(*I)) 797212904Sdim definePhysReg(MII, *I, regReserved); 798208599Srdivacky 799210299Sed SmallVector<unsigned, 8> VirtDead; 800208599Srdivacky SmallVector<MachineInstr*, 32> Coalesced; 801208599Srdivacky 802207618Srdivacky // Otherwise, sequentially allocate each instruction in the MBB. 803208599Srdivacky while (MII != MBB->end()) { 804207618Srdivacky MachineInstr *MI = MII++; 805224145Sdim const MCInstrDesc &MCID = MI->getDesc(); 806207618Srdivacky DEBUG({ 807208599Srdivacky dbgs() << "\n>> " << *MI << "Regs:"; 808208599Srdivacky for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { 809208599Srdivacky if (PhysRegState[Reg] == regDisabled) continue; 810208599Srdivacky dbgs() << " " << TRI->getName(Reg); 811208599Srdivacky switch(PhysRegState[Reg]) { 812208599Srdivacky case regFree: 813208599Srdivacky break; 814208599Srdivacky case regReserved: 815208599Srdivacky dbgs() << "*"; 816208599Srdivacky break; 817234353Sdim default: { 818218893Sdim dbgs() << '=' << PrintReg(PhysRegState[Reg]); 819234353Sdim LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]); 820234353Sdim assert(I != LiveVirtRegs.end() && "Missing VirtReg entry"); 821234353Sdim if (I->Dirty) 822208599Srdivacky dbgs() << "*"; 823234353Sdim assert(I->PhysReg == Reg && "Bad inverse map"); 824208599Srdivacky break; 825208599Srdivacky } 826234353Sdim } 827208599Srdivacky } 828207618Srdivacky dbgs() << '\n'; 829208599Srdivacky // Check that LiveVirtRegs is the inverse. 830208599Srdivacky for (LiveRegMap::iterator i = LiveVirtRegs.begin(), 831208599Srdivacky e = LiveVirtRegs.end(); i != e; ++i) { 832234353Sdim assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) && 833208599Srdivacky "Bad map key"); 834234353Sdim assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) && 835208599Srdivacky "Bad map value"); 836234353Sdim assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map"); 837208599Srdivacky } 838207618Srdivacky }); 839207618Srdivacky 840208599Srdivacky // Debug values are not allowed to change codegen in any way. 841208599Srdivacky if (MI->isDebugValue()) { 842212904Sdim bool ScanDbgValue = true; 843212904Sdim while (ScanDbgValue) { 844212904Sdim ScanDbgValue = false; 845212904Sdim for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 846212904Sdim MachineOperand &MO = MI->getOperand(i); 847212904Sdim if (!MO.isReg()) continue; 848212904Sdim unsigned Reg = MO.getReg(); 849218893Sdim if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 850234353Sdim LiveRegMap::iterator LRI = findLiveVirtReg(Reg); 851212904Sdim if (LRI != LiveVirtRegs.end()) 852234353Sdim setPhysReg(MI, i, LRI->PhysReg); 853210299Sed else { 854212904Sdim int SS = StackSlotForVirtReg[Reg]; 855218893Sdim if (SS == -1) { 856212904Sdim // We can't allocate a physreg for a DebugValue, sorry! 857218893Sdim DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); 858212904Sdim MO.setReg(0); 859218893Sdim } 860212904Sdim else { 861212904Sdim // Modify DBG_VALUE now that the value is in a spill slot. 862263508Sdim bool IsIndirect = MI->isIndirectDebugValue(); 863263508Sdim uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 864212904Sdim const MDNode *MDPtr = 865212904Sdim MI->getOperand(MI->getNumOperands()-1).getMetadata(); 866212904Sdim DebugLoc DL = MI->getDebugLoc(); 867263508Sdim MachineBasicBlock *MBB = MI->getParent(); 868263508Sdim MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL, 869263508Sdim TII->get(TargetOpcode::DBG_VALUE)) 870263508Sdim .addFrameIndex(SS).addImm(Offset).addMetadata(MDPtr); 871263508Sdim DEBUG(dbgs() << "Modifying debug info due to spill:" 872263508Sdim << "\t" << *NewDV); 873263508Sdim // Scan NewDV operands from the beginning. 874263508Sdim MI = NewDV; 875263508Sdim ScanDbgValue = true; 876263508Sdim break; 877212904Sdim } 878210299Sed } 879234353Sdim LiveDbgValueMap[Reg].push_back(MI); 880210299Sed } 881207618Srdivacky } 882208599Srdivacky // Next instruction. 883208599Srdivacky continue; 884207618Srdivacky } 885207618Srdivacky 886208599Srdivacky // If this is a copy, we may be able to coalesce. 887212904Sdim unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0; 888210299Sed if (MI->isCopy()) { 889210299Sed CopyDst = MI->getOperand(0).getReg(); 890210299Sed CopySrc = MI->getOperand(1).getReg(); 891210299Sed CopyDstSub = MI->getOperand(0).getSubReg(); 892210299Sed CopySrcSub = MI->getOperand(1).getSubReg(); 893212904Sdim } 894207618Srdivacky 895208599Srdivacky // Track registers used by instruction. 896243830Sdim UsedInInstr.clear(); 897208599Srdivacky 898208599Srdivacky // First scan. 899208599Srdivacky // Mark physreg uses and early clobbers as used. 900208599Srdivacky // Find the end of the virtreg operands 901208599Srdivacky unsigned VirtOpEnd = 0; 902210299Sed bool hasTiedOps = false; 903210299Sed bool hasEarlyClobbers = false; 904210299Sed bool hasPartialRedefs = false; 905210299Sed bool hasPhysDefs = false; 906208599Srdivacky for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 907207618Srdivacky MachineOperand &MO = MI->getOperand(i); 908243830Sdim // Make sure MRI knows about registers clobbered by regmasks. 909243830Sdim if (MO.isRegMask()) { 910243830Sdim MRI->addPhysRegsUsedFromRegMask(MO.getRegMask()); 911243830Sdim continue; 912243830Sdim } 913208599Srdivacky if (!MO.isReg()) continue; 914208599Srdivacky unsigned Reg = MO.getReg(); 915208599Srdivacky if (!Reg) continue; 916208599Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) { 917208599Srdivacky VirtOpEnd = i+1; 918210299Sed if (MO.isUse()) { 919210299Sed hasTiedOps = hasTiedOps || 920224145Sdim MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; 921210299Sed } else { 922210299Sed if (MO.isEarlyClobber()) 923210299Sed hasEarlyClobbers = true; 924210299Sed if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) 925210299Sed hasPartialRedefs = true; 926210299Sed } 927207618Srdivacky continue; 928207618Srdivacky } 929243830Sdim if (!MRI->isAllocatable(Reg)) continue; 930208599Srdivacky if (MO.isUse()) { 931208599Srdivacky usePhysReg(MO); 932208599Srdivacky } else if (MO.isEarlyClobber()) { 933210299Sed definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 934210299Sed regFree : regReserved); 935210299Sed hasEarlyClobbers = true; 936210299Sed } else 937210299Sed hasPhysDefs = true; 938207618Srdivacky } 939207618Srdivacky 940210299Sed // The instruction may have virtual register operands that must be allocated 941210299Sed // the same register at use-time and def-time: early clobbers and tied 942210299Sed // operands. If there are also physical defs, these registers must avoid 943210299Sed // both physical defs and uses, making them more constrained than normal 944210299Sed // operands. 945212904Sdim // Similarly, if there are multiple defs and tied operands, we must make 946212904Sdim // sure the same register is allocated to uses and defs. 947210299Sed // We didn't detect inline asm tied operands above, so just make this extra 948210299Sed // pass for all inline asm. 949210299Sed if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || 950224145Sdim (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { 951210299Sed handleThroughOperands(MI, VirtDead); 952210299Sed // Don't attempt coalescing when we have funny stuff going on. 953210299Sed CopyDst = 0; 954212904Sdim // Pretend we have early clobbers so the use operands get marked below. 955212904Sdim // This is not necessary for the common case of a single tied use. 956212904Sdim hasEarlyClobbers = true; 957210299Sed } 958210299Sed 959208599Srdivacky // Second scan. 960210299Sed // Allocate virtreg uses. 961208599Srdivacky for (unsigned i = 0; i != VirtOpEnd; ++i) { 962207618Srdivacky MachineOperand &MO = MI->getOperand(i); 963208599Srdivacky if (!MO.isReg()) continue; 964207618Srdivacky unsigned Reg = MO.getReg(); 965218893Sdim if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 966208599Srdivacky if (MO.isUse()) { 967208599Srdivacky LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst); 968234353Sdim unsigned PhysReg = LRI->PhysReg; 969208599Srdivacky CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0; 970208599Srdivacky if (setPhysReg(MI, i, PhysReg)) 971208599Srdivacky killVirtReg(LRI); 972207618Srdivacky } 973207618Srdivacky } 974207618Srdivacky 975243830Sdim for (UsedInInstrSet::iterator 976243830Sdim I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I) 977249423Sdim MRI->setRegUnitUsed(*I); 978207618Srdivacky 979212904Sdim // Track registers defined by instruction - early clobbers and tied uses at 980212904Sdim // this point. 981243830Sdim UsedInInstr.clear(); 982210299Sed if (hasEarlyClobbers) { 983210299Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 984210299Sed MachineOperand &MO = MI->getOperand(i); 985212904Sdim if (!MO.isReg()) continue; 986210299Sed unsigned Reg = MO.getReg(); 987210299Sed if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 988212904Sdim // Look for physreg defs and tied uses. 989212904Sdim if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue; 990249423Sdim markRegUsedInInstr(Reg); 991210299Sed } 992207618Srdivacky } 993207618Srdivacky 994208599Srdivacky unsigned DefOpEnd = MI->getNumOperands(); 995234353Sdim if (MI->isCall()) { 996208599Srdivacky // Spill all virtregs before a call. This serves two purposes: 1. If an 997212904Sdim // exception is thrown, the landing pad is going to expect to find 998212904Sdim // registers in their spill slots, and 2. we don't have to wade through 999212904Sdim // all the <imp-def> operands on the call instruction. 1000208599Srdivacky DefOpEnd = VirtOpEnd; 1001208599Srdivacky DEBUG(dbgs() << " Spilling remaining registers before call.\n"); 1002208599Srdivacky spillAll(MI); 1003210299Sed 1004210299Sed // The imp-defs are skipped below, but we still need to mark those 1005210299Sed // registers as used by the function. 1006224145Sdim SkippedInstrs.insert(&MCID); 1007207618Srdivacky } 1008207618Srdivacky 1009208599Srdivacky // Third scan. 1010208599Srdivacky // Allocate defs and collect dead defs. 1011208599Srdivacky for (unsigned i = 0; i != DefOpEnd; ++i) { 1012207618Srdivacky MachineOperand &MO = MI->getOperand(i); 1013210299Sed if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) 1014210299Sed continue; 1015208599Srdivacky unsigned Reg = MO.getReg(); 1016208599Srdivacky 1017208599Srdivacky if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1018243830Sdim if (!MRI->isAllocatable(Reg)) continue; 1019208599Srdivacky definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 1020208599Srdivacky regFree : regReserved); 1021207618Srdivacky continue; 1022207618Srdivacky } 1023208599Srdivacky LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc); 1024234353Sdim unsigned PhysReg = LRI->PhysReg; 1025208599Srdivacky if (setPhysReg(MI, i, PhysReg)) { 1026208599Srdivacky VirtDead.push_back(Reg); 1027208599Srdivacky CopyDst = 0; // cancel coalescing; 1028208599Srdivacky } else 1029208599Srdivacky CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0; 1030207618Srdivacky } 1031207618Srdivacky 1032208599Srdivacky // Kill dead defs after the scan to ensure that multiple defs of the same 1033208599Srdivacky // register are allocated identically. We didn't need to do this for uses 1034208599Srdivacky // because we are crerating our own kill flags, and they are always at the 1035208599Srdivacky // last use. 1036208599Srdivacky for (unsigned i = 0, e = VirtDead.size(); i != e; ++i) 1037208599Srdivacky killVirtReg(VirtDead[i]); 1038208599Srdivacky VirtDead.clear(); 1039207618Srdivacky 1040243830Sdim for (UsedInInstrSet::iterator 1041243830Sdim I = UsedInInstr.begin(), E = UsedInInstr.end(); I != E; ++I) 1042249423Sdim MRI->setRegUnitUsed(*I); 1043208599Srdivacky 1044208599Srdivacky if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) { 1045208599Srdivacky DEBUG(dbgs() << "-- coalescing: " << *MI); 1046208599Srdivacky Coalesced.push_back(MI); 1047208599Srdivacky } else { 1048208599Srdivacky DEBUG(dbgs() << "<< " << *MI); 1049207618Srdivacky } 1050207618Srdivacky } 1051207618Srdivacky 1052208599Srdivacky // Spill all physical registers holding virtual registers now. 1053208599Srdivacky DEBUG(dbgs() << "Spilling live registers at end of block.\n"); 1054208599Srdivacky spillAll(MBB->getFirstTerminator()); 1055207618Srdivacky 1056208599Srdivacky // Erase all the coalesced copies. We are delaying it until now because 1057208599Srdivacky // LiveVirtRegs might refer to the instrs. 1058208599Srdivacky for (unsigned i = 0, e = Coalesced.size(); i != e; ++i) 1059208599Srdivacky MBB->erase(Coalesced[i]); 1060208599Srdivacky NumCopies += Coalesced.size(); 1061208599Srdivacky 1062208599Srdivacky DEBUG(MBB->dump()); 1063207618Srdivacky} 1064207618Srdivacky 1065207618Srdivacky/// runOnMachineFunction - Register allocate the whole function 1066207618Srdivacky/// 1067207618Srdivackybool RAFast::runOnMachineFunction(MachineFunction &Fn) { 1068208599Srdivacky DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" 1069243830Sdim << "********** Function: " << Fn.getName() << '\n'); 1070207618Srdivacky MF = &Fn; 1071208599Srdivacky MRI = &MF->getRegInfo(); 1072207618Srdivacky TM = &Fn.getTarget(); 1073207618Srdivacky TRI = TM->getRegisterInfo(); 1074207618Srdivacky TII = TM->getInstrInfo(); 1075234353Sdim MRI->freezeReservedRegs(Fn); 1076223017Sdim RegClassInfo.runOnMachineFunction(Fn); 1077243830Sdim UsedInInstr.clear(); 1078249423Sdim UsedInInstr.setUniverse(TRI->getNumRegUnits()); 1079207618Srdivacky 1080234353Sdim assert(!MRI->isSSA() && "regalloc requires leaving SSA"); 1081234353Sdim 1082207618Srdivacky // initialize the virtual->physical register map to have a 'null' 1083207618Srdivacky // mapping for all virtual registers 1084218893Sdim StackSlotForVirtReg.resize(MRI->getNumVirtRegs()); 1085234353Sdim LiveVirtRegs.setUniverse(MRI->getNumVirtRegs()); 1086207618Srdivacky 1087207618Srdivacky // Loop over all of the basic blocks, eliminating virtual register references 1088208599Srdivacky for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end(); 1089208599Srdivacky MBBi != MBBe; ++MBBi) { 1090208599Srdivacky MBB = &*MBBi; 1091208599Srdivacky AllocateBasicBlock(); 1092208599Srdivacky } 1093207618Srdivacky 1094210299Sed // Add the clobber lists for all the instructions we skipped earlier. 1095224145Sdim for (SmallPtrSet<const MCInstrDesc*, 4>::const_iterator 1096210299Sed I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I) 1097234353Sdim if (const uint16_t *Defs = (*I)->getImplicitDefs()) 1098210299Sed while (*Defs) 1099210299Sed MRI->setPhysRegUsed(*Defs++); 1100210299Sed 1101234353Sdim // All machine operands and other references to virtual registers have been 1102234353Sdim // replaced. Remove the virtual registers. 1103234353Sdim MRI->clearVirtRegs(); 1104234353Sdim 1105210299Sed SkippedInstrs.clear(); 1106207618Srdivacky StackSlotForVirtReg.clear(); 1107212904Sdim LiveDbgValueMap.clear(); 1108207618Srdivacky return true; 1109207618Srdivacky} 1110207618Srdivacky 1111207618SrdivackyFunctionPass *llvm::createFastRegisterAllocator() { 1112207618Srdivacky return new RAFast(); 1113207618Srdivacky} 1114