LiveStackAnalysis.cpp revision 243830
1137817Srwatson//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===// 2137817Srwatson// 3172930Srwatson// The LLVM Compiler Infrastructure 4182063Srwatson// 5189503Srwatson// This file is distributed under the University of Illinois Open Source 6137817Srwatson// License. See LICENSE.TXT for details. 7137817Srwatson// 8137817Srwatson//===----------------------------------------------------------------------===// 9137817Srwatson// 10137817Srwatson// This file implements the live stack slot analysis pass. It is analogous to 11137817Srwatson// live interval analysis except it's analyzing liveness of stack slots rather 12137817Srwatson// than registers. 13172930Srwatson// 14172930Srwatson//===----------------------------------------------------------------------===// 15172930Srwatson 16189503Srwatson#define DEBUG_TYPE "livestacks" 17189503Srwatson#include "llvm/CodeGen/LiveStackAnalysis.h" 18189503Srwatson#include "llvm/CodeGen/LiveIntervalAnalysis.h" 19137817Srwatson#include "llvm/CodeGen/Passes.h" 20137817Srwatson#include "llvm/Target/TargetRegisterInfo.h" 21137817Srwatson#include "llvm/Support/Debug.h" 22137817Srwatson#include "llvm/Support/raw_ostream.h" 23137817Srwatson#include "llvm/ADT/Statistic.h" 24137817Srwatson#include <limits> 25137817Srwatsonusing namespace llvm; 26137817Srwatson 27137817Srwatsonchar LiveStacks::ID = 0; 28137817SrwatsonINITIALIZE_PASS_BEGIN(LiveStacks, "livestacks", 29137817Srwatson "Live Stack Slot Analysis", false, false) 30137817SrwatsonINITIALIZE_PASS_DEPENDENCY(SlotIndexes) 31137817SrwatsonINITIALIZE_PASS_END(LiveStacks, "livestacks", 32137817Srwatson "Live Stack Slot Analysis", false, false) 33137817Srwatson 34137817Srwatsonchar &llvm::LiveStacksID = LiveStacks::ID; 35137817Srwatson 36137817Srwatsonvoid LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const { 37137817Srwatson AU.setPreservesAll(); 38137817Srwatson AU.addPreserved<SlotIndexes>(); 39137817Srwatson AU.addRequiredTransitive<SlotIndexes>(); 40137817Srwatson MachineFunctionPass::getAnalysisUsage(AU); 41137817Srwatson} 42137817Srwatson 43137817Srwatsonvoid LiveStacks::releaseMemory() { 44189503Srwatson // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd. 45137817Srwatson VNInfoAllocator.Reset(); 46137817Srwatson S2IMap.clear(); 47137817Srwatson S2RCMap.clear(); 48137817Srwatson} 49137817Srwatson 50137817Srwatsonbool LiveStacks::runOnMachineFunction(MachineFunction &MF) { 51137817Srwatson TRI = MF.getTarget().getRegisterInfo(); 52137817Srwatson // FIXME: No analysis is being done right now. We are relying on the 53189503Srwatson // register allocators to provide the information. 54137817Srwatson return false; 55137817Srwatson} 56137817Srwatson 57137817SrwatsonLiveInterval & 58137817SrwatsonLiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { 59137817Srwatson assert(Slot >= 0 && "Spill slot indice must be >= 0"); 60137817Srwatson SS2IntervalMap::iterator I = S2IMap.find(Slot); 61137817Srwatson if (I == S2IMap.end()) { 62163606Srwatson I = S2IMap.insert(I, std::make_pair(Slot, 63137817Srwatson LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F))); 64165469Srwatson S2RCMap.insert(std::make_pair(Slot, RC)); 65137817Srwatson } else { 66137817Srwatson // Use the largest common subclass register class. 67137817Srwatson const TargetRegisterClass *OldRC = S2RCMap[Slot]; 68137817Srwatson S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 69137817Srwatson } 70137817Srwatson return I->second; 71137817Srwatson} 72172930Srwatson 73137817Srwatson/// print - Implement the dump method. 74137817Srwatsonvoid LiveStacks::print(raw_ostream &OS, const Module*) const { 75137817Srwatson 76137817Srwatson OS << "********** INTERVALS **********\n"; 77172930Srwatson for (const_iterator I = begin(), E = end(); I != E; ++I) { 78137817Srwatson I->second.print(OS); 79137817Srwatson int Slot = I->first; 80182063Srwatson const TargetRegisterClass *RC = getIntervalRegClass(Slot); 81182063Srwatson if (RC) 82182063Srwatson OS << " [" << RC->getName() << "]\n"; 83182063Srwatson else 84137817Srwatson OS << " [Unknown]\n"; 85137817Srwatson } 86137817Srwatson} 87137817Srwatson