LiveRegUnits.cpp revision 263508 
1//===-- LiveInterval.cpp - Live Interval Representation -------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LiveRegUnits utility for tracking liveness of
11// physical register units across machine instructions in forward or backward
12// order.
13//
14//===----------------------------------------------------------------------===//
15
16#include "llvm/CodeGen/LiveRegUnits.h"
17#include "llvm/CodeGen/MachineInstrBundle.h"
18using namespace llvm;
19
20/// Return true if the given MachineOperand clobbers the given register unit.
21/// A register unit is only clobbered if all its super-registers are clobbered.
22static bool operClobbersUnit(const MachineOperand *MO, unsigned Unit,
23                             const MCRegisterInfo *MCRI) {
24  for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
25    for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) {
26      if (!MO->clobbersPhysReg(*SI))
27        return false;
28    }
29  }
30  return true;
31}
32
33/// We assume the high bits of a physical super register are not preserved
34/// unless the instruction has an implicit-use operand reading the
35/// super-register or a register unit for the upper bits is available.
36void LiveRegUnits::removeRegsInMask(const MachineOperand &Op,
37                                    const MCRegisterInfo &MCRI) {
38  SparseSet<unsigned>::iterator LUI = LiveUnits.begin();
39  while (LUI != LiveUnits.end()) {
40    if (operClobbersUnit(&Op, *LUI, &MCRI))
41      LUI = LiveUnits.erase(LUI);
42    else
43      ++LUI;
44  }
45}
46
47void LiveRegUnits::stepBackward(const MachineInstr &MI,
48                                const MCRegisterInfo &MCRI) {
49  // Remove defined registers and regmask kills from the set.
50  for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
51    if (O->isReg()) {
52      if (!O->isDef())
53        continue;
54      unsigned Reg = O->getReg();
55      if (Reg == 0)
56        continue;
57      removeReg(Reg, MCRI);
58    } else if (O->isRegMask()) {
59      removeRegsInMask(*O, MCRI);
60    }
61  }
62  // Add uses to the set.
63  for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
64    if (!O->isReg() || !O->readsReg() || O->isUndef())
65      continue;
66    unsigned Reg = O->getReg();
67    if (Reg == 0)
68      continue;
69    addReg(Reg, MCRI);
70  }
71}
72
73/// Uses with kill flag get removed from the set, defs added. If possible
74/// use StepBackward() instead of this function because some kill flags may
75/// be missing.
76void LiveRegUnits::stepForward(const MachineInstr &MI,
77                               const MCRegisterInfo &MCRI) {
78  SmallVector<unsigned, 4> Defs;
79  // Remove killed registers from the set.
80  for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
81    if (O->isReg()) {
82      unsigned Reg = O->getReg();
83      if (Reg == 0)
84        continue;
85      if (O->isDef()) {
86        if (!O->isDead())
87          Defs.push_back(Reg);
88      } else {
89        if (!O->isKill())
90          continue;
91        assert(O->isUse());
92        removeReg(Reg, MCRI);
93      }
94    } else if (O->isRegMask()) {
95      removeRegsInMask(*O, MCRI);
96    }
97  }
98  // Add defs to the set.
99  for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
100    addReg(Defs[i], MCRI);
101  }
102}
103
104/// Adds all registers in the live-in list of block @p BB.
105void LiveRegUnits::addLiveIns(const MachineBasicBlock *MBB,
106                              const MCRegisterInfo &MCRI) {
107  for (MachineBasicBlock::livein_iterator L = MBB->livein_begin(),
108         LE = MBB->livein_end(); L != LE; ++L) {
109    addReg(*L, MCRI);
110  }
111}
112